INFINEON C161S User Manual

Data Sheet, V1.0, Nov. 2003

C161S

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2003-11 Published by Infineon Technologies AG,

St.-Martin-Strasse 53, 81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.

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circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).

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Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V1.0, Nov. 2003

C161S

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C161S

Revision History: 2003-11 V1.0

Previous Version: none Page Subjects (major changes since last revision)

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Template: mc_tmplt_a5.fm / 3 / 2003-09-01

C161S16-Bit Single-Chip Microcontroller

C166 Family

C161S

1 Summary of Features

• High Performance 16-bit CPU with 4-Stage Pipeline – 80 ns Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 Mbytes Total Linear Address Space for Code and Data – 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 30 Sources, Sample-Rate down to 40 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)

• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input

• On-Chip Memory Modules: 2 Kbytes On-Chip Internal RAM (IRAM)

• On-Chip Peripheral Modules – Two Multi-Functional General Purpose Timer Units with 5 Timers – Two Serial Channels (Sync./Asynchronous and High-Speed-Synchronous) – On-Chip Real Time Clock

• External Address Space for Code and Data – Programmable External Bus Characteristics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses with 8-bit or 16-bit

Data Bus Width – Four Programmable Chip-Select Signals – 4 Mbytes maximum address window size, results in a total external address space

of 16 Mbytes, when all chip-select signal (address windows) are active

• Idle and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

• Up to 63 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis

• Power Supply: the C161S can operate from a 5 V or a 3 V power supply (see Table 1)

• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 80-Pin MQFP Package

× 16 bit), 800 ns Division (32 / 16 bit)

Data Sheet 1 V1.0, 2003-11

C161S

Summary of Features

This document describes several derivatives of the C161 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product.

Table 1 C161S Derivative Synopsis Derivative Max. Operating

Frequency

SAB-C161S-L25M 25 MHz 4.5 to 5.5 V (Standard) 0 to 70 SAF-C161S-L25M 25 MHz 4.5 to 5.5 V (Standard) -40 to 85 SAB-C161S-LM3V 20 MHz 3.0 to 3.6 V (Reduced) 0 to 70 SAF-C161S-LM3V 20 MHz 3.0 to 3.6 V (Reduced) -40 to 85

Operating Voltage Ambient

Temperature

°C

For simplicity all versions are referred to by the term C161S throughout this document.

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the C161S please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet 2 V1.0, 2003-11

C161S

General Device Information

2 General Device Information

2.1 Introduction

The C161S is a derivative of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. It also provides clock generation via PLL and power management features. The C161S is especially suited for cost sensitive applications.

XTAL1

XTAL2

RSTIN

V

DD

V

SS

PORT0 16 bit

PORT1 16 bit

RSTOUT

NMI

EA

ALE

RD

WR/WRL Port 5

2 bit

Figure 1 Logic Symbol

Port 2 7 bit

C161S

Port 3 12 bit

Port 4 6 bit

Port 6 4 bit

MCA05504

Data Sheet 3 V1.0, 2003-11

C161S

2.2 Pin Configuration and Definition

P5.15/T2EUD

P5.14/T4EUD

P2.15/EX7IN

P2.14/EX6IN

P2.13/EX5IN

P2.11/EX3IN

V

SS

XTAL1 XTAL2

V

DD

P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD

P3.5/T4IN P3.6/T3IN

P3.7/T2IN P3.8/MRST P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19

P2.10/EX2IN

P2.12/EX4IN

80797877767574737271706968676665646362

160 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21222324252627282930313233343536373839

P6.3/CS3

P2.9/EX1IN

C161S

P6.2/CS2

General Device Information

SS

P6.1/CS1

P6.0/CS0

NMI

RSTOUT

DD

RSTIN

V

P1H.6/A14

P1H.7/A15

V

61

P1H.5/A13 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

P1H.4/A12

P1H.3/A11

P1H.2/A10

P1H.1/A9

P1H.0/A8

P1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

P0H.2/AD10

40

SS

DD

V

P4.4/A20

P4.5/A21

RD

WR/WRL

EA

ALE

P0L.0/AD0

P0L.1/AD1

P0L.4/AD4

P0L.5/AD5

P0L.2/AD2

P0L.3/AD3

P0L.6/AD6

SS

DD

V

P0L.7/AD7

P0H.0/AD8

P0H.1/AD9

MCP05505

Figure 2 Pin Configuration (top view)

Data Sheet 4 V1.0, 2003-11

C161S

Table 2 Pin Definitions and Functions Symbol Pin

No.

XTAL1

Input Outp.

I

Function

XTAL1: Input to the oscillator amplifier and input to the

internal clock generator

XTAL223

O

XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics (see Chapter 5.4) must be observed.

P3

IO

Port 3 is a 12-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/pull or open drain drivers.

The following Port 3 pins also serve for alternate functions: P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12

P3.13

5 6 7 8 9 10 11 12 13 14 15

16

I O I I I I I/O I/O O I/O O O I/O

CAPIN GPT2 Register CAPREL Capture Input

T3OUT GPT1 Timer T3 Toggle Latch Output

T3EUD GPT1 Timer T3 External Up/Down Control Input

T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp.

T3IN GPT1 Timer T3 Count/Gate Input

T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp.

MRST SSC Master-Receive/Slave-Transmit Inp./Outp.

MTSR SSC Master-Transmit/Slave-Receive Outp./Inp.

TxD0 ASC0 Clock/Data Output (Async./Sync.)

RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.)

BHE

WRH

External Memory High Byte Enable Signal, External Memory High Byte Write Strobe

SCLK SSC Master Clock Output / Slave Clock Input.

General Device Information

P4

IO

Port 4 is a 6-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state.

Port 4 can be used to output the segment address lines: P4.0 P4.1 P4.2 P4.3 P4.4 P4.5

Data Sheet 5 V1.0, 2003-11

17 18 19 20 23 24

O O O O O O

A16 Least Significant Segment Address Line

A17 Segment Address Line

A18 Segment Address Line

A19 Segment Address Line

A20 Segment Address Line

A21 Segment Address Line

C161S

General Device Information

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin

No.

Input Outp.

Function

RD 25 O External Memory Read Strobe. RD is activated for every

external instruction or data read access. WR

/

WRL

26 O External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL

-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection.

ALE 27 O Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the multiplexed bus modes.

EA

28 I External Access Enable pin. A low level at this pin during and

after Reset forces the C161S to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. “ROMless” versions must have this pin tied to ‘0’.

PORT0

P0L.0-7

P0H.0-7

29-36

39-46

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 – D7 P0H.0 – P0H.7: I/O D8 – D15

Multiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 – AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15

Data Sheet 6 V1.0, 2003-11

C161S

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin

No.

PORT1

P1L.0-7

47-54

Input

Function

Outp.

IO PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver

P1H.0-7

55-62

is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.

RSTIN

65 I/O Reset Input with Schmitt-Trigger characteristics. A low level

at this pin while the oscillator is running resets the C161S. An internal pull-up resistor permits power-on reset using only a capacitor connected to

V

SS

A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table.

General Device Information

.

line is internally pulled low

RST OUT

NMI

Note: To let the reset configuration of PORT0 settle and to

let the PLL lock a reset duration of approx. 1 ms is recommended.

66 O Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

67 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C161S to go into power down mode. If NMI

is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI

should be pulled high externally.

Data Sheet 7 V1.0, 2003-11

C161S

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin

No.

P6

Input Outp.

IO

Function

Port 6 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The Port 6 pins also serve for alternate functions:

P6.0 P6.1 P6.2 P6.3

P2

68 69 70 71

O O O O

IO

CS0 CS1 CS2 CS3

Chip Select 0 Output Chip Select 1 Output Chip Select 2 Output Chip Select 3 Output

Port 2 is a 7-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The following Port 2 pins also serve for alternate functions:

P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15

72 73 74 75 76 77 78

I I I I I I I

EX1IN Fast External Interrupt 1 Input EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input EX4IN Fast External Interrupt 4 Input EX5IN Fast External Interrupt 5 Input EX6IN Fast External Interrupt 6 Input EX7IN Fast External Interrupt 7 Input

General Device Information

P5

I

Port 5 is a 2-bit input-only port with Schmitt-Trigger char. The pins of Port 5 also serve as timer inputs:

P5.14 P5.15

V

DD

79 80

4, 22, 37, 64

I I

T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Input T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Input

– Digital Supply Voltage:

+ 5 V during normal operation and idle mode. + 3.3 V during reduced supply operation and idle mode.

≥ 2.5 V during power down mode.

Note: Please refer to the Operating Conditions Parameters.

V

SS

1, 21,

– Digital Ground.

38, 63

Data Sheet 8 V1.0, 2003-11

C161S

General Device Information

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is low.

•Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet 9 V1.0, 2003-11

C161S

Functional Description

3 Functional Description

The architecture of the C161S combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the onchip memory blocks allow the design of compact systems with maximum performance.

Figure 3 gives an overview of the different on-chip components and of the advanced,

high bandwidth internal bus structure of the C161S.

Note: All time specifications refer to a CPU clock of 20 MHz

(see definition in the AC Characteristics section).

ProgMem

Internal

ROM

Area

Instr. / Data

16

32

External Instr. / Data

Interrupt Controller

C166-Core

CPU

PEC

16-Level

Priority

Interrupt Bus

Peripheral Data Bus

Data

16

IRAM

Internal

RAM

Dual Port

2 Kbytes

Osc / PLL

RTC WDT

XTAL

On-Chip XBUS (16-Bit Demux)

6

Port 4

EBC

XBUS Control

ASC0

(USART)

SSC

(SPI)

External Bus

4

Port 6

Control

Port 0

16

Port 1

BRGen

12

GPT

T2

T3

T4

T5

T6

7

Port 2

Port 5Port 3

216

MCB04323_1S.vsd

Figure 3 Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are connected to the CPU via separate buses. A fourth bus, the XBUS, connects external resources as well as additional on-chip resources, the X-Peripherals (see Figure 3).

Data Sheet 10 V1.0, 2003-11

C161S

Functional Description

3.1 Memory Organization

The memory space of the C161S is configured in a von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 Mbytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.

The C161S is prepared to incorporate on-chip program memory (not in the ROM-less derivatives, of course) for code or constant data. The internal ROM area can be mapped either to segment 0 or segment 1.

2 Kbytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family.

× 512 bytes) of the address space are reserved for the Special Function

In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 Mbytes of external RAM and/or ROM can be connected to the microcontroller. The maximum contiguous external address space is 4 Mbytes, i.e. this is the maximum address window size. Using the chip-select lines (multiple windows) this results in a maximum usable external address space of 16 Mbytes.

Data Sheet 11 V1.0, 2003-11

C161S

Functional Description

3.2 External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows:

• 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed

• 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed

• 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed

• 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which control the access to different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 4 external CS external glue logic. The C161S offers the possibility to switch the CS unlatched mode. In this mode the internal filter logic is switched off and the CS are directly generated from the address. The unlatched CS CSCFG (SYSCON.6).

For applications which require less than 4 Mbytes of external memory space, this address space can be restricted to 1 Mbyte, 256 Kbytes, or to 64 Kbytes. In this case Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if the full address width is used.

signals (3 windows plus default) can be generated in order to save

outputs to an

signals

mode is enabled by setting

Data Sheet 12 V1.0, 2003-11

C161S

Functional Description

3.3 Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C161S’s instructions can be executed in just one machine cycle which requires 100 ns at 20 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16

× 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another

pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

SP

STKOV

STKUN

CPU

MDH MDL

R15

16

Internal

RAM

ROM

Exec. Unit

Instr. Ptr.

Instr. Reg.

32

4-Stage Pipeline

PSW

SYSCON

BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 4

Data Page Ptr. Code Seg. Ptr.

Mul/Div-HW

Bit-Mask Gen

ALU

(16-bit)

Barrel - Shifter

Context Ptr.

ADDRSEL 1 ADDRSEL 2 ADDRSEL 3

General

Purpose

Registers

R0

R15

R0

16

MCB02147

Figure 4 CPU Block Diagram

The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.

Data Sheet 13 V1.0, 2003-11

C161S

Functional Description

A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C161S instruction set which includes the following instruction classes:

• Arithmetic Instructions

• Logical Instructions

• Boolean Bit Manipulation Instructions

• Compare and Loop Control Instructions

• Shift and Rotate Instructions

• Prioritize Instruction

• Data Movement Instructions

• System Stack Instructions

• Jump and Call Instructions

• Return Instructions

• System Control Instructions

• Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.

Data Sheet 14 V1.0, 2003-11

C161S

Functional Description

3.3.1 Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C161S is capable of reacting very fast to the occurrence of non-deterministic events.

The architecture of the C161S supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C161S has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.

Table 3 shows all of the possible C161S interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt request bit (xIR).

Data Sheet 15 V1.0, 2003-11

C161S

Functional Description

Table 3 C161S Interrupt Nodes Source of Interrupt or

PEC Service Request

Request Flag

Enable Flag

Interrupt Vector

Vector Location

Unassigned node CC8IR CC8IE CC8INT 00’0060 External Interrupt 1 CC9IR CC9IE CC9INT 00’0064 External Interrupt 2 CC10IR CC10IE CC10INT 00’0068 External Interrupt 3 CC11IR CC11IE CC11INT 00’006C External Interrupt 4 CC12IR CC12IE CC12INT 00’0070 External Interrupt 5 CC13IR CC13IE CC13INT 00’0074 External Interrupt 6 CC14IR CC14IE CC14INT 00’0078 External Interrupt 7 CC15IR CC15IE CC15INT 00’007C GPT1 Timer 2 T2IR T2IE T2INT 00’0088 GPT1 Timer 3 T3IR T3IE T3INT 00’008C GPT1 Timer 4 T4IR T4IE T4INT 00’0090

H

Trap Number

18

H

19

H

1A

H

1B

H

1C

H

1D

H

1E

H

1F

H

22

H

23

H

24

H

GPT2 Timer 5 T5IR T5IE T5INT 00’0094 GPT2 Timer 6 T6IR T6IE T6INT 00’0098 GPT2 CAPREL Reg. CRIR CRIE CRINT 00’009C Unassigned node ADCIR ADCIE ADCINT 00’00A0 Unassigned node ADEIR ADEIE ADEINT 00’00A4 ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8 ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C ASC0 Receive S0RIR S0RIE S0RINT 00’00AC ASC0 Error S0EIR S0EIE S0EINT 00’00B0 SSC Transmit SCTIR SCTIE SCTINT 00’00B4 SSC Receive SCRIR SCRIE SCRINT 00’00B8 SSC Error SCEIR SCEIE SCEINT 00’00BC Unassigned node XP0IR XP0IE XP0INT 00’0100 Unassigned node XP1IR XP1IE XP1INT 00’0104 Unassigned node XP2IR XP2IE XP2INT 00’0108

25

H

26 27 28 29 2A 47 2B 2C 2D 2E 2F 40 41 42

H

PLL/OWD and RTC XP3IR XP3IE XP3INT 00’010C Unassigned node CC29IR CC29IE CC29INT 00’0110 Unassigned node CC30IR CC30IE CC30INT 00’0114 Unassigned node CC31IR CC31IE CC31INT 00’0118

43

H

44 45 46

H

Data Sheet 16 V1.0, 2003-11

C161S

Functional Description

The C161S also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4 Hardware Trap Summary Exception Condition Trap

Flag

Reset Functions:

–

• Hardware Reset

• Software Reset

• W-dog Timer Overflow

Trap Vector

RESET RESET RESET

Vector Location

00’0000 00’0000 00’0000

H H H

Trap Number

00

H

00

H

00

H

Trap Priority

III III III

Class A Hardware Traps:

• Non-Maskable Interrupt

• Stack Overflow

NMI STKOF STKUF

NMITRAP STOTRAP STUTRAP

00’0008 00’0010 00’0018

• Stack Underflow

Class B Hardware Traps:

• Undefined Opcode

• Protected Instruction

UNDOPC PRTFLT

BTRAP BTRAP

00’0028 00’0028

Fault

• Illegal Word Operand

ILLOPA

BTRAP

00’0028

Access

• Illegal Instruction

ILLINA

BTRAP

00’0028

Access

• Illegal External Bus

ILLBUS

BTRAP

00’0028

Access

Reserved – – [2C

3C

Software Traps

• TRAP Instruction

–– Any

[00’0000 00’01FC in steps of 4

H

]

H

–

02

H H H

H H

H

04 06

0A 0A

0A

[0B 0F

H H H

H H

H

–

H

]

H

Any [00

–

H

]

H

7F

–

H

]

H

II II II

I I

I

–

Current CPU Priority

Data Sheet 17 V1.0, 2003-11

C161S

Functional Description

3.4 General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.

Data Sheet 18 V1.0, 2003-11

C161S

T2EUD

T3EUD

T2IN

T3IN

CPU

Functional Description

U/D

2n : 1f

T2

Mode

Control

T3

Mode

Control

GPT1 Timer T2

Reload Capture

Toggle FF

GPT1 Timer T3 T3OTL

U/D

Interrupt Request

T3OUT

Other

Timers Capture Reload

T4IN

T4EUD

CPU

2n : 1f

T4

Mode

Control

GPT1 Timer T4

U/D

Interrupt

Request

MCT02141

n = 3 … 10

Figure 5 Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows the C161S to measure absolute time differences or to perform pulse multiplication without software overhead.

Data Sheet 19 V1.0, 2003-11

C161S

Functional Description

The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode.

f

SYS

T3IN/

CAPIN

2n: 1

T5

Mode

Control

MUX

CT3

GPT2 Timer T5

U/D

GPT2 CAPREL

Clear

Capture

Interrupt Request (T5IR)

Interrupt Request (CRIR)

Interrupt Request (T6IR)

f

SYS

2n: 1

T6

Mode

Control

n = 2 … 9

Figure 6 Block Diagram of GPT2

Clear

GPT2 Timer T6

U/D

Toggle FF

T6OTL

Mcb03999_x1s.vsd

Data Sheet 20 V1.0, 2003-11

C161S

Functional Description

3.5 Real Time Clock

The Real Time Clock (RTC) module of the C161S consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver ( therefore independent from the selected clock generation mode of the C161S. All timers count up.

The RTC module can be used for different purposes:

• System clock to determine the current time and date

• Cyclic time based interrupt

• 48-bit timer for long term measurements

T14REL

Reload

f

RTC

= f

/32) and is

OSC

f

T14 8:1

RTCLRTCH

RTC

Interrupt Request

MCD04432

Figure 7 RTC Block Diagram

Note: The registers associated with the RTC are not affected by a reset in order to

maintain the correct system time even when intermediate resets are executed.

Data Sheet 21 V1.0, 2003-11

C161S

Functional Description

3.6 Serial Channels

Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 625 kbit/s and half-duplex synchronous communication at up to 2.5 Mbit/s (@ 20 MHz CPU clock). A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake-up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 5 Mbit/s (@ 20 MHz CPU clock). It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception, and error handling three separate interrupt vectors are provided. The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data.

Data Sheet 22 V1.0, 2003-11

C161S

Functional Description

3.7 Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 (@ 20 MHz). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz).

µs and 420 ms can be monitored

pin low in order to allow

3.8 Parallel Ports

The C161S provides up to 63 I/O lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with them. All port lines that are not used for these alternate functions may be used as general purpose IO lines.

PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A21/19/17 … A16 in systems where segmentation is enabled to access more than 64 Kbytes of memory. Port 6 provides optional chip select signals. Port 3 includes alternate functions of timers, serial interfaces, and the optional bus control signal BHE Port 5 is used for timer control signals.

.

Data Sheet 23 V1.0, 2003-11

C161S

Functional Description

3.9 Oscillator Watchdog

The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and supplies the CPU with the PLL clock signal. Under these circumstances the PLL will oscillate with its basic frequency.

f

In direct drive mode the PLL base frequency is used directly ( In prescaler mode the PLL base frequency is divided by 2 (

f

CPU

Note: The CPU clock source is only switched back to the oscillator clock after a

hardware reset.

The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON. In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also no interrupt request will be generated in case of a missing oscillator clock.

= 2 … 5 MHz).

CPU

= 1 … 2.5 MHz).

Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD

Thus the oscillator watchdog may also be disabled via hardware by (externally) pulling the RD

line low upon a reset, similar to the standard reset configuration via

PORT0.

at that time.

Data Sheet 24 V1.0, 2003-11

C161S

Functional Description

3.10 Power Management

The C161S provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel):

• Power Saving Modes switch the C161S into a special operating mode (control via

instructions). Idle Mode stops the CPU while the peripherals can continue to operate. Power Down Mode stops all clock signals and all operation (RTC may optionally continue running).

• Clock Generation Management controls the distribution and the frequency of

internal and external clock signals (control via register SYSCON2). Slow Down Mode lets the C161S run at a CPU clock frequency of for prescaler operation) which drastically reduces the consumed power. The PLL can be optionally disabled while operating in Slow Down Mode.

• Peripheral Management permits temporary disabling of peripheral modules (control

via register SYSCON3). Each peripheral can separately be disabled/enabled. A group control option disables a major part of the peripheral set by setting one single bit.

f

/ 1 … 32 (half

OSC

The on-chip RTC supports intermittent operation of the C161S by generating cyclic wake-up signals. This offers full performance to quickly react on action requests while the intermittent sleep phases greatly reduce the average power consumption of the system.

Data Sheet 25 V1.0, 2003-11

C161S

Functional Description

3.11 Instruction Set Summary

Table 5 lists the instructions of the C161S in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the “C166 Family Instruction Set Manual”.

This document also provides a detailed description of each instruction.

Table 5 Instruction Set Summary Mnemonic Description Bytes

ADD(B) Add word (byte) operands 2 / 4 ADDC(B) Add word (byte) operands with Carry 2 / 4 SUB(B) Subtract word (byte) operands 2 / 4 SUBC(B) Subtract word (byte) operands with Carry 2 / 4 MUL(U) (Un)Signed multiply direct GPR by direct GPR (16DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

× 16-bit) 2

DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2 CPL(B) Complement direct word (byte) GPR 2 NEG(B) Negate direct word (byte) GPR 2 AND(B) Bitwise AND, (word/byte operands) 2 / 4 OR(B) Bitwise OR, (word/byte operands) 2 / 4 XOR(B) Bitwise XOR, (word/byte operands) 2 / 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV(N) Move (negated) direct bit to direct bit 4 BAND, BOR,

BXOR BCMP Compare direct bit to direct bit 4 BFLDH/L Bitwise modify masked high/low byte of bit-addressable

CMP(B) Compare word (byte) operands 2 / 4 CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4 CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4

AND/OR/XOR direct bit with direct bit 4

4

direct word memory with immediate data

PRIOR Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR SHL / SHR Shift left/right direct word GPR 2 ROL / ROR Rotate left/right direct word GPR 2 ASHR Arithmetic (sign bit) shift right direct word GPR 2

Data Sheet 26 V1.0, 2003-11

2

C161S

Functional Description

Table 5 Instruction Set Summary (cont’d) Mnemonic Description Bytes

MOV(B) Move word (byte) data 2 / 4 MOVBS Move byte operand to word operand with sign extension 2 / 4 MOVBZ Move byte operand to word operand with zero extension 2 / 4 JMPA, JMPI,

Jump absolute/indirect/relative if condition is met 4 JMPR

JMPS Jump absolute to a code segment 4 J(N)B Jump relative if direct bit is (not) set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI,

Call absolute/indirect/relative subroutine if condition is met 4 CALLR

CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call

4

absolute subroutine TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/from system stack 2 SCXT Push direct word register onto system stack and update

register with word operand RET Return from intra-segment subroutine 2 RETS Return from inter-segment subroutine 2 RETP Return from intra-segment subroutine and pop direct

word register from system stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode (supposes NMI

-pin being low) 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End-of-Initialization on RSTOUT

-pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2

4

2

EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4 EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4 NOP Null operation 2

Data Sheet 27 V1.0, 2003-11

C161S

Functional Description

3.12 Special Function Registers Overview

Table 6 lists all SFRs which are implemented in the C161S in alphabetical order. The

following markings assist in classifying the listed registers:

“b” in the “Name” column marks Bit-addressable SFRs. “E” in the “Physical Address” column marks (E)SFRs in the Extended SFR-Space. “X” in the “Physical Address” column marks registers within on-chip X-peripherals.

Table 6 C161S Registers, Ordered by Name Name Physical

Address ADCIC b FF98 ADDRSEL1 FE18 ADDRSEL2 FE1A ADDRSEL3 FE1C ADDRSEL4 FE1E

H

8-Bit Addr.

CC

H

0C

H

0D

H

0E

H

0F

H

Description Reset

Value

Software Interrupt Control Register 0000 Address Select Register 1 0000 Address Select Register 2 0000 Address Select Register 3 0000 Address Select Register 4 0000

H

ADEIC b FF9A BUSCON0 b FF0C BUSCON1 b FF14 BUSCON2 b FF16 BUSCON3 b FF18 BUSCON4 b FF1A CAPREL FE4A CC10IC b FF8C CC11IC b FF8E CC12IC b FF90 CC13IC b FF92 CC14IC b FF94 CC15IC b FF96 CC29IC b F184

H

CD 86 8A 8B 8C 8D 25 C6 C7 C8 C9 CA CB

E C2

CC30IC b F18CHE C6

Software Interrupt Control Register 0000

H

Bus Configuration Register 0 0XX0

H

Bus Configuration Register 1 0000

H

Bus Configuration Register 2 0000

H

Bus Configuration Register 3 0000

H

Bus Configuration Register 4 0000

H

GPT2 Capture/Reload Register 0000

H

EX2IN Interrupt Control Register 0000

H

EX3IN Interrupt Control Register 0000

H

EX4IN Interrupt Control Register 0000

H

EX5IN Interrupt Control Register 0000

H

EX6IN Interrupt Control Register 0000

H

EX7IN Interrupt Control Register 0000

H

Software Interrupt Control Register 0000

H

Software Interrupt Control Register 0000

H

CC31IC b F194 CC8IC b FF88 CC9IC b FF8A

H

E CA

C4 C5

Software Interrupt Control Register 0000

H

Software Interrupt Control Register 0000

H

EX1IN Interrupt Control Register 0000

H

Data Sheet 28 V1.0, 2003-11

C161S

Table 6 C161S Registers, Ordered by Name (cont’d) Name Physical

Address CP FE10 CRIC b FF6A CSP FE08 DP0H b F102 DP0L b F100 DP1H b F106 DP1L b F104 DP2 b FFC2 DP3 b FFC6 DP4 b FFCA DP6 b FFCE

H

8-Bit Addr.

08 B5 04

E 81 E 80 E 83 E 82

E1 E3 E5 E7

Description Reset

CPU Context Pointer Register FC00

H

GPT2 CAPREL Interrupt Ctrl. Reg. 0000

H

CPU Code Seg. Pointer Reg. (read only) 0000

H

P0H Direction Control Register 00

H

P0L Direction Control Register 00

H

P1H Direction Control Register 00

H

P1L Direction Control Register 00

H

Port 2 Direction Control Register 0000

H

Port 3 Direction Control Register 0000

H

Port 4 Direction Control Register 00

H

Port 6 Direction Control Register 00

H

Functional Description

Value

H

DPP0 FE00 DPP1 FE02 DPP2 FE04 DPP3 FE06

H

00 01 02 03

EXICON b F1C0HE E0 IDCHIP F07CHE 3E IDMANUF F07EHE 3F IDMEM F07AHE 3D IDMEM2 F076 IDPROG F078

H

E 3B

E 3C ISNC b F1DEHE EF MDC b FF0E MDH FE0C MDL FE0E

H

87 06 07

ODP2 b F1C2HE E1

CPU Data Page Pointer 0 Reg. (10 bits) 0000

H

CPU Data Page Pointer 1 Reg. (10 bits) 0001

H

CPU Data Page Pointer 2 Reg. (10 bits) 0002

H

CPU Data Page Pointer 3 Reg. (10 bits) 0003

H

External Interrupt Control Register 0000

H

Identifier 05XX

H

Identifier 1820

H

Identifier 0000

H

Identifier 0000

H

Identifier 0000

H

Interrupt Subnode Control Register 0000

H

CPU Multiply Divide Control Register 0000

H

CPU Multiply Divide Reg. – High Word 0000

H

CPU Multiply Divide Reg. – Low Word 0000

H

Port 2 Open Drain Control Register 0000

H

ODP3 b F1C6HE E3 ODP6 b F1CEHE E7 ONES b FF1E P0H b FF02

H

8F 81

Port 3 Open Drain Control Register 0000

H

Port 6 Open Drain Control Register 00

H

Constant Value 1’s Register (read only) FFFF

H

Port 0 High Reg. (Upper half of PORT0) 00

H

Data Sheet 29 V1.0, 2003-11

C161S

Table 6 C161S Registers, Ordered by Name (cont’d) Name Physical

Address P0L b FF00 P1H b FF06 P1L b FF04 P2 b FFC0 P3 b FFC4 P4 b FFC8 P5 b FFA2 P6 b FFCC PECC0 FEC0 PECC1 FEC2 PECC2 FEC4

H

8-Bit Addr.

80

H

83

H

82

H

E0

H

E2

H

E4

H

D1

H

E6

H

60

H

61

H

62

H

Description Reset

Port 0 Low Reg. (Lower half of PORT0) 00 Port 1 High Reg. (Upper half of PORT1) 00 Port 1 Low Reg.(Lower half of PORT1) 00 Port 2 Register 0000 Port 3 Register 0000 Port 4 Register (8 bits) 00 Port 5 Register (read only) XXXX Port 6 Register (8 bits) 00 PEC Channel 0 Control Register 0000 PEC Channel 1 Control Register 0000 PEC Channel 2 Control Register 0000

Functional Description

Value

H

PECC3 FEC6 PECC4 FEC8 PECC5 FECA PECC6 FECC PECC7 FECE PSW b FF10 RP0H b F108

H

63 64 65 66 67 88

E 84 RTCH F0D6HE 6B RTCL F0D4HE 6A S0BG FEB4

S0CON b FFB0 S0EIC b FF70 S0RBUF FEB2

H

5A

D8 B8 59

PEC Channel 3 Control Register 0000

H

PEC Channel 4 Control Register 0000

H

PEC Channel 5 Control Register 0000

H

PEC Channel 6 Control Register 0000

H

PEC Channel 7 Control Register 0000

H

CPU Program Status Word 0000

H

System Startup Config. Reg. (Rd. only) XX

H

RTC High Register XXXX

H

RTC Low Register XXXX

H

Serial Channel 0 Baud Rate Generator

H

Reload Register Serial Channel 0 Control Register 0000

H

Serial Channel 0 Error Interrupt Ctrl. Reg 0000

H

Serial Channel 0 Receive Buffer Reg.

H

(read only)

0000

XX

H

S0RIC b FF6E

H

B7

Serial Channel 0 Receive Interrupt

H

0000

H

Control Register

S0TBIC b F19CHE CE

Serial Channel 0 Transmit Buffer

H

0000

H

Interrupt Control Register

Data Sheet 30 V1.0, 2003-11

C161S

Table 6 C161S Registers, Ordered by Name (cont’d) Name Physical

Address

S0TBUF FEB0

H

8-Bit Addr.

58

H

Description Reset

Serial Channel 0 Transmit Buffer Register (write only)

S0TIC b FF6C

H

B6

Serial Channel 0 Transmit Interrupt

H

Control Register

SP FE12

H

SSCBR F0B4HE 5A SSCCON b FFB2 SSCEIC b FF76

H

SSCRB F0B2HE 59 SSCRIC b FF74

H

SSCTB F0B0HE 58

09

D9 BB

BA

CPU System Stack Pointer Register FC00

H

SSC Baudrate Register 0000

H

SSC Control Register 0000

H

SSC Error Interrupt Control Register 0000

H

SSC Receive Buffer XXXX

H

SSC Receive Interrupt Control Register 0000

H

SSC Transmit Buffer 0000

H

Functional Description

Value

00

H

0000

H

SSCTIC b FF72 STKOV FE14 STKUN FE16 SYSCON b FF12

H

B9 0A 0B 89

SYSCON2 b F1D0HE E8 SYSCON3 b F1D4HE EA T14 F0D2HE 69 T14REL F0D0HE 68 T2 FE40 T2CON b FF40 T2IC b FF60 T3 FE42 T3CON b FF42 T3IC b FF62 T4 FE44

H

20 A0 B0 21 A1 B1 22

SSC Transmit Interrupt Control Register 0000

H

CPU Stack Overflow Pointer Register FA00

H

CPU Stack Underflow Pointer Register FC00

H

CPU System Configuration Register

H

CPU System Configuration Register 2 0000

H

CPU System Configuration Register 3 0000

H

RTC Timer 14 Register XXXX

H

RTC Timer 14 Reload Register XXXX

H

GPT1 Timer 2 Register 0000

H

GPT1 Timer 2 Control Register 0000

H

GPT1 Timer 2 Interrupt Control Register 0000

H

GPT1 Timer 3 Register 0000

H

GPT1 Timer 3 Control Register 0000

H

GPT1 Timer 3 Interrupt Control Register 0000

H

GPT1 Timer 4 Register 0000

H

1)

0XX0

H

T4CON b FF44 T4IC b FF64 T5 FE46 T5CON b FF46

H

A2 B2 23 A3

GPT1 Timer 4 Control Register 0000

H

GPT1 Timer 4 Interrupt Control Register 0000

H

GPT2 Timer 5 Register 0000

H

GPT2 Timer 5 Control Register 0000

H

Data Sheet 31 V1.0, 2003-11

C161S

Table 6 C161S Registers, Ordered by Name (cont’d) Name Physical

Address T5IC b FF66 T6 FE48 T6CON b FF48 T6IC b FF68 TFR b FFAC WDT FEAE WDTCON b FFAE XP0IC b F186

H

XP1IC b F18EHE C7 XP2IC b F196

H

XP3IC b F19EHE CF

8-Bit Addr.

B3 24 A4 B4 D6 57 D7

E C3

E CB

Description Reset

GPT2 Timer 5 Interrupt Control Register 0000

H

GPT2 Timer 6 Register 0000

H

GPT2 Timer 6 Control Register 0000

H

GPT2 Timer 6 Interrupt Control Register 0000

H

Trap Flag Register 0000

H

Watchdog Timer Register (read only) 0000

H

Watchdog Timer Control Register

H

Software Interrupt Control Register 0000

H

Software Interrupt Control Register 0000

H

Software Interrupt Control Register 0000

H

RTC/PLL Interrupt Control Register 0000

H

Functional Description

Value

H

2)

00XX

H

ZEROS b FF1C

1) The system configuration is selected during reset.

2) The reset value depends on the indicated reset source.

H

8E

Constant Value 0’s Register (read only) 0000

H

Data Sheet 32 V1.0, 2003-11

C161S

Electrical Parameters

4 Electrical Parameters

4.1 Absolute Maximum Ratings

Table 7 Absolute Maximum Rating Parameters Parameter Symbol Limit Values Unit Notes

Min. Max.

Storage temperature Junction temperature

V

Voltage on respect to ground (

pins with

DD

V

SS

)

Voltage on any pin with respect to ground (

V

SS

)

Input current on any pin during overload condition

T T V

V

I

ST

J

DD

IN

OV

-65 150 °C –

-40 150 °C under bias

-0.5 6.5 V –

-0.5 VDD + 0.5 V –

-10 10 mA –

Absolute sum of all input

Σ|I

| – 100 mA –

OV

currents during overload condition

Power dissipation

P

DISS

– 1.5 W –

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

V

During absolute maximum rating overload conditions ( voltage on

V

pins with respect to ground (VSS) must not exceed the values

DD

> VDD or VIN < VSS) the

IN

defined by the absolute maximum ratings.

Data Sheet 33 V1.0, 2003-11

C161S

Electrical Parameters

4.2 Operating Conditions

The following operating conditions must not be exceeded in order to ensure correct operation of the C161S. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed.

Table 8 Operating Condition Parameters Parameter Symbol Limit Values Unit Notes

Min. Max.

Standard digital supply voltage

Reduced digital supply voltage

Digital ground voltage Overload current Absolute sum of overload

currents

V

DD

V

DD

V

SS

I

OV

Σ|I

| – 50 mA

OV

4.5 5.5 V Active mode,

2.5

1)

5.5 V Power down mode

3.0 3.6 V Active mode,

2.5

1)

3.6 V Power down mode

0 V Reference voltage – ±5 mA Per pin

f

CPUmax

f

CPUmax

3)

= 25 MHz

= 20 MHz

2)3)

External Load

C

L

– 100 pF –

Capacitance Ambient temperature

1) Output voltages and output currents will be reduced when VDD leaves the range defined for active mode.

2) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e. currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits. Proper operation is not guaranteed if overload conditions occur on functional pins such as XTAL1, RD etc.

3) Not subject to production test, verified by design/characterization.

T

A

V

> VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload

OV

070°C SAB-C161S …

-40 85

-40 125

°C SAF-C161S … °C SAK-C161S …

, WR,

Data Sheet 34 V1.0, 2003-11

C161S

Electrical Parameters

4.3 Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C161S and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics): The logic of the C161S will provide signals with the respective timing characteristics.

SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C161S.

Data Sheet 35 V1.0, 2003-11

C161S

Electrical Parameters

4.4 DC Parameters

Table 9 DC Characteristics (Standard Supply Voltage Range)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

Input low voltage (TTL,

V

IL

all except XTAL1) Input low voltage XTAL1 Input high voltage (TTL,

all except RSTIN

and XTAL1) Input high voltage RSTIN

V V

V

IL2

IH

IH1

(when operated as input) Input high voltage XTAL1

V

IH2

1)

Min. Max.

SR -0.5 0.2 VDD

- 0.1

SR -0.5 0.3 V SR 0.2 VDD

+ 0.9

SR 0.6 V

DDVDD

V

DD

0.5

DD

+

0.5

SR 0.7 V

DDVDD

+

0.5

V –

V – V –

V –

Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, RSTOUT, RSTIN

2)

)

Output low voltage (all other outputs)

Output high voltage

3)

(PORT0, PORT1, Port 4, ALE,

, WR, BHE, RSTOUT)

RD Output high voltage

3)

(all other outputs)

Input leakage current (Port 5) Input leakage current (all other) I RSTIN inactive current RSTIN active current RD/WR inactive current

/WR active current

RD ALE inactive current ALE active current Port 6 inactive current

4)

7)

V

OL

V

OL1

V

OH

V

OH1

I

OZ1

OZ2

I

RSTH

I

RSTL

I

RWH

I

RWL

I

ALEL

I

ALEH

I

P6H

CC – 0.45 V IOL = 2.4 mA

CC – 0.45 V IOL = 1.6 mA

CC 2.4 – V IOH = -2.4 mA

V

0.9

– V IOH = -0.5 mA

DD

CC 2.4 – V IOH = -1.6 mA

V

0.9

– V IOH = -0.5 mA

DD

CC – ±200 nA 0 V < VIN < V CC – ±500 nA 0.45 V < VIN < V

5)

6)

5)

6)

5)

6)

5)

– -10 µA VIN = V

-100 – µA VIN = V – -40 µA V

-500 – µA V – 40 µA V 500 – µA V – -40 µA V

OUT

= 2.4 V = V = V = 2.4 V = 2.4 V

IH1

IL

OLmax

DD

Data Sheet 36 V1.0, 2003-11

C161S

Electrical Parameters

Table 9 DC Characteristics (Standard Supply Voltage Range) (cont’d)

(Operating Conditions apply)

1)

Parameter Symbol Limit Values Unit Test Condition

Min. Max.

Port 6 active current PORT0 configuration current

7)

XTAL1 input current I Pin capacitance

8)

(digital inputs/outputs)

1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.

For signal levels outside these specifications also refer to the specification of the overload current

2) Valid in bidirectional reset mode only.

3) This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

4) These parameters describe the RSTIN

5) The maximum current may be drawn while the respective signal line remains inactive.

6) The minimum current must be drawn in order to drive the respective signal line active.

7) This specification is only valid during Reset and Adapt Mode.

8) Not subject to production test, verified by design/characterization.

6)

I

P6L

5)

I

P0H

6)

I

P0L

IL

C

IO

pull-up, which equals a resistance of ca. 50 to 250 kΩ.

-500 – µA V

OUT

= V

– -10 µA VIN = V

-100 – µA VIN = V

CC – ±20 µA0 V < VIN < V CC – 10 pF f = 1 MHz,

T

= 25 °C

A

OL1max

IHmin

ILmax

DD

I

.

OV

Data Sheet 37 V1.0, 2003-11

C161S

Electrical Parameters

Table 10 DC Characteristics (Reduced Supply Voltage Range)

(Operating Conditions apply)

1)

Parameter Symbol Limit Values Unit Test Condition

Min. Max.

Input low voltage (TTL,

V

SR -0.5 0.8 V –

IL

all except XTAL1) Input low voltage XTAL1 Input high voltage (TTL,

all except RSTIN

and XTAL1) Input high voltage RSTIN

(when operated as input) Input high voltage XTAL1

V V

V

SR -0.5 0.3 V

IL2

SR 1.8 VDD +

IH

SR 0.6 V

IH1

SR 0.7 V

IH2

0.5

DDVDD

0.5

DDVDD

+

DD

V – V –

V –

0.5

Output low voltage

V

CC – 0.45 V IOL = 1.6 mA

OL

(PORT0, PORT1, Port 4, ALE, RD

, WR, BHE, RSTOUT,

2)

RSTIN

)

Output low voltage (all other outputs)

Output high voltage

3)

(PORT0, PORT1, Port 4, ALE,

, WR, BHE, RSTOUT)

RD Output high voltage

3)

(all other outputs) Input leakage current (Port 5) Input leakage current (all other) I RSTIN inactive current RSTIN active current RD/WR inactive current

/WR active current

RD ALE inactive current ALE active current Port 6 inactive current Port 6 active current

4)

7)

V

OL1

V

OH

V

OH1

I

OZ1

OZ2

I

RSTH

I

RSTL

I

RWH

I

RWL

I

ALEL

I

ALEH

I

P6H

I

P6L

CC – 0.45 V IOL = 1.0 mA

CC 0.9 V

– V IOH = -0.5 mA

DD

– V IOH = -0.25 mA

DD

CC – ±200 nA 0 V < VIN < V CC – ±500 nA 0.45 V < VIN < V

5)

6)

5)

6)

5)

6)

5)

6)

– -10 µA VIN = V

-100 – µA VIN = V – -10 µA V

-500 – µA V – 20 µA V 500 – µA V – -10 µA V

-500 – µA V

OUT

= 2.4 V = V = V = 2.4 V = 2.4 V = V

IH1

IL

OLmax

OL1max

DD

Data Sheet 38 V1.0, 2003-11

C161S

Electrical Parameters

Table 10 DC Characteristics (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

1)

Parameter Symbol Limit Values Unit Test Condition

Min. Max.

PORT0 configuration current

7)

XTAL1 input current I Pin capacitance

8)

(digital inputs/outputs)

1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions.

For signal levels outside these specifications also refer to the specification of the overload current

2) Valid in bidirectional reset mode only.

3) This specification is not valid for outputs which are switched to open drain mode. In this case the respective

output will float and the voltage results from the external circuitry.

4) These parameters describe the RSTIN

5) The maximum current may be drawn while the respective signal line remains inactive.

6) The minimum current must be drawn in order to drive the respective signal line active.

7) This specification is only valid during Reset and Adapt Mode.

8) Not subject to production test, verified by design/characterization.

5)

I

P0H

6)

I

P0L

IL

C

IO

pull-up, which equals a resistance of ca. 50 to 250 kΩ.

– -5 µA VIN = V

-100 – µA VIN = V

CC – ±20 µA0 V < VIN < V CC – 10 pF f = 1 MHz,

T

= 25 °C

A

IHmin

ILmax

DD

I

.

OV

Data Sheet 39 V1.0, 2003-11

C161S

Electrical Parameters

Table 11 Power Consumption C161S (Standard Supply Voltage Range)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

Min. Max.

Power supply current (active) with all peripherals active

Idle mode supply current with all peripherals active

Idle mode supply current with all peripherals deactivated,

I

DD5

I

IDX5

I

IDO5

– 15 +

× f

1.8

– 3 +

× f

0.6

2)

– 500 +

× f

50

mA RSTIN = V

CPU

mA RSTIN = V

CPU

µARSTIN = V

OSC

f

CPU

f

CPU

f

OSC

IL2

in [MHz]

IH1

in [MHz]

IH1

in [MHz]

1)

PLL off, SDD factor = 32 Sleep and Power down mode

supply current with RTC running Sleep and Power down mode

I

PDR5

I

PDO5

2)

– 200 +

× f

25

OSC

µA V

f

OSC

DD

= V

in [MHz]

– 50 µA VDD = V

DDmax

3)

supply current with RTC disabled

1) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 8.

V

These parameters are tested at

V

or VIH.

at

IL

2) This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current,

however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.

3) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at

V

- 0.1 V to VDD, V

DD

REF

and maximum CPU clock with all outputs disconnected and all inputs

DDmax

= 0 V, all outputs (including pins configured as outputs) disconnected.

Data Sheet 40 V1.0, 2003-11

C161S

Electrical Parameters

Table 12 Power Consumption C161S (Reduced Supply Voltage Range)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

Min. Max.

Power supply current (active) with all peripherals active

Idle mode supply current with all peripherals active

Idle mode supply current with all peripherals deactivated,

I

DD3

I

IDX3

I

IDO3

– 7 +

× f

1.2

– 1 +

× f

0.4

2)

– 300 +

× f

30

mA RSTIN = V

CPU

mA RSTIN = V

CPU

µARSTIN = V

OSC

f

CPU

f

CPU

f

OSC

IL2

in [MHz]

IH1

in [MHz]

IH1

in [MHz]

1)

PLL off, SDD factor = 32 Sleep and Power down mode

supply current with RTC running Sleep and Power down mode

I

PDR3

I

PDO3

2)

– 100 +

× f

10

OSC

µA V

f

OSC

DD

= V

in [MHz]

– 30 µA VDD = V

DDmax

3)

supply current with RTC disabled

1) The supply current is a function of the operating frequency. This dependency is illustrated in Figure 8.

V

These parameters are tested at

V

or VIH.

at

IL

2) This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current,

however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry.

3) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to

0.1 V or at

V

- 0.1 V to VDD, V

DD

REF

and maximum CPU clock with all outputs disconnected and all inputs

DDmax

= 0 V, all outputs (including pins configured as outputs) disconnected.

Data Sheet 41 V1.0, 2003-11

C161S

I [mA]

100

80

60

Electrical Parameters

I

DD5max

I

DD5typ

I

DD3max

I

DD3typ

40

I

IDX5max

I

IDX5typ

20

10 20 30 40

I

IDX3max

I

IDX3typ

f

CPU

[MHz]

Figure 8 Supply and Idle Current as a Function of Operating Frequency

Data Sheet 42 V1.0, 2003-11

C161S

3000

2500

1500

I [µA]

Electrical Parameters

I

IDO5max

I

IDO5typ

I

IDO3max

I

IDO3typ

I

PDR5max

1000

I

500

10 20 30 40

PDR3max

f

OSC

I

PDOmax

[MHz]

Figure 9 Sleep and Power Down Supply Current as a Function of Oscillator

Frequency

Data Sheet 43 V1.0, 2003-11

C161S

Timing Characteristics

5 Timing Characteristics

5.1 Definition of Internal Timing

The internal operation of the C161S is controlled by the internal CPU clock f edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations.

The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see Figure 10).

Phase Locked Loop Operation

f

OSC

TCL

f

CPU

. Both

TCL

Direct Clock Drive

f

OSC

TCL

f

CPU

TCL

Prescaler Operation

f

OSC

TCL

f

CPU

TCL

MCT04338

Figure 10 Generation Mechanisms for the CPU Clock

The CPU clock signal

f

can be generated from the oscillator clock signal f

CPU

OSC

via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate

f

. This influence must

CPU

be regarded when calculating the timings for the C161S.

Note: The example for PLL operation shown in Figure 10 refers to a PLL factor of 4.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic

Data Sheet 44 V1.0, 2003-11

C161S

Timing Characteristics

levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins P0.15-13 (P0H.7-5).

Table 13 associates the combinations of these three bits with the respective clock

generation mode.

Table 13 C161S Clock Generation Modes CLKCFG

(P0H.7-5)

1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 f

CPU Frequency

f

= f

CPU

f

× 4 2.5 to 6.25 MHz Default configuration

OSC

f

× 3 3.33 to 8.33 MHz –

OSC

f

× 2 5 to 12.5 MHz –

OSC

f

× 5 2 to 5 MHz –

OSC

f

× 1 1 to 25 MHz Direct drive

OSC

× 1.5 6.66 to 16.67 MHz –

OSC

× F

External Clock Input Range

1)

Notes

2)

f

0 0 1 0 0 0

1) The external clock input range refers to a CPU clock range of 10 … 25 MHz (PLL operation). If the on-chip

oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 16 MHz.

2) The maximum frequency depends on the duty cycle of the external clock signal.

/ 2 2 to 50 MHz CPU clock via prescaler

OSC

f

× 2.5 4 to 10 MHz –

OSC

Prescaler Operation

When prescaler operation is configured (CLKCFG = 001

) the CPU clock is derived from

B

the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of the duration of an individual TCL) is defined by the period of the input clock

f

is half the frequency of f

CPU

and the high and low time of f

OSC

f

OSC

CPU

.

(i.e.

The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of

f

for any TCL.

OSC

Phase Locked Loop

When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is enabled and provides the CPU clock (see Table 13). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. = f

× F). With every F’th transition of f

OSC

the PLL circuit synchronizes the CPU clock

OSC

f

CPU

to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly.

Due to this adaptation to the input clock the frequency of

f

it is locked to

. The slight variation causes a jitter of f

OSC

f

is constantly adjusted so

CPU

which also effects the

CPU

duration of individual TCLs.

Data Sheet 45 V1.0, 2003-11

C161S

Timing Characteristics

The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and Figure 11). For a period of N deviation D

× TCL)

(N

:

N

= N × TCL

min

where N = number of consecutive TCLs and 1 So for a period of 3 TCLs @ 20 MHz (i.e. N = 3): D

and (3TCL)

= 3TCL

min

× TCL the minimum value is computed using the corresponding

- DN, DN [ns] = ±(13.3 + N × 6.3) / f

NOM

[MHz] (1)

CPU

≤ N ≤ 40.

= (13.3 + 3 × 6.3) / 20 = 1.61 ns,

3

- 1.61 ns = 73.39 ns (@ f

NOM

= 20 MHz).

CPU

This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible.

Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 11).

Max. jitter

D

ns

±30

±26.5

±20

±10

±1

N

This approximated formula is valid for

<

N

40 and 10 MHz f

1

–

110 20 40

<

–

CPU

<

25 MHz.

–

30

10 MHz

16 MHz

20 MHz

25 MHz

N

MCD04455

Figure 11 Approximated Maximum Accumulated PLL Jitter

Data Sheet 46 V1.0, 2003-11

C161S

Timing Characteristics

Direct Drive

When direct drive is configured (CLKCFG = 011

) the on-chip phase locked loop is

B

disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of

f

(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock

CPU

f

.

OSC

f

directly follows the frequency of f

CPU

so the high and low time of

OSC

The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula:

TCL

For two consecutive TCLs the deviation caused by the duty cycle of so the duration of 2TCL is always 1/

min

= 1/f

OSC

× DC

(DC = duty cycle) (2)

min

f

is compensated

OSC

f

. The minimum value TCL

OSC

therefore has to be

min

used only once for timings that require an odd number of TCLs (1, 3, …). Timings that

f

require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/

OSC

.

Data Sheet 47 V1.0, 2003-11

C161S

Timing Characteristics

5.2 External Clock Drive XTAL1

Table 14 External Clock Drive XTAL1 (Operating Conditions apply) Parameter Symbol Direct Drive

1:1

Min. Max. Min. Max. Min. Max.

Oscillator

t

OSC

SR 40 – 20 – 60

period High time Low time Rise time Fall time

1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock

generation mode. Please see respective table above.

2) The clock input signal must reach the defined levels V

3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (f

direct drive mode depends on the duty cycle of the clock input signal.

2)

t t t t

SR 20

1

SR 20

2

SR – 8 – 5 – 10 ns

3

SR – 8 – 5 – 10 ns

4

3)

– 5 – 10 – ns – 5 – 10 – ns

and V

IL2

Prescaler

2:1

.

IH2

PLL

Unit

1:N

1)

500

1)

ns

) in

CPU

t

1

VDD0.5

t

2

t

3

OSC

t

4

MCT02534

V

IH2

V

IL

Figure 12 External Clock Drive XTAL1

Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is

limited to a range of 4 MHz to 16 MHz. It is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is verified by design only (not tested in production).

Data Sheet 48 V1.0, 2003-11

C161S

5.3 Testing Waveforms

2.4 V

0.45 V

AC inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’. Timing measurements are made at

Figure 13 Input Output Waveforms

1.8 V

0.8 V

V

min for a logic 1’ and

IH

Test Points

’ ’’

1.8 V

0.8 V

V

max for a logic 0’.

IL

Timing Characteristics

’

MCA04414

+ 0.1 V

V

Load

V

- 0.1 V

Load

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded

Figure 14 Float Waveforms

Timing

Reference

Points

- 0.1 V

V

OH

V

+ 0.1 V

OL

V

/

V

OH

level occurs (

OL

I

/ = 20 mA).

OH OL

MCA00763

Data Sheet 49 V1.0, 2003-11

C161S

Timing Characteristics

Memory Cycle Variables

The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle.

Table 15 describes, how these variables are to be computed.

Table 15 Memory Cycle Variables Description Symbol Values

ALE Extension Memory Cycle Time Waitstates Memory Tristate Time

t

A

t

C

t

F

TCL × <ALECTL> 2TCL × (15 - <MCTC>) 2TCL × (1 - <MTTC>)

Note: Please respect the maximum operating frequency of the respective derivative.

5.4 AC Characteristics

Table 16 Multiplexed Bus (Standard Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2

Parameter Symbol Max. CPU Clock

t

+ tC + tF (120 ns at 25 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 25 MHz

1 / 2TCL = 1 to 25 MHz

Min. Max. Min. Max.

ALE high time

Address setup to ALE

Address hold after ALE

ALE falling edge to RD

(with RW-delay)

WR ALE falling edge to RD

WR

(no RW-delay)

t

,

t

,

t

CC 10 + tA– TCL - 10

5

CC 4 + t

6

CC 10 + tA– TCL - 10

7

CC 10 + tA– TCL - 10

8

CC -10 + tA– -10 + t

9

– TCL - 16

A

+

t

A

t

A

t

A

t

A

Unit

– ns

Address float after RD, WR

(with RW-delay)

Address float after RD WR

(no RW-delay)

Data Sheet 50 V1.0, 2003-11

t

,

t

CC – 6 – 6ns

10

CC – 26 – TCL + 6 ns

11

C161S

Timing Characteristics

Table 16 Multiplexed Bus (Standard Supply Voltage Range) (cont’d)

(Operating Conditions apply)

t

ALE cycle time = 6 TCL + 2

Parameter Symbol Max. CPU Clock

+ tC + tF (120 ns at 25 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 25 MHz

1 / 2TCL = 1 to 25 MHz

Min. Max. Min. Max.

RD, WR low time (with RW-delay)

RD, WR low time (no RW-delay)

to valid data in

RD (with RW-delay)

RD

to valid data in

(no RW-delay) ALE low to valid data in

t

CC 30 + tC– 2TCL - 10

12

CC 50 + tC– 3TCL - 10

13

SR – 20 + t

14

SR – 40 + t

15

SR – 40 + t

16

+ t

C

A

C

– ns

+

t

C

– ns

+

t

C

– 2TCL - 20

+

t

C

– 3TCL - 20

t

+

C

– 3TCL - 20

+

t

+ t

A

Unit

ns

C

Address to valid data in

Data hold after RD rising edge

Data float after RD

Data valid to WR

Data hold after WR t

ALE rising edge after RD

,

WR Address hold after RD

,

WR ALE falling edge to CS CS

low to Valid Data In

hold after RD, WR

CS

1)

t

t t

t

SR – 50 + 2t

17

+ t

C

SR 0 – 0 – ns

18

SR – 26 + t

19

CC 20 + tC– 2TCL - 20

22

CC 26 + tF– 2TCL - 14

23

CC 26 + tF– 2TCL - 14

25

CC 26 + tF– 2TCL - 14

27

CC -4 - t

38

SR – 40 + t

39

CC 46 + tF– 3TCL - 14

40

10 - t

A

+ 2t

A

– 4TCL - 30

A

– 2TCL - 14

F

+

t

C

+

t

F

+

t

F

t

+

F

-4 - t

A

C

A

– 3TCL - 20

t

+

F

+ 2

t

+

F

– ns

10 - t

t

+

C

– ns

t

+ t

A

+ 2t

ns

C

ns

ns ns

A

Data Sheet 51 V1.0, 2003-11

C161S

Timing Characteristics

Table 16 Multiplexed Bus (Standard Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2

Parameter Symbol Max. CPU Clock

t

+ tC + tF (120 ns at 25 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 25 MHz

1 / 2TCL = 1 to 25 MHz

Min. Max. Min. Max.

ALE fall. edge to RdCS, WrCS

(with RW delay)

ALE fall. edge to RdCS, WrCS

(no RW delay)

Address float after RdCS

, WrCS (with RW

t

CC 16 + tA– TCL - 4

42

+

t

A

CC -4 + t

43

CC – 0 – 0ns

44

– -4

A

+

t

A

– ns

delay) Address float after

RdCS

, WrCS (no RW

t

CC – 20 – TCL ns

45

delay)

Unit

RdCS (with RW delay)

RdCS (no RW delay)

RdCS (with RW delay)

RdCS (no RW delay)

Data valid to WrCS

Data hold after RdCS Data float after RdCS

Address hold after RdCS

Data hold after WrCS

1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

to Valid Data In

, WrCS Low Time

t

t t

t

SR – 16 + t

46

SR – 36 + t

47

CC 30 + tC– 2TCL - 10

48

CC 50 + tC– 3TCL - 10

49

CC 26 + tC– 2TCL - 14

50

SR 0 – 0 – ns

51

SR – 20 + t

52

CC 20 + tF– 2TCL - 20

54

, WrCS

t

specified together with the address and signal BHE

CC 20 + tF– 2TCL - 20

56

C

F

(see figures below).

– 2TCL - 24

t

+

C

– 3TCL - 24

t

+

C

– ns

t

+

C

– ns

t

+

C

– ns

+

t

C

– 2TCL - 20

t

+

F

– ns

+

t

F

– ns

t

+

F

ns

Data Sheet 52 V1.0, 2003-11

C161S

Timing Characteristics

Table 17 Multiplexed Bus (Reduced Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2

Parameter Symbol Max. CPU Clock

t

+ tC + tF (150 ns at 20 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 20 MHz

1 / 2TCL = 1 to 20 MHz

Min. Max. Min. Max.

ALE high time

Address setup to ALE t

Address hold after ALE

ALE falling edge to RD

(with RW-delay)

WR ALE falling edge to RD

WR

(no RW-delay)

t

,

t

,

t

CC 11 + tA– TCL - 14

5

CC 5 + t

6

CC 15 + tA– TCL - 10

7

CC 15 + tA– TCL - 10

8

CC -10 + tA– -10 + t

9

– TCL - 20

A

+

t

A

t

A

t

A

t

A

Unit

– ns

Address float after RD

(with RW-delay)

WR Address float after RD

WR

(no RW-delay)

RD

, WR low time

(with RW-delay)

, WR low time

RD (no RW-delay)

RD to valid data in (with RW-delay)

to valid data in

RD (no RW-delay)

ALE low to valid data in

Address to valid data in

Data hold after RD rising edge

,

t

,

t

CC – 6 – 6ns

10

CC – 31 – TCL + 6 ns

11

CC 34 + tC– 2TCL - 16

12

t

+

C

CC 59 + tC– 3TCL - 16

13

+

t

C

SR – 22 + t

14

SR – 47 + t

15

SR – 45 + t

16

+ t

C

SR – 57 + 2tA

17

+

t

C

SR 0 – 0 – ns

18

– 2TCL - 28

C

– 3TCL - 28

C

– 3TCL - 30

A

– 4TCL - 43

– ns

ns

+

t

C

ns

+

t

C

ns

t

+ t

+

A

C

ns

+ 2

t

+ t

A

C

Data float after RD

Data Sheet 53 V1.0, 2003-11

t

SR – 36 + t

19

– 2TCL - 14

F

+

ns

t

F

C161S

Timing Characteristics

Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

t

ALE cycle time = 6 TCL + 2

Parameter Symbol Max. CPU Clock

+ tC + tF (150 ns at 20 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 20 MHz

1 / 2TCL = 1 to 20 MHz

Min. Max. Min. Max.

Data valid to WR t

Data hold after WR t

ALE rising edge after RD

,

WR Address hold after RD

,

WR ALE falling edge to CS CS

low to Valid Data In

hold after RD, WR

CS

1)

t

t t

t

CC 24 + tC– 2TCL - 26

22

CC 36 + tF– 2TCL - 14

23

CC 36 + tF– 2TCL - 14

25

CC 36 + tF– 2TCL - 14

27

CC -8 - t

38

SR – 47 + t

39

CC 57 + tF– 3TCL - 18

40

10 - t

A

+ 2t

A

C

A

– ns

+

t

C

– ns

+

t

F

– ns

+

t

F

– ns

t

+

F

-8 - t

A

10 - t

– 3TCL - 28

t

+ 2t

+

C

– ns

t

+

F

Unit

A

ns ns

A

ALE fall. edge to RdCS WrCS

(with RW delay)

ALE fall. edge to RdCS WrCS

(no RW delay)

Address float after RdCS

, WrCS (with RW

delay) Address float after

RdCS, WrCS (no RW delay)

RdCS

to Valid Data In

(with RW delay) RdCS

to Valid Data In

(no RW delay) RdCS

, WrCS Low Time

(with RW delay) RdCS

, WrCS Low Time

(no RW delay)

,

t

,

t

CC 19 + tA– TCL - 6

42

t

+

A

CC -6 + t

43

CC – 0 – 0ns

44

CC – 25 – TCL ns

45

SR – 20 + t

46

SR – 45 + t

47

CC 38 + tC– 2TCL - 12

48

CC 63 + tC– 3TCL - 12

49

– -6

A

t

+

A

– 2TCL - 30

C

– 3TCL - 30

C

+

t

C

t

+

C

– ns

ns

+

t

C

ns

t

+

C

– ns

Data Sheet 54 V1.0, 2003-11

C161S

Timing Characteristics

Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 6 TCL + 2

Parameter Symbol Max. CPU Clock

t

+ tC + tF (150 ns at 20 MHz CPU clock without waitstates)

A

= 20 MHz

Variable CPU Clock

1 / 2TCL = 1 to 20 MHz

Unit

Min. Max. Min. Max.

Data valid to WrCS t

Data hold after RdCS t Data float after RdCS

Address hold after RdCS

, WrCS

Data hold after WrCS

1) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are

specified together with the address and signal BHE

t

CC 28 + tC– 2TCL - 22

50

+

t

C

SR 0 – 0 – ns

51

SR – 30 + t

52

CC 30 + tF– 2TCL - 20

54

CC 30 + tF– 2TCL - 20

56

(see figures below).

– 2TCL - 20

F

t

+

F

t

+

F

– ns

t

+

F

– ns

ns

Data Sheet 55 V1.0, 2003-11

C161S

ALE

CSxL

A23-A16

(A15-A8)

, CSxE

BHE

Read Cycle

BUS

t

5

t

6

Address

Timing Characteristics

t

16

t

38

t

39

t

17

t

25

t

40

t

27

Address

t

7

t

54

t

19

t

18

Data In

RD

RdCSx

Write Cycle

BUS

WR,

WRL

,

WRH

WrCSx

t

8

t

42

10

t

14

t

44

12

t

46

t

48

t

51

t

52

t

23

Data OutAddress

t

8

t

42

10

t

44

t

22

t

12

t

50

56

t

48

Figure 15 External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet 56 V1.0, 2003-11

C161S

ALE

CSxL

A23-A16

(A15-A8)

BHE

, CSxE

Read Cycle

BUS

Timing Characteristics

t

5

t

38

t

16

t

39

t

17

t

25

t

40

t

27

Address

t

6

t

7

t

54

t

19

t

18

Data InAddress

RD

RdCSx

Write Cycle

BUS

WR,

WRL

,

WRH

WrCSx

t

8

t

42

10

t

14

t

44

12

t

46

t

48

t

51

t

52

t

23

Data OutAddress

t

8

t

42

10

t

44

t

22

t

12

t

50

56

t

48

Figure 16 External Memory Cycle:

Multiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet 57 V1.0, 2003-11

C161S

CSxL

A23-A16

(A15-A8)

BHE

, CSxE

Read Cycle

ALE

BUS

t

5

t

38

t

16

t

39

t

17

Address

t

6

t

7

Address Data In

Timing Characteristics

t

25

t

40

t

27

t

54

t

19

t

18

RD

RdCSx

Write Cycle

BUS

WR,

WRL

,

WRH

WrCSx

t

9

t

43

t

11

t

45

t

15

t

13

t

47

t

49

t

51

t

52

t

23

Data OutAddress

t

9

t

43

t

11

t

45

t

22

t

13

t

50

56

t

49

Figure 17 External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet 58 V1.0, 2003-11

C161S

CSxL

A23-A16

(A15-A8)

BHE

, CSxE

Read Cycle

BUS

ALE

Timing Characteristics

t

5

t

38

t

16

t

39

t

17

t

25

t

40

t

27

Address

t

6

t

7

t

54

t

19

t

18

Data InAddress

RD

RdCSx

Write Cycle

BUS

WR,

WRL

,

WRH

WrCSx

t

9

t

43

t

11

t

45

t

15

t

13

t

47

t

49

t

51

t

52

t

23

Data OutAddress

t

56

t

9

t

43

t

11

t

45

t

22

t

13

t

50

t

49

Figure 18 External Memory Cycle:

Multiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet 59 V1.0, 2003-11

C161S

Timing Characteristics

Table 18 Demultiplexed Bus (Standard Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2

Parameter Symbol Max. CPU Clock

t

+ tC + tF (80 ns at 25 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 25 MHz

1 / 2TCL = 1 to 25 MHz

Min. Max. Min. Max.

ALE high time

Address setup to ALE

ALE falling edge to RD

(with RW-delay)

WR ALE falling edge to RD

WR

(no RW-delay)

t

,

t

,

t

CC 10 + tA– TCL - 10

5

CC 4 + t

6

CC 10 + tA– TCL - 10

8

CC -10 + tA– -10

9

– TCL - 16

A

+

– ns

t

A

– ns

t

A

– ns

t

A

– ns

t

A

Unit

RD

, WR low time

(with RW-delay)

, WR low time

RD (no RW-delay)

RD

to valid data in

(with RW-delay)

to valid data in

RD (no RW-delay)

ALE low to valid data in t

Address to valid data in

Data hold after RD rising edge

Data float after RD edge (with RW-delay

rising

1)

)

t

CC 30 + tC– 2TCL - 10

12

t

+

C

CC 50 + tC– 3TCL - 10

13

+

t

C

SR – 20 + t

14

SR – 40 + t

15

SR – 40 +

16

t

+ t

A

SR – 50 +

17

2

t

+ t

A

SR 0 – 0 – ns

18

SR – 26 +

20

2

t

+ t

A

– 2TCL - 20

C

– 3TCL - 20

C

– 3TCL - 20

C

– 4TCL - 30

C

– 2TCL - 14

1)

F

– ns

t

+

C

+

t

C

+

t

A

+ 2

+ 22 + t

F

+ t

t

A

t

1)

+ t

A

ns

C

ns

C

ns

Data float after RD edge (no RW-delay

Data valid to WR

Data Sheet 60 V1.0, 2003-11

rising

1)

)

t

SR – 10 +

21

t

2

CC 20 + tC– 2TCL - 20

22

A

+ t

1)

F

– TCL - 10

t

+ 22

A

1)

+ t

F

– ns

t

+

C

ns

C161S

Timing Characteristics

Table 18 Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)

(Operating Conditions apply)

t

ALE cycle time = 4 TCL + 2

Parameter Symbol Max. CPU Clock

+ tC + tF (80 ns at 25 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 25 MHz

1 / 2TCL = 1 to 25 MHz

Min. Max. Min. Max.

Data hold after WR t

ALE rising edge after RD,

t

CC 10 + tF– TCL - 10

24

CC -10 + tF– -10 + t

26

+

– ns

t

F

– ns

WR

2)

Address hold after WR ALE falling edge to CS

low to Valid Data In

CS

hold after RD, WR

CS

t

3)

t

3)

t

3)

t

CC 0 + t

28

CC -4 - t

38

SR – 40 +

39

CC 6 + t

41

– 0 + t

F

10 - t

A

F

A

t

+ 2t

C

A

– TCL - 14

– ns

10 - t

A

-4 - t

F

A

– 3TCL - 20

t

+ 2t

+

C

A

– ns

+

t

F

Unit

ns ns

ALE falling edge to RdCS

, WrCS (with

RW-delay) ALE falling edge to

RdCS, WrCS (no RW-delay)

RdCS

to Valid Data In

(with RW-delay) RdCS to Valid Data In

(no RW-delay) RdCS

, WrCS Low Time

(with RW-delay) RdCS

, WrCS Low Time

(no RW-delay) Data valid to WrCS

Data hold after RdCS

t

CC 16 + tA– TCL - 4

42

t

+

A

CC -4 + t

43

SR – 16 + t

46

SR – 36 + t

47

CC 30 + tC– 2TCL - 10

48

CC 50 + tC– 3TCL - 10

49

CC 26 + tC– 2TCL - 14

50

SR 0 – 0 – ns

51

– -4

A

t

+

A

– 2TCL - 24

C

– 3TCL - 24

C

+

t

C

t

+

C

+

t

C

– ns

+

t

C

+

t

C

– ns

ns

Data float after RdCS (with RW-delay)

Data Sheet 61 V1.0, 2003-11

1)

t

SR – 20 + t

53

– 2TCL - 20

F

+ 2

t

A

+ t

ns

1)

F

C161S

Timing Characteristics

Table 18 Demultiplexed Bus (Standard Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2

Parameter Symbol Max. CPU Clock

t

+ tC + tF (80 ns at 25 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 25 MHz

1 / 2TCL = 1 to 25 MHz

Min. Max. Min. Max.

Data float after RdCS (no RW-delay)

1)

Address hold after RdCS

, WrCS

Data hold after WrCS

1) RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2) Read data are latched with the same clock edge that triggers the address change and the rising RD

Therefore address changes before the end of RD

3) These parameters refer to the latched chip select signals (CSxL

specified together with the address and signal BHE

t

SR – 0 + t

68

CC -6 + t

55

CC 6 + t

57

– TCL - 20

F

– -6 + t

F

– TCL - 14

F

have no impact on read cycles.

). The early chip select signals (CSxE) are

(see figures below).

+

F

t

F

A

+ t

1)

F

+ 2

t

– ns

Unit

ns

edge.

Data Sheet 62 V1.0, 2003-11

C161S

Timing Characteristics

Table 19 Demultiplexed Bus (Reduced Supply Voltage Range)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2

Parameter Symbol Max. CPU Clock

t

+ tC + tF (100 ns at 20 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 20 MHz

1 / 2TCL = 1 to 20 MHz

Min. Max. Min. Max.

ALE high time

Address setup to ALE t

ALE falling edge to RD WR

(with RW-delay)

ALE falling edge to RD

(no RW-delay)

WR

, WR low time

RD (with RW-delay)

t

,

t

,

t

CC 11 + tA– TCL - 14

5

CC 5 + t

6

CC 15 + tA– TCL - 10

8

CC -10 + tA– -10

9

CC 34 + tC– 2TCL - 16

12

– TCL - 20

A

+

– ns

t

A

– ns

t

A

– ns

t

A

– ns

t

A

– ns

t

C

Unit

RD

, WR low time

(no RW-delay)

to valid data in

RD (with RW-delay)

RD

to valid data in

(no RW-delay) ALE low to valid data in

Address to valid data in t

Data hold after RD rising edge

Data float after RD edge (with RW-delay

Data float after RD edge (no RW-delay

rising

1)

)

rising

1)

)

t

CC 59 + tC– 3TCL - 16

13

t

+

C

SR – 22 + t

14

SR – 47 + t

15

SR – 45 +

16

t

+ t

A

SR – 57 +

17

2

t

+ t

A

SR 0 – 0 – ns

18

SR – 36 +

20

t

+ t

2

A

SR – 15 +

21

t

+ t

2

A

– 2TCL - 28

C

– 3TCL - 28

C

– 3TCL - 30

C

– 4TCL - 43

C

– 2TCL - 14

1)

F

– TCL - 10

1)

F

– ns

+

t

C

t

+

C

+

t

A

+ 2

+ 22 + t

F

+ 22 + t

F

+ t

t

A

t

1)

t

1)

+ t

A

ns

C

ns

C

ns

Data valid to WR

Data Sheet 63 V1.0, 2003-11

t

CC 24 + tC– 2TCL - 26

22

+

– ns

t

C

C161S

Timing Characteristics

Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

t

ALE cycle time = 4 TCL + 2

Parameter Symbol Max. CPU Clock

+ tC + tF (100 ns at 20 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 20 MHz

1 / 2TCL = 1 to 20 MHz

Min. Max. Min. Max.

Data hold after WR t

ALE rising edge after RD,

t

CC 15 + tF– TCL - 10

24

CC -12 + tF– -12 + t

26

+

– ns

t

F

– ns

WR

2)

Address hold after WR ALE falling edge to CS

low to Valid Data In

CS

hold after RD, WR

CS

t

3)

t

3)

t

3)

t

CC 0 + t

28

CC -8 - t

38

SR – 47 +

39

CC 9 + t

41

– 0 + t

F

10 - t

A

F

A

t

+ 2t

C

A

– TCL - 16

– ns

10 - t

A

-8 - t

F

A

– 3TCL - 28

t

+ 2t

+

C

– ns

+

t

F

Unit

ns ns

A

ALE falling edge to RdCS

, WrCS (with

RW-delay) ALE falling edge to

RdCS, WrCS (no RW-delay)

RdCS

to Valid Data In

(with RW-delay) RdCS to Valid Data In

(no RW-delay) RdCS

, WrCS Low Time

(with RW-delay) RdCS

, WrCS Low Time

(no RW-delay) Data valid to WrCS

Data hold after RdCS

t

CC 19 + tA– TCL - 6

42

t

+

A

CC -6 + t

43

SR – 20 + t

46

SR – 45 + t

47

CC 38 + tC– 2TCL - 12

48

CC 63 + tC– 3TCL - 12

49

CC 28 + tC– 2TCL - 22

50

SR 0 – 0 – ns

51

– -6

A

t

+

A

– 2TCL - 30

C

– 3TCL - 30

C

+

t

C

t

+

C

+

t

C

– ns

+

t

C

+

t

C

– ns

ns

Data float after RdCS (with RW-delay)

Data Sheet 64 V1.0, 2003-11

1)

t

SR – 30 + t

53

– 2TCL - 20

F

+ 2

t

A

+ t

ns

1)

F

C161S

Timing Characteristics

Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d)

(Operating Conditions apply)

ALE cycle time = 4 TCL + 2

Parameter Symbol Max. CPU Clock

t

+ tC + tF (100 ns at 20 MHz CPU clock without waitstates)

A

Variable CPU Clock

= 20 MHz

1 / 2TCL = 1 to 20 MHz

Min. Max. Min. Max.

Data float after RdCS (no RW-delay)

1)

Address hold after RdCS

, WrCS

Data hold after WrCS

1) RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral).

2) Read data are latched with the same clock edge that triggers the address change and the rising RD

Therefore address changes before the end of RD

3) These parameters refer to the latched chip select signals (CSxL

specified together with the address and signal BHE

t

SR – 5 + t

68

CC -16 + tF– -16 + t

55

57

CC 9 + t

have no impact on read cycles.

– TCL - 16

F

(see figures below).

– TCL - 20

F

+ 2

t

F

– ns

A

+ t

1)

F

– ns

+

t

F

). The early chip select signals (CSxE) are

Unit

ns

edge.

Data Sheet 65 V1.0, 2003-11

C161S

ALE

CSxL

A23-A16

A15-A0

BHE

, CSxE

Read Cycle

BUS

(D15-D8)

D7-D0

Timing Characteristics

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

20

t

18

Data In

RD

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL

,

WRH

WrCSx

t

8

t

42

t

14

t

12

t

46

t

48

t

51

t

53

t

24

Data Out

t

57

t

8

t

42

t

22

t

12

t

50

t

48

Figure 19 External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Normal ALE

Data Sheet 66 V1.0, 2003-11

C161S

ALE

CSxL

A23-A16

A15-A0

BHE

CSxE

Read Cycle

BUS

(D15-D8)

D7-D0

Timing Characteristics

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

,

t

6

t

55

t

20

t

18

Data In

RD

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL

,

WRH

WrCSx

t

8

t

42

t

14

t

12

t

46

t

48

t

51

t

53

t

24

Data Out

t

57

t

8

t

42

t

22

t

12

t

50

t

48

Figure 20 External Memory Cycle:

Demultiplexed Bus, With Read/Write Delay, Extended ALE

Data Sheet 67 V1.0, 2003-11

C161S

ALE

CSxL

A23-A16

A15-A0

BHE

, CSxE

Read Cycle

BUS

(D15-D8)

D7-D0

RD

Timing Characteristics

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

21

t

18

Data In

t

9

t

15

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL

,

WRH

WrCSx

t

43

13

t

47

t

49

t

51

t

68

t

24

Data Out

t

9

t

43

t

22

t

13

t

50

t

49

57

Figure 21 External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Normal ALE

Data Sheet 68 V1.0, 2003-11

C161S

CSxL

A23-A16

A15-A0

BHE

, CSxE

Read Cycle

BUS

(D15-D8)

D7-D0

ALE

Timing Characteristics

t

5

t

38

t

16

t

39

t

17

t

26

t

41

t

28

Address

t

6

t

55

t

21

t

18

Data In

RD

RdCSx

Write Cycle

BUS

(D15-D8)

D7-D0

WR,

WRL

, WRH

WrCSx

t

9

t

43

t

15

t

13

t

47

t

49

t

51

t

68

t

24

Data Out

t

57

t

9

t

43

t

22

t

13

t

50

t

49

Figure 22 External Memory Cycle:

Demultiplexed Bus, No Read/Write Delay, Extended ALE

Data Sheet 69 V1.0, 2003-11

C161S

6 Package Outlines

0.65

12.35

±0.08

0.3

0.12

17.2

14

M

1)

D

A-B

+0.1

-0.05

2

0.25 MIN.

0.1

CDC80x

0.2

A-BH4x

0.2

A-B

H

2.45 MAX.

0.88

D

4xD

±0.15

Package Outlines

+0.08

-0.02

MAX.7˚

0.15

A

B

1)

14

17.2

80

Index Marking

1

0.6 x 45˚

1)

Does not include plastic or metal protrusion of 0.25 max. per side

Figure 23 P-MQFP-80-7 (Plastic Metric Quad Flat Package)

GPM05249

You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products.

SMD = Surface Mounted Device

Dimensions in mm

Data Sheet 70 V1.0, 2003-11

www.infineon.com

Published by Infineon Technologies AG

INFINEON C161S User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Summary of Features

2 General Device Information

2.1 Introduction

2.2 Pin Configuration and Definition

3 Functional Description

3.1 Memory Organization

3.2 External Bus Controller

3.3 Central Processing Unit (CPU)

3.3.1 Interrupt System

3.4 General Purpose Timer (GPT) Unit

3.5 Real Time Clock

3.6 Serial Channels

3.7 Watchdog Timer

3.8 Parallel Ports

3.9 Oscillator Watchdog

3.10 Power Management

3.11 Instruction Set Summary

3.12 Special Function Registers Overview

4 Electrical Parameters

4.1 Absolute Maximum Ratings

4.2 Operating Conditions

4.3 Parameter Interpretation

4.4 DC Parameters

5 Timing Characteristics

5.1 Definition of Internal Timing

5.2 External Clock Drive XTAL1

5.3 Testing Waveforms

5.4 AC Characteristics

6 Package Outlines