INFINEON C161S User Manual

Data Sheet, V1.0, Nov. 2003

C161S

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

Edition 2003-11 Published by Infineon Technologies AG,

St.-Martin-Strasse 53, 81669 München, Germany

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The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.

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circuits, descriptions and charts stated herein.

Information

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Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, V1.0, Nov. 2003

C161S

16-Bit Single-Chip Microcontroller

Microcontrollers

Never stop thinking.

C161S

Revision History: 2003-11 V1.0

Previous Version: none Page Subjects (major changes since last revision)

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Template: mc_tmplt_a5.fm / 3 / 2003-09-01

C161S16-Bit Single-Chip Microcontroller

C166 Family

C161S

1 Summary of Features

• High Performance 16-bit CPU with 4-Stage Pipeline – 80 ns Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 Mbytes Total Linear Address Space for Code and Data – 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 30 Sources, Sample-Rate down to 40 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)

• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input

• On-Chip Memory Modules: 2 Kbytes On-Chip Internal RAM (IRAM)

• On-Chip Peripheral Modules – Two Multi-Functional General Purpose Timer Units with 5 Timers – Two Serial Channels (Sync./Asynchronous and High-Speed-Synchronous) – On-Chip Real Time Clock

• External Address Space for Code and Data – Programmable External Bus Characteristics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses with 8-bit or 16-bit

Data Bus Width – Four Programmable Chip-Select Signals – 4 Mbytes maximum address window size, results in a total external address space

of 16 Mbytes, when all chip-select signal (address windows) are active

• Idle and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

• Up to 63 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis

• Power Supply: the C161S can operate from a 5 V or a 3 V power supply (see Table 1)

• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 80-Pin MQFP Package

× 16 bit), 800 ns Division (32 / 16 bit)

Data Sheet 1 V1.0, 2003-11

C161S

Summary of Features

This document describes several derivatives of the C161 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product.

Table 1 C161S Derivative Synopsis Derivative Max. Operating

Frequency

SAB-C161S-L25M 25 MHz 4.5 to 5.5 V (Standard) 0 to 70 SAF-C161S-L25M 25 MHz 4.5 to 5.5 V (Standard) -40 to 85 SAB-C161S-LM3V 20 MHz 3.0 to 3.6 V (Reduced) 0 to 70 SAF-C161S-LM3V 20 MHz 3.0 to 3.6 V (Reduced) -40 to 85

Operating Voltage Ambient

Temperature

°C

For simplicity all versions are referred to by the term C161S throughout this document.

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• the derivative itself, i.e. its function set, the temperature range, and the supply voltage

• the package and the type of delivery.

For the available ordering codes for the C161S please refer to the “Product Catalog Microcontrollers”, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet 2 V1.0, 2003-11

C161S

General Device Information

2 General Device Information

2.1 Introduction

The C161S is a derivative of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. It also provides clock generation via PLL and power management features. The C161S is especially suited for cost sensitive applications.

XTAL1

XTAL2

RSTIN

PORT0 16 bit

PORT1 16 bit

RSTOUT

NMI

ALE

WR/WRL Port 5

2 bit

Figure 1 Logic Symbol

Port 2 7 bit

C161S

Port 3 12 bit

Port 4 6 bit

Port 6 4 bit

MCA05504

Data Sheet 3 V1.0, 2003-11

C161S

2.2 Pin Configuration and Definition

P5.15/T2EUD

P5.14/T4EUD

P2.15/EX7IN

P2.14/EX6IN

P2.13/EX5IN

P2.11/EX3IN

XTAL1 XTAL2

P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD

P3.5/T4IN P3.6/T3IN

P3.7/T2IN P3.8/MRST P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13/SCLK

P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19

P2.10/EX2IN

P2.12/EX4IN

80797877767574737271706968676665646362

160 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21222324252627282930313233343536373839

P6.3/CS3

P2.9/EX1IN

C161S

P6.2/CS2

General Device Information

P6.1/CS1

P6.0/CS0

NMI

RSTOUT

RSTIN

P1H.6/A14

P1H.7/A15

P1H.5/A13 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

P1H.4/A12

P1H.3/A11

P1H.2/A10

P1H.1/A9

P1H.0/A8

P1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

P0H.2/AD10

P4.4/A20

P4.5/A21

WR/WRL

ALE

P0L.0/AD0

P0L.1/AD1

P0L.4/AD4

P0L.5/AD5

P0L.2/AD2

P0L.3/AD3

P0L.6/AD6

P0L.7/AD7

P0H.0/AD8

P0H.1/AD9

MCP05505

Figure 2 Pin Configuration (top view)

Data Sheet 4 V1.0, 2003-11

C161S

Table 2 Pin Definitions and Functions Symbol Pin

No.

XTAL1

Input Outp.

Function

XTAL1: Input to the oscillator amplifier and input to the

internal clock generator

XTAL223

XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics (see Chapter 5.4) must be observed.

Port 3 is a 12-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/pull or open drain drivers.

The following Port 3 pins also serve for alternate functions: P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12

P3.13

5 6 7 8 9 10 11 12 13 14 15

I O I I I I I/O I/O O I/O O O I/O

CAPIN GPT2 Register CAPREL Capture Input

T3OUT GPT1 Timer T3 Toggle Latch Output

T3EUD GPT1 Timer T3 External Up/Down Control Input

T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp.

T3IN GPT1 Timer T3 Count/Gate Input

T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp.

MRST SSC Master-Receive/Slave-Transmit Inp./Outp.

MTSR SSC Master-Transmit/Slave-Receive Outp./Inp.

TxD0 ASC0 Clock/Data Output (Async./Sync.)

RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.)

BHE

WRH

External Memory High Byte Enable Signal, External Memory High Byte Write Strobe

SCLK SSC Master Clock Output / Slave Clock Input.

General Device Information

Port 4 is a 6-bit bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-

impedance state.

Port 4 can be used to output the segment address lines: P4.0 P4.1 P4.2 P4.3 P4.4 P4.5

Data Sheet 5 V1.0, 2003-11

17 18 19 20 23 24

O O O O O O

A16 Least Significant Segment Address Line

A17 Segment Address Line

A18 Segment Address Line

A19 Segment Address Line

A20 Segment Address Line

A21 Segment Address Line

C161S

General Device Information

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin

No.

Input Outp.

Function

RD 25 O External Memory Read Strobe. RD is activated for every

external instruction or data read access. WR

WRL

26 O External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL

-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection.

ALE 27 O Address Latch Enable Output. Can be used for latching the

address into external memory or an address latch in the multiplexed bus modes.

28 I External Access Enable pin. A low level at this pin during and

after Reset forces the C161S to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. “ROMless” versions must have this pin tied to ‘0’.

PORT0

P0L.0-7

P0H.0-7

29-36

39-46

IO PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 – D7 P0H.0 – P0H.7: I/O D8 – D15

Multiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 – AD7 P0H.0 – P0H.7: A8 – A15 AD8 – AD15

Data Sheet 6 V1.0, 2003-11

C161S

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin

No.

PORT1

P1L.0-7

47-54

Input

Function

Outp.

IO PORT1 consists of the two 8-bit bidirectional I/O ports P1L

and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver

P1H.0-7

55-62

is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.

RSTIN

65 I/O Reset Input with Schmitt-Trigger characteristics. A low level

at this pin while the oscillator is running resets the C161S. An internal pull-up resistor permits power-on reset using only a capacitor connected to

A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table.

General Device Information

line is internally pulled low

RST OUT

NMI

Note: To let the reset configuration of PORT0 settle and to

let the PLL lock a reset duration of approx. 1 ms is recommended.

66 O Internal Reset Indication Output. This pin is set to a low level

when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

67 I Non-Maskable Interrupt Input. A high to low transition at this

pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C161S to go into power down mode. If NMI

is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI

should be pulled high externally.

Data Sheet 7 V1.0, 2003-11

C161S

Table 2 Pin Definitions and Functions (cont’d) Symbol Pin

No.

Input Outp.

Function

Port 6 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The Port 6 pins also serve for alternate functions:

P6.0 P6.1 P6.2 P6.3

68 69 70 71

O O O O

CS0 CS1 CS2 CS3

Chip Select 0 Output Chip Select 1 Output Chip Select 2 Output Chip Select 3 Output

Port 2 is a 7-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The following Port 2 pins also serve for alternate functions:

P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15

72 73 74 75 76 77 78

I I I I I I I

EX1IN Fast External Interrupt 1 Input EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input EX4IN Fast External Interrupt 4 Input EX5IN Fast External Interrupt 5 Input EX6IN Fast External Interrupt 6 Input EX7IN Fast External Interrupt 7 Input

General Device Information

Port 5 is a 2-bit input-only port with Schmitt-Trigger char. The pins of Port 5 also serve as timer inputs:

P5.14 P5.15

79 80

4, 22, 37, 64

I I

T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Input T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Input

– Digital Supply Voltage:

+ 5 V during normal operation and idle mode. + 3.3 V during reduced supply operation and idle mode.

≥ 2.5 V during power down mode.

Note: Please refer to the Operating Conditions Parameters.

1, 21,

– Digital Ground.

38, 63

Data Sheet 8 V1.0, 2003-11

C161S

General Device Information

Note: The following behavioural differences must be observed when the bidirectional

reset is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset.

• The reset indication flags always indicate a long hardware reset.

• The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is low.

•Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extended to the duration of the internal reset sequence.

Data Sheet 9 V1.0, 2003-11

C161S

Functional Description

3 Functional Description

The architecture of the C161S combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the onchip memory blocks allow the design of compact systems with maximum performance.

Figure 3 gives an overview of the different on-chip components and of the advanced,

high bandwidth internal bus structure of the C161S.

Note: All time specifications refer to a CPU clock of 20 MHz

(see definition in the AC Characteristics section).

ProgMem

Internal

ROM

Area

Instr. / Data

External Instr. / Data

Interrupt Controller

C166-Core

CPU

PEC

16-Level

Priority

Interrupt Bus

Peripheral Data Bus

Data

IRAM

Internal

RAM

Dual Port

2 Kbytes

Osc / PLL

RTC WDT

XTAL

On-Chip XBUS (16-Bit Demux)

Port 4

EBC

XBUS Control

ASC0

(USART)

SSC

(SPI)

External Bus

Port 6

Control

Port 0

Port 1

BRGen

GPT

Port 2

Port 5Port 3

216

MCB04323_1S.vsd

Figure 3 Block Diagram

The program memory, the internal RAM (IRAM) and the set of generic peripherals are connected to the CPU via separate buses. A fourth bus, the XBUS, connects external resources as well as additional on-chip resources, the X-Peripherals (see Figure 3).

Data Sheet 10 V1.0, 2003-11

C161S

Functional Description

3.1 Memory Organization

The memory space of the C161S is configured in a von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 Mbytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable.

The C161S is prepared to incorporate on-chip program memory (not in the ROM-less derivatives, of course) for code or constant data. The internal ROM area can be mapped either to segment 0 or segment 1.

2 Kbytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs).

1024 bytes (2 Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family.

× 512 bytes) of the address space are reserved for the Special Function

In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 Mbytes of external RAM and/or ROM can be connected to the microcontroller. The maximum contiguous external address space is 4 Mbytes, i.e. this is the maximum address window size. Using the chip-select lines (multiple windows) this results in a maximum usable external address space of 16 Mbytes.

Data Sheet 11 V1.0, 2003-11

C161S

Functional Description

3.2 External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows:

• 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed

• 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed

• 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed

• 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which control the access to different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0.

Up to 4 external CS external glue logic. The C161S offers the possibility to switch the CS unlatched mode. In this mode the internal filter logic is switched off and the CS are directly generated from the address. The unlatched CS CSCFG (SYSCON.6).

For applications which require less than 4 Mbytes of external memory space, this address space can be restricted to 1 Mbyte, 256 Kbytes, or to 64 Kbytes. In this case Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if the full address width is used.

signals (3 windows plus default) can be generated in order to save

outputs to an

signals

mode is enabled by setting

Data Sheet 12 V1.0, 2003-11

C161S

Functional Description

3.3 Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C161S’s instructions can be executed in just one machine cycle which requires 100 ns at 20 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16

× 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another

pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

STKOV

STKUN

CPU

MDH MDL

R15

Internal

RAM

ROM

Exec. Unit

Instr. Ptr.

Instr. Reg.

4-Stage Pipeline

PSW

SYSCON

BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 ADDRSEL 4

Data Page Ptr. Code Seg. Ptr.

Mul/Div-HW

Bit-Mask Gen

ALU

(16-bit)

Barrel - Shifter

Context Ptr.

ADDRSEL 1 ADDRSEL 2 ADDRSEL 3

General

Purpose

Registers

R15

MCB02147

Figure 4 CPU Block Diagram

The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others.

Data Sheet 13 V1.0, 2003-11

C161S

Functional Description

A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C161S instruction set which includes the following instruction classes:

• Arithmetic Instructions

• Logical Instructions

• Boolean Bit Manipulation Instructions

• Compare and Loop Control Instructions

• Shift and Rotate Instructions

• Prioritize Instruction

• Data Movement Instructions

• System Stack Instructions

• Jump and Call Instructions

• Return Instructions

• System Control Instructions

• Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.

Data Sheet 14 V1.0, 2003-11

C161S

Functional Description

3.3.1 Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C161S is capable of reacting very fast to the occurrence of non-deterministic events.

The architecture of the C161S supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C161S has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.

Table 3 shows all of the possible C161S interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt requests by setting the respective interrupt request bit (xIR).

Data Sheet 15 V1.0, 2003-11

C161S

Functional Description

Table 3 C161S Interrupt Nodes Source of Interrupt or

PEC Service Request

Request Flag

Enable Flag

Interrupt Vector

Vector Location

Unassigned node CC8IR CC8IE CC8INT 00’0060 External Interrupt 1 CC9IR CC9IE CC9INT 00’0064 External Interrupt 2 CC10IR CC10IE CC10INT 00’0068 External Interrupt 3 CC11IR CC11IE CC11INT 00’006C External Interrupt 4 CC12IR CC12IE CC12INT 00’0070 External Interrupt 5 CC13IR CC13IE CC13INT 00’0074 External Interrupt 6 CC14IR CC14IE CC14INT 00’0078 External Interrupt 7 CC15IR CC15IE CC15INT 00’007C GPT1 Timer 2 T2IR T2IE T2INT 00’0088 GPT1 Timer 3 T3IR T3IE T3INT 00’008C GPT1 Timer 4 T4IR T4IE T4INT 00’0090

Trap Number

GPT2 Timer 5 T5IR T5IE T5INT 00’0094 GPT2 Timer 6 T6IR T6IE T6INT 00’0098 GPT2 CAPREL Reg. CRIR CRIE CRINT 00’009C Unassigned node ADCIR ADCIE ADCINT 00’00A0 Unassigned node ADEIR ADEIE ADEINT 00’00A4 ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8 ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C ASC0 Receive S0RIR S0RIE S0RINT 00’00AC ASC0 Error S0EIR S0EIE S0EINT 00’00B0 SSC Transmit SCTIR SCTIE SCTINT 00’00B4 SSC Receive SCRIR SCRIE SCRINT 00’00B8 SSC Error SCEIR SCEIE SCEINT 00’00BC Unassigned node XP0IR XP0IE XP0INT 00’0100 Unassigned node XP1IR XP1IE XP1INT 00’0104 Unassigned node XP2IR XP2IE XP2INT 00’0108

26 27 28 29 2A 47 2B 2C 2D 2E 2F 40 41 42

PLL/OWD and RTC XP3IR XP3IE XP3INT 00’010C Unassigned node CC29IR CC29IE CC29INT 00’0110 Unassigned node CC30IR CC30IE CC30INT 00’0114 Unassigned node CC31IR CC31IE CC31INT 00’0118

44 45 46

Data Sheet 16 V1.0, 2003-11

C161S

Functional Description

The C161S also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts.

Table 4 shows all of the possible exceptions or error conditions that can arise during run-

time:

Table 4 Hardware Trap Summary Exception Condition Trap

Flag

Reset Functions:

–

• Hardware Reset

• Software Reset

• W-dog Timer Overflow

Trap Vector

RESET RESET RESET

Vector Location

00’0000 00’0000 00’0000

H H H

Trap Number

Trap Priority

III III III

Class A Hardware Traps:

• Non-Maskable Interrupt

• Stack Overflow

NMI STKOF STKUF

NMITRAP STOTRAP STUTRAP

00’0008 00’0010 00’0018

• Stack Underflow

Class B Hardware Traps:

• Undefined Opcode

• Protected Instruction

UNDOPC PRTFLT

BTRAP BTRAP

00’0028 00’0028

Fault

• Illegal Word Operand

ILLOPA

BTRAP

00’0028

Access

• Illegal Instruction

ILLINA

BTRAP

00’0028

Access

• Illegal External Bus

ILLBUS

BTRAP

00’0028

Access

Reserved – – [2C

Software Traps

• TRAP Instruction

–– Any

[00’0000 00’01FC in steps of 4

]

–

H H H

H H

04 06

0A 0A

[0B 0F

H H H

H H

–

]

Any [00

–

]

–

]

II II II

I I

–

Current CPU Priority

Data Sheet 17 V1.0, 2003-11

C161S

Functional Description

3.4 General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking.

In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention.

Data Sheet 18 V1.0, 2003-11

C161S

T2EUD

T3EUD

T2IN

T3IN

CPU

Functional Description

U/D

2n : 1f

Mode

Control

Mode

Control

GPT1 Timer T2

Reload Capture

Toggle FF

GPT1 Timer T3 T3OTL

U/D

Interrupt Request

T3OUT

Other

Timers Capture Reload

T4IN

T4EUD

CPU

2n : 1f

Mode

Control

GPT1 Timer T4

U/D

Interrupt

Request

MCT02141

n = 3 … 10

Figure 5 Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows the C161S to measure absolute time differences or to perform pulse multiplication without software overhead.

Data Sheet 19 V1.0, 2003-11

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