INFINEON C161PI DATA SHEET

C161PI

Microcontrollers

C166 Family

16-Bit Single-Chip Microcontroller C161PI

www.infineon.com

Data Sheet 1999-07

Preliminary

C161PI Revision History: 1999-07 Preliminary

Previous Versions: 1998-05 (C161RI / Preliminary)

1998-01 (C161RI / Advance Information) 1997-12 (C161RI / Advance Information)

Page Subjects

--- 3 V specification introduced 4, 5, 7 Signal FOUT added 14 XRAM description added 15 Unlatched CS

description added 23 Block Diagram corrected 24 Description of divider chain improved 25, 51, 52 ADC description updated to 10-bit 36, 37 Revised description of Absolute Max. Ratings and Operating Condition s 39, 44 Power supply values improved 45 - 50 Revised description for clock generation includ ing P LL 54 ff. Standard 25-MHz timing

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The C161PI is the successor of the C161RI. Therefore this data sheet also replaces the C161RI

data sheet (see also revision history).

Edition 1999-07 Published by Infineon Technologies AG i. Gr.,

St.-Martin-Strasse 53

D-81541 München

The information herein is given to descr ibe certain components and shall not be considered as warranted characteristics. Terms of delivery and r ight s to tec hnical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and con dit ions and prices please contact your neares t Inf i neon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).

Warnings

Due to technical requirement s components may contain dangerous substan ces. For information on the types in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon T echnologies, if a failure of suc h co mpon ents can reasonably b e expected to cau se t he failure of that l i fe-support device or system, or to affect the safety or e ffectiveness of t hat de vice or syst em. L if e support de vices o r sys tems ar e inten ded to b e impla nted in the human body , or to support and/o r ma int ain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

C166 Family of C161PI High-Performance CMOS 16-Bit Microcontrollers

Preliminary C161PI 16-Bit Microcontroller

• High Performance 16-bit CPU with 4-Stage Pipeline – 80 ns Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 × 16 bit), 800 n s Division (32 / 16 bit) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Sup po rt – 16 MBytes Total Linear Address Sp ace for Cod e and Data – 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 27 Sources, Sample-Rate down to 40 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)

• Clk. Generation via on-chip PLL (1:1.5/2/2.5/3/4/5), via prescaler or via direct clk. inp.

• On-Chip Memory Modules – 1 KByte On-Chip Internal RAM (IRAM) – 2 KBytes On-Chip Extension RAM (XRAM)

• On-Chip Peripheral Modules – 4-Channel 10-bit A/D Converter with Programm. Conversion Time down to 7.8 µs – Two Multi-Functional General Purpose Timer Units with 5 Timers – Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

C Bus Interface (10-bit Addressing, 400 KH z) with 2 Channels (multiplexed)

–I

• Up to 8 MBytes External Address Space for Cod e and Data – Programmable External Bus Ch aracter istics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit

Data Bus Width

– Five Programmable Chip-Sel ect Signals

• Idle and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and O scillator W atchdog

• On-Chip Real Time Clock

• Up to 76 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis

• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Bo ards

• On-Chip Bootstrap Loader

• 100-Pin MQFP / TQFP Package

Data Sheet 1 1999-07

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This document describes the SAB-C161PI-LM, the SAB-C161PI-LF, the SAF-C161PILM and the SAF-C161PI-LF. For simplicity all versions are referred to by the term C1 61P I throughout this document.

Ordering Information

The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies:

• the derivative itself, i.e. its function set

• the specified temperature range

• the package

• the type of delivery.

For the available ordering codes for the C161PI please refer to the „Product Catalog Microcontrollers“, which summarizes all available microcontroller variants.

Note: The ordering codes for Mask-ROM versions are defined for each product after

verification of the respective ROM code.

Data Sheet 2 1999-07

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Introduction

The C161PI is a derivative of the Infineon C166 Family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 8 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. The C161PI derivative is especially suited for cost sensitive applications.

XTAL1 XTAL2

RSTIN RSTOUT

NMI EA

ALE RD WR/WRL

Port 5 6 bit

VDDV

C161PI

AREFVAGND

PORT0 16 bit

PORT1 16 bit

Port 2 8 bit

Port 3 15 bit

Port 4 7 bit

Port 6 8 bit

Figure 1 Logic Symbol

Data Sheet 3 1999-07

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Pin Configuration MQFP Package

(top view)

AGNDVAREF

P5.1/AN1

P5.0/AN0

P2.15/EX7IN

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P2.14/EX6IN

P2.13/EX5IN

P2.12/EX4IN

P2.11/EX3IN

P2.10/EX2IN

P2.9/EX1IN

P2.8/EX0IN

P6.7/SDA2

P6.6/SCL1

P6.5/SDA1

P6.4/CS4

P6.3/CS3

P6.2/CS2

P6.1/CS1

P6.0/CS0

P5.2/AN2

P5.3/AN3 P5.14/T4EUD P5.15/T2EUD

XTAL1 XTAL2

P3.0/SCL0

P3.1/SDA0

P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD

P3.5/T4IN P3.6/T3IN

P3.7/T2IN P3.8/MRST P3.9/MTSR

P3.10/TxD0

P3.11/RxD0

P3.12/BHE

/WRH

P3.13/SCLK

P3.15/CLKOUT/

FOUT V

P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19 P4.4/A20

100999897969594939291908988878685848382

1 2 3 4

6 7

9 10 11 12 13 14

C161PI

15 16 17 18 19 20 21 22 23 24

26 27 28 29 30

31323334353637383940414243444546474849

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

NMI RSTOUT RSTIN V

P1H.7/A15 P1H.6/A14 P1H.5/A13 P1H.4/A12 P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 V

P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9

P4.5/A21

P4.6/A22

WR/WRL

ALE

READY

P0L.0/AD0

P0L.1/AD1

P0L.2/AD2

P0L.3/AD3

P0L.4/AD4

P0L.5/AD5

P0L.6/AD6

P0L.7/AD7

P0H.0/AD8

Figure 2

Data Sheet 4 1999-07

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Pin Configuration TQFP Package

(top view)

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P5.14/T4EUD P5.15/T2EUD

XTAL1 XTAL2

P3.0/SCL0

P3.1/SDA0

P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD

P3.5/T4IN P3.6/T3IN

P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TxD0

P3.11/RxD0

P3.12/BHE

/WRH

P3.13/SCLK

P3.15/CLKOUT/

FOUT V

P4.0/A16 P4.1/A17

P5.1/AN1

P5.0/AN0

AGNDVAREF

P2.15/EX7IN

P2.14/EX6IN

P2.13/EX5IN

P2.12/EX4IN

P2.11/EX3IN

P2.10/EX2IN

P2.9/EX1IN

P2.8/EX0IN

P6.7/SDA2

P6.6/SCL1

P6.5/SDA1

P6.4/CS4

P6.3/CS3

P6.2/CS2

P6.1/CS1

P6.0/CS0

NMI

RSTOUT

RSTIN

P1H.7/A15

P1H.6/A14

P1H.5/A13

P1H.4/A12

P1H.3/A11

P1H.2/A10

P1H.1/A9

P1H.0/A8

C161PI

63 62 61 60 59 58 57 56 55 54 53 52 51

P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11

P5.3/AN3

P5.2/AN2

100999897969594939291908988878685848382818079787776

1 2

4 5

7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

24 25

26272829303132333435363738394041424344454647484950

P4.2/A18

P4.3/A19

P4.4/A20

P4.5/A21

P4.6/A22

WR/WRL

READY

ALE

P0L.0/AD0

P0L.1/AD1

P0L.2/AD2

P0L.3/AD3

P0L.4/AD4

P0L.5/AD5

P0L.6/AD6

P0L.7/AD7

P0H.0/AD8

P0H.1/AD9

P0H.2/AD10

Figure 3

Data Sheet 5 1999-07

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Table 1 Pin Definitions and Functions

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Symbol Pin

Num. TQFP

P5.0 P5.1 P5.2 P5.3 P5.14 P5.15

XTAL1 XTAL245

97 98 99 100 1 2

Pin Num. MQFP

99 100 1 2 3 4

6 7

Input Outp.

I I I I I I

I O

Function

Port 5 is a 6-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 also serve as (up to

4) analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Input T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Input

XTAL1: Input to the oscillator amplifier and input to

the internal clock generator XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed.

Data Sheet 6 1999-07

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Table 1 Pin Definitions and Functions (continued)

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Symbol Pin

Num. TQFP

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5

P3.6 P3.7

P3.8 P3.9 P3.10 P3.11 P3.12

P3.13 P3.15

7 8 9 10 11 12

13 14

15 16 17 18 19

20 21

Pin Num. MQFP

9 10 11 12 13 14

15 16

17 18 19 20 21

22 23

Input Outp.

I/O I/O I O I I

I I

I/O I/O O I/O O O I/O O O

Function

Port 3 is a 15 -bit bid irectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 3 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: SCL0 I2C Bus Clock Line 0 SDA0 I2C Bus Data Line 0 CAPIN GPT2 Register CAPREL Capture Input T3OUT GPT1 Timer T3 Toggle Latch Output T3EUD GPT1 Timer T3 External Up/Down Ctrl.Inp T4IN GPT1 Timer T4 Count/Gate/Reload/

Capture Input T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2 Count/Gate/Reload/

Capture Input MRST SSC Master-Rec. / Slave-Trans. Inp/Outp. MTSR SSC Master-Trans. / Slave-Rec. Outp/Inp. T×D0 ASC0 Clock/Data Output (Async./Sync.) R×D0 ASC0 Data Input (Async.) or I/O (Sync.) BHE WRH SCLK SSC Master Clock Outp. / Slave Clock Inp. CLKOUT System Clock Output (=CPU Clock) FOUT Programmable Frequency Output

External Memory High Byte Enable Signal,

External Memory High Byte Write Strobe

Note: Pins P3.0 and P3.1 are open drain outputs only.

Data Sheet 7 1999-07

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Table 1 Pin Definitions and Functions (continued)

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Symbol Pin

Num. TQFP

P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6

24 25 26 27 28 29 30

31 33 O External Memory Read Strobe. RD is activated for

Pin Num. MQFP

26 27 28 29 30 31 32

Input Outp.

O O O O O O O

Function

Port 4 is a 7-bit bidi rectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 4 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 4 is selectable (TTL or special). Port 4 can be used to output the segment address lines: A16 Least Significant Segment Addre ss Line A17 Segment Address Line A18 Segment Address Line A19 Segment Address Line A20 Segment Address Line A21 Segment Address Line A22 Most Significant Segment Address Line

every external instruction or data read access.

WR WRL

READY

ALE 34 36 O Address Latch Enable Output. Can be used for latching

32 34 O External Memory Write Strobe. In WR-mode this pin is

activated for every external data write access. In WRL mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection.

33 35 I Ready Input. When the Ready function is enabled, a

high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level . An internal pullup device will hold this pin high whe n nothing is driving it.

the address into externa l memory or a n address latch in the multiplexed bus modes.

Data Sheet 8 1999-07

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Table 1 Pin Definitions and Functions (continued)

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Symbol Pin

Num. TQFP

EA 35 37 I External Access Enable pin. A low level at this pin

PORT0

P0L.0-7 P0H.0-7

3845 4855

Pin Num. MQFP

4047 5057

Input Outp.

IO PORT0 consists of the two 8-bit bidirectional I/O ports

Function

during and after Reset forces the C161PI to begin instruction execution out of external memory. A high level forces execution out of the internal program memory.

"ROMless" versions must have this pin tied to ‘0’.

P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of external bus configurations, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7 P0H.0 – P0H.7: I/O D8 - D15

Multiplexed bus modes:

Data Path Width: 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 - A15 AD8 - AD15

PORT1

P1L.0-7 P1H.0-7

Data Sheet 9 1999-07

5663 6673

5865 6875

IO PORT1 consists of the two 8-bit bidirectional I/O ports

P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.

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Table 1 Pin Definitions and Functions (continued)

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Symbol Pin

Num. TQFP

Pin Num. MQFP

Input Outp.

Function

RSTIN 76 78 I/O Reset Input with Schmitt-Trigger characteristics. A low

level at this pin while the oscillator is running resets the C161PI. An internal pullup resistor permits powe r-on

reset using only a capacitor connected to

. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN

line is internally pulled low for th e duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table.

Note: To let the reset configuration of PORT0 settle

and to let the PLL lock a reset duration of ca. 1 ms is recommended.

RST OUT

NMI

77 79 O Internal Reset Indication Output. This pin is set to a low

level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT

remains low until the EINIT (end of initialization) instruction is executed.

78 80 I Non-Maskable Interrupt Input. A high to low transition

at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI C161PI to go into power down mode. If NMI

pin must be low in order to force the

is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI

should be pulled high externally.

Data Sheet 10 1999-07

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Table 1 Pin Definitions and Functions (continued)

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Symbol Pin

Num. TQFP

P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7

79 80 81 82 83 84 85 86

P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15

87 88 89 90 91 92 93 94

Pin Num. MQFP

81 82 83 84 85 86 87 88

89 90 91 92 93 94 95 96

Input Outp.

O O O O O I/O I/O I/O

I I I I I I I I

Function

Port 6 is an 8 -bit bid irectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The Port 6 pins also serve for alternate functions: CS0 CS1 CS2 CS3 CS4 SDA1 I SCL1 I SDA2 I

Chip Select 0 Output Chip Select 1 Output Chip Select 2 Output Chip Select 3 Output Chip Select 4 Output

C Bus Data Line 1

C Bus Clock Line 1

C Bus Data Line 2

Note: Pins P6.7-5 are open drain outputs only.

Port 2 is an 8 -bit bid irectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The Port 2 pins also serve for alternate functions: EX0IN Fast External Interrupt 0 Input EX1IN Fast External Interrupt 1 Input EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input EX4IN Fast External Interrupt 4 Input EX5IN Fast External Interrupt 5 Input EX6IN Fast External Interrupt 6 Input EX7IN Fast External Interrupt 7 Input

AREF

AGND

Data Sheet 11 1999-07

95 97 - Reference voltage for the A/D converter. 96 98 - Reference ground for the A/D converter.

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Table 1 Pin Definitions and Functions (continued)

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Symbol Pin

Num. TQFP

6, 23, 37, 47, 65, 75

3, 22, 36, 46, 64, 74

Pin Num. MQFP

8, 25, 39, 49, 67, 77

5, 24, 38, 48, 66, 76

Input

Function

Outp.

- Digital Supply Voltage: + 5 V or + 3 V during normal operati on and idle mode. ≥ 2.5 V during power down mode

- Digital Ground.

Note: The following behaviour differences must be observed when the bidirectional reset

is active:

• Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset.

• The reset indication flags always indicat e a long hardware reset.

• The PORT0 configuration is treated like on a hardware reset. Especially the bootstrap loader may be activated when P0L.4 is lo w.

• Pin RSTIN

may only be connected to external reset devices with an open drain output

driver.

• A short hardware reset is extende d to th e duration of the internal reset sequence.

Data Sheet 12 1999-07

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Functional Description

The architecture of the C161PI combines advantages of both RISC and CISC processors and of advanced p eripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161PI.

Note: All time specifications refer to a CPU clock of 25 MHz

(see definition in the AC Characteristics section).

XTAL

(no

internal

ROM)

OSC

Oscillator

(input: 16MHz;

(16MHz)

prescaler

PLL

or direct drive)

I²C-Bus

Interface

XRAM

2 KByte

Port 6

Port 0

(16-bit NON MUX Data / Addresses)

XBUS

CS Logic

Instr./Data

External Instr./Data

External

Bus

(MUX

only) &

XBUS

Control,

(4 CS)

Channel

10-bit

8-bit ADC

Port 5

&&RUH

&38&RUH

&38

3(&

Interrupt Controller 11 ext. IR

Interr upt Bus

Peripheral Data

USART

ASC BRG

Sync.

Channel

(SPI) SSC BRG

GPT 1

T 2 T 3 T 4

GPT 2

T 5 T 6

RTC

Data Data

Port 2Port 3Port 4 Port 1

Internal

RAM

.%\WH

Dual Port

Watchdog

C161RI V0.1

Figure 4 Block Diagram

Data Sheet 13 1999-07

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Memory Organization

The memory space of the C161PI is confi gured in a Von Neumann ar chitecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made dire ctly bitaddressable.

1 KByte of on-chip Internal RAM (IRAM) is provided as a storage for user defined variables, for the system stack, general p urpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0,

…, RL7, RH7) so-called Gene ral P urpose Registers (GPRs). 1024 bytes (2 * 512 bytes) of the a ddress space are reserved for the Special Fun ction

Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for futu re members of the C166 Family.

2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed.

In order to meet the needs of designs wh ere more memory is re quired tha n is pr ovided on chip, up to 8 MBytes of external RAM and/or ROM can be connected to the microcontroller.

Data Sheet 14 1999-07

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External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be progra mmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows:

– 16-/18-/20-/23-bit Addresses, 16-bit Data, Demultip lexed – 16-/18-/20-/23-bit Addresses, 16-bit Data, Multiplexed – 16-/18-/20-/23-bit Addresses, 8-bit Data, Multiplexed – 16-/18-/20-/23-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus mo des, addresses are output on PORT1 and data is input/ output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independ ent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which allow to access differe nt resources with different bus characteristics. These address windows are arrange d hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS external glue logic. The C161PI offers the possibility to switch the CS unlatched mode. In thi s mode the interna l filter log ic is switched off and the CS are directly generated from the ad dress. The unla tched CS CSCFG (SYSCON.6).

signals (4 windows plus default) can be generated in order to save

outputs to an

signals

mode is enabled by setting

Access to very slow memories is supported via a particular ‘R eady’ function. For applications which require less than 8 MBytes of external memory space, this

address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no address lin es at all. It outputs all 7 address lines, if an address space of 8 MBytes is used.

Data Sheet 15 1999-07

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Central Processing Unit (CPU)

The main core of the CP U consists of a 4-stage instru ction pipeline, a 16-bit a rithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divid e unit, a bit-mask generator and a barrel shifter.

Based on these hardware provisions, most of the C161PI’s instructions can be executed in just one machine cycle which requ ire s 2 CPU clo cks (4 TCL). For example, shift and rotate instructions are always processed during one machine cycle independent of th e number of bits to be shifted. All multip le-cycle instructio ns have been o ptimized so that they can be executed very fast as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so called ‘Jump Cache’, reduces the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

Figure 5 CPU Block Diagram

Data Sheet 16 1999-07

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The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the avail able internal RAM space. For easy paramet er passing, a register bank may overlap others.

A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow.

The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C161PI instruction set which includes the following instruction classes:

– Arithmetic Instructions – Logical Instructions – Boolean Bit Manipulation Instructions – Compare and Loop Control Instru ctio ns – Shift and Rotate Instructions – Prioritize Instruction – Data Movement Instructions – System Stack Instructions – Jump and Call Instructions – Return Instructions – System Control Instructions – Miscellaneous Instructions

The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing mo des are provided to specify the required operand s.

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Interrupt System

With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C161PI is capable of reacting very fast to the occurrence of non-deterministic events.

The architecture of the C161PI supports several mechanisms for fast and flexible response to service requests th at can be generated from various sources internal or external to the microcontro ller. Any of these interrupt req uests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is

‘stolen’ from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer betwe en any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when perfor ming in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the correspond ing source related vector lo cation. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C161PI has 8 PEC cha nnels each of which offers such fast interrupt-driven d ata transfer capabilities.

A separate control re gister which co ntains an interrupt r equ est flag, an in terrupt en able flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be progra mmed to one o f sixteen i nterrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location.

Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individual trap (interrupt) number.

The following table shows all of the possible C161PI interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not used by associated peripherals, may be used to

generate software controlled interrupt re quests by setting the respective interrupt request bit (xIR).

Data Sheet 18 1999-07

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Table 2 C161PI Interrupt Nodes

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Source of Interrupt or PEC Service Request

Request Flag

Enable Flag

Interrupt Vector

Vector Location

External Interrupt 0 CC8IR CC8IE CC8INT 00’0060 External Interrupt 1 CC9IR CC9IE CC9INT 00’0064 External Interrupt 2 CC10IR CC10IE CC10INT 00’0068 External Interrupt 3 CC11IR CC11IE CC11INT 00’006C External Interrupt 4 CC12IR CC12IE CC12INT 00’0070 External Interrupt 5 CC13IR CC13IE CC13INT 00’0074 External Interrupt 6 CC14IR CC14IE CC14INT 00’0078 External Interrupt 7 CC15IR CC15IE CC15INT 00’007C GPT1 Timer 2 T2IR T2IE T2INT 00’0088 GPT1 Timer 3 T3IR T3IE T3INT 00’008C GPT1 Timer 4 T4IR T4IE T4INT 00’0090 GPT2 Timer 5 T5IR T5IE T5INT 00’0094 GPT2 Timer 6 T6IR T6IE T6INT 00’0098 GPT2 CAPREL

CRIR CRIE CRINT 00’009C

H H H

H H H H

H H

H H H H

Trap Number

A/D Conversion

ADCIR ADCIE ADCINT 00’00A0

Complete A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4 ASC0 Transmit S0TIR S0TIE S 0TINT 00’00A8 ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011C

ASC0 Receive S0RIR S0RIE S0RINT 00’00ACH2B ASC0 Error S0EIR S0EIE S0EINT 00’00B0 SSC Transmit SCTIR SCTIE SCTINT 00’00B4 SSC Receive SCRIR SCRIE SCRINT 00’00B8

SSC Error SCEIR SCEIE SCEINT 00’0 0BCH2F I2C Data Transfer

XP0IR XP0IE XP0INT 00’0100

Event I2C Protocol Event XP1IR XP1IE XP1INT 00’0104 X-Peripheral Node 2 XP2IR XP2IE XP2INT 00’0108 PLL Unlock / RTC XP3IR XP3IE XP3INT 00’010C

H H H

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The C161PI also provides an excellent mechanism to identify and to process exceptions

or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branchin g to a dedicated vector ta ble location). The occurence of a hardware trap is add iti onally signi fie d by a n individ ual bit in the trap fla g register ( TFR). Except when another higher prio ritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error conditions that can arise during run-time:

Table 3 Hardware Trap Summary Exception Condition Trap

Flag

Trap Vector

Vector Location

Reset Functions:

Hardware Reset Software Reset Watchdog Timer Ov erflow

RESET RESET RESET

00’0000 00’0000 00’0000

Class A Hardware Traps:

Non-Maskable Interrupt Stack Overflow Stack Underflow

NMI STKOF STKUF

NMITRAP STOTRAP STUTRAP

00’0008 00’0010 00’0018

Class B Hardware Traps:

Undefined Opco de Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access

UNDOPC PRTFLT ILLOPA ILLINA ILLBUS

BTRAP BTRAP BTRAP BTRAP BTRAP

00’0028 00’0028 00’0028 00’0028 00’0028

Reserved [2C

Software Traps:

TRAP Instruction

Any [00’0000 00’01FC in steps of 4

Trap Number

H H H

H H H H H

– 3CH][0BH –

00 00

02 04 06

0A 0A 0A 0A 0A

H H H

Any

–

[00

]

H H H H H

]

–

]

Trap Prio

III III III

II II II

I I I I I

Current CPU Priority

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General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for man y different time related tasks such a s event timing and coun ting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate indep endently in a number of different modes, or may be concatenated with another timer of the same module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Time r Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the

operation of a timer is controlled by the ‘gate’ leve l on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 16 TCL.

The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate eg. position tracking.

In Incremental Interface Mo de the GPT1 timers (T2, T3 , T4) can be directly con nected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are intern ally derived from these two input sign als, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt inpu t.

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on a port pin (T3OUT) eg. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time per iods with high resolution.

In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 are captured into T2 or T4 in response to a signal at their asso ciated input p ins (TxIN). Timer T3 is reloa ded with the contents of T2 or T4 triggered either by an e xternal signa l or by a se lectable state tra nsition of its toggle latch T3OTL. When both T2 and T4 are configured to al ternately reload T3 on opposite state transi tions of T3OTL with the low and hi gh times of a PWM signal, this signal can be constantly generated without software intervention.

Data Sheet 21 1999-07

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T2EUD

T2IN

T3IN

T3EUD

T4IN

CPU

2n : 1

Mode

Control

Mode

Control

Mode

Control

U/D

GPT1 Timer T2

Reload

Capture

GPT1 Timer T3 T3OTL

U/D

Capture

Reload

GPT1 Timer T4

Interrupt Request

Toggle FF

T3OUT

Other Timers

Interrupt Request

T4EUD

U/D

MCT02141

Figure 6 Block Diagram of GPT1

With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/ underflow.

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The state of this latch may be used to clock ti mer T5. The overflows/underflows of timer T6 can additionally be used to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external sig nal tr ansition on the corresponding port pin (CAPIN), and timer T5 may optionally b e cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead.

The capture trigger (ti mer T5 to CAPREL) may also be gen erated upon transitions of

GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode.

CAPIN

CPU

2n : 1

Mode

Control

MUX

CT3

Mode

Control

GPT2 Timer T5

Clear

Capture

GPT2 CAPREL

GPT2 Timer T6

U/D

T6OTL

Interrupt Request

T6OUT

Other Timers

Mcb03999C.vsd

Figure 7 Block Diagram of GPT2

Data Sheet 23 1999-07

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