Infineon AURIX User Manual

CPU

Central Processing Unit

AURIX™ TC3xx Microcontroller Training V1.0 2020-06

Please read the Important Notice and Warnings at the end of this document

› Code optimization (e.g. reduced code

size by using 16-bit & 32-bit instructions)

CPU

Central Processing Unit

Key Features Customer Benefits

Highlights

› The Central Processing Unit (CPU)

comprises of an Instruction Fetch Unit, an Execution Unit, a General Purpose Register File (GPR), a CPU Slave interface (CPS), and Floating Point Unit (FPU).

Temporal protection system

Flexible memory protection

Wide range of supported instructions

› Time bounded real time operation

› Multiple protection ranges over the

memory

Central Processing Unit

Program Memory Interface

Data Memory Interface

Instruction Fetch Unit

Execution Unit

General Purpose Register File

FPU

CPS

CPU

Comunication with other

modules through CPS

CPU

Temporal protection system

A very common problem of real time systems is given by the tasks with a defined runtime. Overrunning this can lead to overall program failures. Each core has a temporal protection system (TPS) formed out of three 32-bit decrementing counters clocked by the primary clock.

The operating system (OS) loads the

expected runtime at task‘s start and a

trap is generated when the counter reaches 0. Generating a trap, and not an interrupt, protects the system in

case the task is allowed to disable

interrupts for periods of time.

Based on the counters‘ values

(together with the time-out flags), it is ensured that the real time application is

time bounded.

Central Processing Unit

Program Memory Interface

Data Memory Interface

Instruction Fetch Unit

Execution Unit

General Purpose Register File

FPU

CPS

CPU

Generate a trap

Two 32-bit

counters

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