IMS 740 User Manual

IMS

INTERNATIONAL

GENERAL

The

Model

64K

bytes

DESCRIPTION

740 I/O

of

Dynamic

PROCESSOR

RAM Synchronous/Asynchronous programmable

interval timers interrupt structure,

The

Z-80A

Data Channels. data serial

to be

data

parallel

SIO

interfaces

acted

to be

I/O

( two

and

used

Parallel interface

The SIO

upon

placed

on the

lines compatible

the

converts

by the

MODEL

I/O

PROCESSOR BOARD

is a

with

single board computer

Parity,

2K

communication

with

for

baud

rates),

to the

Z-80A

CPU to Two

input

serial data

system. Output data

RS-232C

port.

740

bytes

of

IPL

channels with

Bell Z-80

S-100

801

Automatic Calling

internally-prioritized

BUS

asynchronous

from

the

is

converted

with a Z-80A

PROM,

Two

MODEM

Host

processor.

or

synchronous Serial

RS-232C port

from

*

A

processor,

programmable

control,

Unit,

Ten

Four

vectored

to

parallel

to

The

8255A

slave The

one

Z-80 A CPU

MODEL

slot

brought

Equipment the

RS-232C

proper operation

S-100

8255A

Due

CPU

the

BUS

Mode 2 S-100

to the

modules

master S-100

intelligent

intercommunication

Programmable

bus.

740 I/O

in the

Series

out to a 3M

(DTE)

to

port (DTE

of

terminal.

TO I/O

PROCESSOR INTERFACE

drastic reduction

are

becoming

CPU and

I/O

controllers.

must

Peripheral Interface circuit interfaces

Processor consists

5000

26-pin

header.

connect directly

to

DTE)

BUS to

more

used

When

be

supported. master/slave interface through The

S-100

8255A

scheme

implemented

required

BUS

is

selected

and the

to

READ

interface

is

supported

through

S-100 vector interrupt structure.

allow

from

the and

slave

WRITE

of a

or

8000

Computer Systems. Each serial

The

RS-232C

to a

the

RS-232C cable wires

Slave

of

Z-80A

hardware

common.

to

control

multiple

The IMS 740

the use of the

by an

the use of a

Z-80A

CPU to

to the

the

single printed circuit board

ports

MODEM.

are

designed

To

connect a terminal directly

must

CPU

costs,

multiple

8255A

Interface

system designs

A

Model

451

Z-80A

CPUs

are

utilized, a method

Z-80A 8255A 8255A

Mode 2 bidirectional bus.

which

standard S-100

The

generate

bidirectional bus.

slave

module

is

configued

I/O

Address decode

Z-80A slave logic

the

ACK-

which

CPU is

modules

S-100

BUS to the

that

RS-232C

as

Data Terminal

be

interchanged

utilize multiple

configured

which

of

is

implemented

in

Mode

and

STB- signals

occupies

port

is

to

for

as

act as

processor

as a

2. The select

is

D00740

REV 1.0

IMS

INTERNATIONAL

October

20,

1981

Page

1

S-100 I/O

Configuring

DEVICE ADDRESS SELECTION (JE)

JE

A7

1

A6 2 A5

3

A4

4

A3

5

A2

6

12 11 10

and

9

8

7

Programming

SHUNT SHUNT

Example shown

8255A BASIC OPERATION

I/O

IN IN

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OFF = 1 ON = 0

DEVICE

places

ADDRESS

XO X2

XO X2 X3

X3 X3 X3

X3 X3 X3 X3 X3 X3 X3 X3 X3 X3

OPERATION PORT PORT

COH

740

board

A -> C ->

S-100 S-100 S-100

OOH 01H 02H 03H 08H 09H OAH OBH

OCH ODH

OEH

OFH

at I/O

S-100 S-100

BUS -> BUS -> BUS ->

_>

0 -> 1 -> 0 -> 1 -> 0 ->

1 ->

0

->

1 ->

0 ->

1 ->

0 ->

1 ->

address

BUS

1

P

OR

POR'

CON

CONTROL(Mode

CON'

PCO

Control/Data

PCO

Res

PCI

Reset

PCI PC4

INTE2

INT

PC4

PCS

IBF

PCS

PC6

INTE1

PC6 PC7

OBF

PC7

40H - 43H

2)

Flag

Slave

(INTE

for IBF

for OBF

D00740

REV 1.0

IMS

INTERNATIONAL

October

20,

1981

Page

2

8255A

Bidirectional

Bus I/O

Control

Signal Definition

^

INTE2

INTR+

output OBF- (Output

to

PORT

ACK-

INTE1

(Interrupt

operations.

A.

(Acknowledge)

(The

INTE

Request) Used

buffer

:

•-

..*<•-••

Flip-Flop Associated

STB- (Strobe Input) IBF +

PORT

8255A

(Input

Buffer

A.

(The

INTE

Definition

Flip-Flop Associated

to

Full) Used

:

Enables

Used

to

load data

to

•.

the

tri-state

-.-.••,

Full) Indicates

Summary

interrupt

indicate

output

.

- . *'

with

into

that

OBF) Controlled

the

data

with

the

that

:•:••

•

t

:.

input

has

IBF)

S-100

the

;

:

-

buffer

.

BUS

S-100

•••;•• of

'

Master

BUS has

•-•*>': PORT

,'.

'-,

by bit

latch

of

PORT

been loaded into

Controlled

by bit

for

both input

written

• '• •• A.

•

set/reset

!

A.

the

input

set/reset

data

of

....

.

PC6.

latch

PC4.

or

out

i.

of

PAO-PA7

PBO-PB7 PCO

CONTROL/DATA

PCI

RESET SLAVE

PC2

UNUSED

PC3

INTR+

PC4

STB-/INTE2

PCS

IBF +

PC6

ACK-/INTE1

PC7

OBF-

INTERRÜPT

I/O

DATA

UNUSED

SELECTION

JF

VIO VII VI2 VI3 VI4 VI5 VI6 VI7

1 2 3 4 5 6

7 8

. . .

. .

.

. 16 . 15 . 14 . 13 . 12 . 11 . 10 . 9

FLAG

•

OPTION

(JF)

The

installing

Port

A

Note:

Interrupt

For

of a

(PCS

more

SHUNT

INTR).

detail

will

attach

regarding

the

programming

Peripheral Design Handbook.

'

*•"••

IMS

t>

v

-4

D00740

selected

REV 1.0

VIx

Interrupt Level

of the

October

to

Parallel

8255A

see the

INTERNATIONAL

20,

1981 Page

Intel

3

I/O

Processor

Configuring

and

Programming

4

„

.

•*

.1

'

**.

Z-80A

JA

1.

.8

2. .7 3 -

-fi

4. .5

Z-80A

JB

1. .6

2. .5

3. .4

S-100

SIO

PORT A Receive

RxCA RxCA-

TxCA TxCA-

from

from from from

Z-80A RS-232

Z-80A

RS-232

PORT B Receive

RxTxCB-

from

and

Z-80A RS-232 RS-232

RESET DISABLE SHUNT

Transmit

CTC

TO

(this connection

Interface

CTC

T0(requires a shunt)

Interface

Transmit

CTC

Tl(thi s connection

Interface

(JD)

Band

dock

PIN 17

PIN 15

Baud

dock

PIN 17

PIN 15

Selection

Signal Signal

Selections

Signal Signal

is

etched) DD DB

is

etched) DD DB

(JA)

(JB)

.

,,

JD

1.

2.

SHUNT SHUNT

OFF = ON =

Normal

Local

740

mode

Test

J

mode

D00740

REV 1.0

IMS

October

INTERNATIONAL

20,

1981

Page

4

MODEL

740

Signal

Name

Protective

Signal Ground

Transmit

(Data

to

Receive Data

(Data

Request

from

To

Ground

Data

MODEM)

Send

SERIAL

PORT

TO

RS-232C

Circuit

£\£\

AR

£\D

RA

DA

RR

DD

r*A

v>A

CONNECTOR CABLE

±

/

7v

1

/

o

x

—

\

^__

3

/

—

4

\_______

^

— — — — — — —

—

>

Controller

1

3

5

7

Clear

Data

To

Set

Send

Ready

Data Terminal Ready

Ring

Data

Indicator

Carrier

Detect

Transmit Clock

(Clock

From

MODEM)

r*R

vxJD

pr»

vA^

f~*T\

OJJ

r*f?

Vxui

T»R

c;s_______

\

/

6

Oft\

_ __ _ _

O 0 N _ — — —

OS

o ^ — — — — — — —

i

ti

\

___

>

9

> 4

Receive Clock

(Clock

From

MODEM)

DD

D00740

17>

REV 1.0

> 8

IMS

INTERNATIONAL

October

20,

1981

Page

9

Z-80A

PORT A INPUT

AO A2

DSS-

A3

DLO-

A4

C/D+

A5

IBF+

A6

OBF-

A7

PER+

PIO

Definition

BITS

PORT B OUTPUT

BO

NB1+

Bl

NB2 +

B2

NB4+

B3

NB8+

B4

DPR-

B5

CRQ-

B6

ROMEN

B7

PERR+

BITS

+

Summary

BELL

8255A 8255A 8255A

RAM

BELL BELL BELL BELL BELL BELL ROM RAM

801

PCO PCS PC7

PARITY

801 801 801 801 801

801

ENABLE

PARITY

DATA DATA LINE

SET

STATUS

OCCUPIED CONTROL/DATA INPUT BUFFER

OUTPUT

BUFFER

ERROR

NUMBER NUMBER NUMBER NUMBER

BIT 1

BIT 2

BIT

4

BIT

8

DIGIT PRESENT

CALL

REQUEST

RESET

FLAG FÜLL

FÜLL

NOTE:

For

Components

more

see

Zilog

detail

Data

regarding

Book

or

Technical Manuals.

the

programming

of the

Z-80A Microcomputer

D00740

REV 1.0

IMS

INTERNATIONAL

October

20,

1981

Page

6

<O

0

H

<

HD

«u.

l-

CC LU

«o

Ck

0

UJ

O O

cc

CL

O

O O

MODEL

740

Pl

SIGNAL LIST

1 2 3 4 5 6

10 11

12

13

14

15

16

17

18

19

20

21

22 23

24

25

26

27

28 29

30

31

32 33

34 35

36

37

38 39 40 41

42 43

44

45

46

47

48

49

50

7 8 9

SIGNAL

+8V

+16V

VIOVII-

VI2-

VI3-

VI4-

VI5-

VI6-

VI7-

GND

A5 + A4 + A3 +

DO1

+

DOO

+

DO4

+

DO5

+

DO6

+

DI2 +

DI3 +

DI7 +

sOUT+

SINP

+

GND

51

52 53

54 55

56

57

58 59 60 61 62 63 64 65 66

67

68

69

70

71

72 73

74

75 76 77

78

79

80

81 82 83

84

85

86 87 88 89 90 91

92 93 94 95

96

97

98

99

100

SIGNAL

+8V

-16V

GND

pWR-

pDBIN

AO

+

A1 + A2 + A6

+

A7 +

DO2

+

DO3

+

DO7

+

DI4 + DI5

+

DI6

+

DI1 +

DIO

+

POC-

GND

D00740

REV 1.0

BIS

INTERNATIONAL

October

209 1981 Page

8

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MODEL

740

BELL

801 ACÜ

Signal

Name

Frame Ground

Signal

Digit

Abandon

Call

Ground

Present

Call-Retry

Request

PARALLEL PORT

ACU

Connector

Circuit

FGD

SGD

DPR

ACR

CRQ

TO

RS-232C

7>-

2>-

3>

4>

CONNECTOR CABLE

Controller

>

1

> 5

Present

Power

Data

Number

Indication

Set

Bit

Number

1

Bit 2

Bit

4

8

Digit

PND

PWI

DSS

NB1

NB2

NB4

NB8

5>

6>

14>

15>

17>

>

9

>25

>

2

>

4

>

6

>

8

o

Data

Line

Occupied

DLO

D00740

22>

REV 1.0

!IMS

October

INTERNATIONAL

20,

1981

Page

10

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IMS 740 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual