IMP IMP1232LPSN, IMP1232LPS-2, IMP1232LPS, IMP1232LPN, IMP1232LPCMA Datasheet

©

1999 IMP, Inc. 408-432-9100/www.impweb.com 1

Key Features

◆

Pin compatible with the Dallas Semiconductor
DS1232LP/1232LPS
— 40% lower supply current

◆

5V supply monitor

◆

Selectable watchdog period

◆

Debounce manual push-button reset input

◆

Precision temperature-compensated voltage
reference and comparator

◆

Power-up, power-down and brownout detection

◆

250ms reset time

◆

Active LOW open-drain reset and active HIGH
push-pull output

◆

Selectable trip point tolerance: 5% or 10%

◆

Low-cost, surface mount packages: 8/16-pin
SO, 8-pin DIP and 8-pin MicroSO

◆

Wide operating temperature –40°C to +85°C
(N/EPA suffixed devices)

Block Diagram

IMP1

IMP1

232LP/LPS

232LP/LPS

POWER MANAGEMENT

5V

5V µµ

P P

P Pooww

er Suppl

er Suppl

y Monit

y Monit

or and

or and

RReset Cir

eset Cir

cuit

cuit

– Select

– Select

able T

able Trriipp-P-P

oint T

oint T

oler

oler

ance

ance

and W

and W

atc

atc

hdog P

hdog Perer

iod

iod

– Push-Butt

– Push-Butt

on R

on R

eset

eset

The IMP1232LP/LPS microprocessor supervisor can halt and restart a
“hung-up” or “stalled” microprocessor, restart a microprocessor after a
power failure, and debounce and interface a manual push-button micro­processor reset switch. The low-power supervisors feature 40% lower
supply current than the pin compatible Dallas Semiconductor
DS1232LP/LPS.

Precision temperature compensated reference and comparator circuits
monitor the 5V, V

CC

input voltage. During power-up or when the V

CC

power supply falls outside selectable tolerance limits, both the RESET
and RESET become active. When V

CC

rises above the threshold voltage,
the reset signals remain active for an additional 250ms minimum,
allowing the power supply and system microprocessor to stabilize. The
trip point tolerance signal, TOL, selects the trip level tolerance to be
either 5- or 10-percent.

Each device has both a push-pull, active HIGH reset output and an open
drain, active LOW reset output.

A debounced manual reset input activates the reset outputs for a mini­mum period of 250ms.

Also included is a watchdog timer to stop and restart a microprocessor
that is “hung-up”. Three watchdog time-out periods are selectable:

150ms, 610ms and 1,200ms. If the ST input is not strobed
LOW before the time-out period expires, a reset is issued.

Devices are available in 8-pin DIP, 8/16-pin SO and com­pact 8-pin MicroSO packages.

CC

TD

ST

8 (15)

3 (6)

1 (2)

2 (4)

7 (13)

V

CC

40kΩ

Timebase Selection

5%/10% Tolerance

Selection

Reference

Push Button

Debounce

Watchdog

Watchdog

Transition Detector

IMP1232LP/LPS

(16-Pin Package)

+

–

Reset &

Watchdog Timer

4 (8)

GND

V

TOL

PBRST

6 (11)

5 (9)

RESET

RESET

1232_03.eps

2

408-432-9100/www.impweb.com

©

1999 IMP, Inc.

Pin Configuration

IMP1

IMP1

232LP/LPS

232LP/LPS

Pin Descriptions

Ordering Information

1232_02.eps

IMP1232LPSN

13

ST

14 NC

15 V

CC

16

4

3

2

1NC

TD

12 NC5NC
11 RESET6TOL
10 NC7NC

9 RESET8GND

NC

PBRST

NC

DIP/SO/MicroSO SO

rebmuNtraPegakcaP

erutarepmeTgnitarepO

egnaR

ylppuSmumixaM

(tnerruC µ )A

gnirotinoMegatloV

noitacilppA

PL2321PMIPID-80C° 07otC° 03V5

SPL2321PMIOS-610C° 07otC° 03V5

2-SPL2321PMIOS-80C° 07otC° 03V5

AMCPL2321PMIOSorciM-80C° 07otC° 03V5

AMEPL2321PMIOSorciM-804– C° 58otC° 03V5

NPL2321PMIPID-804– C° 58otC° 03V5

2-NSPL2321PMIOS-804– C° 58otC° 03V5

NSPL2321PMIOS-6104– C° 58otC° 03V5

spe.10t_2321

Pin Number Pin Number

8-Pin P

8-Pin Pacackkagagee11

6-Pin P

6-Pin Pacackkagagee

NName

ame

FFunction

unction

1 2 PBRST Debounced manual pushbutton RESET input
2 4 TD Watchdog time delay selection. (t

TD

= 150ms for TD = GND, tTD= 610ms

for TD = Open, and tTD=1200ms for TD = VCC)

3 6 TOL Selects 5% (TOL connected to GND) or 10% (TOL connected to V

CC

) trip

point tolerance
4 8 GND Ground
5 9 RESET Active HIGH reset output. RESET is active:

1. If VCCfalls below the reset voltage trip point.

2. IfPBRST is LOW.

3. If ST is not strobed LOW before the timeout period set by TD expires.

4. During power-up.
6 11 RESET Active LOW reset output. (See RESET)
7 13 ST Strobe Input
815V

CC

5V power

— 1, 3, 5, 7, 10, NC No internal connection

12, 14, 16

PBRST

1V

IMP1232LP

2

TD

IMP1232LPS-2

IMP1232LPCMA

3

TOL

GND

IMP1232LPEMA

4

8

CC

7ST
6 RESET
5

RESET

1232_01.eps

©

1999 IMP, Inc. 408-432-9100/www.impweb.com 3

IMP1

IMP1

232LP/LPS

232LP/LPS

Absolute Maximum Ratings

Electrical Characteristics

Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V

Voltage on ST, TD . . . . . . . . . . . . . . . . . . . . . –0.5V to V

CC

+ 0.5V

Voltage on PBRST, RESET, RESET . . . . . . . . –0.5V to V

CC

+ 0.5V

Operating Temperature Range . . . . . . . . . . . – 40°C to 85°C

(N/EMA version)
0°C to 70°C

Soldering Temperature . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Storage Temperature . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Voltages measured with respect to ground.
These are stress ratings only and functional operation is not implied.

Parameter Symbol Conditions Min Typ Max Units

Supply Voltage (VCC)V

CC

4.5 5.5 V

ST and PBRST Input High Level V

IH

2V

CC

+ 0.3V V

ST and PBRST Input Low Level V

IL

–0.3 0.8 V

VCCTrip Point (TOL = GND) V

CCTP

4.50 4.62 4.74 V

VCCTrip Point (TOL = VCC)V

CCTP

4.25 4.37 4.49 V

Watchdog Time-Out Period t

TD

TD = GND 62.5 150 250 ms

Watchdog Time-Out Period t

TD

TD = V

CC

500 1200 2000 ms

Watchdog Time-Out Period t

TD

TD floating 250 610 1000 ms

Output Voltage V

OH

I = –500µA, Note 3 VCC- 0.5V VCC- 0.1V V

Output Current I

OH

Output = 2.4V , Note 2 – 8 –10 mA

Output Current I

OL

Output = 0.4V, 10 mA

Input Leakage I

IL

Note 1 –1.0 1.0 µA

RESET Low Level V

OL

0.4 V
Internal Pull-Up Resistor Note 1 40 kΩ
Operating Current (CMOS) I

CC1

30 µA

Input Capacitance C

IN

5pF

Output Capacitance C

OUT

10 pF

PBRST Manual Reset t

PB

PBRST = V

IL

20 ms

Minimum Low Time
Reset Active Time t

RST

250 610 1000 ms

ST Pulse Width t

ST

Note 4 20 ns

VCCFail Detect to t

RPD

58µs

RESET or RESET
VCCSlew Rate t

F

4.75V to 4.25V 300 µs

PBRST Stable LOW to t

PDLY

20 ms

RESET and RESET Active
V

CC

Detect to RESET or t

RPU

t

RISE

= 5µs 250 610 1000 ms

RESET Inactive
VCCSlew Rate t

R

4.25V to 4.75V 0 ns

Unless otherwise stated, 4.5V ≤ VCC≤ 5.5V and over the operating temperature range of 0°C to +70°C (–40°C to +85°C for N/EMA
devices). All voltages are referenced to ground.

Notes: 1. PBRST is internally pulled HIGH to VCCthrough a nominal 40kΩ resistor.

2. RESET is an open drain output.

3. RESET remains within 0.5V of V

CC

on power-down until VCCfalls below 2V. RESET remains within 0.5V of ground on power-down

until V

CC

falls below 2.0V.

4. Must not exceed the minimum watchdog time-out period (t

TD

). The watchdog circuit cannot be disabled. To avoid a reset, ST must be

strobed.