IDTech N150X4-L05 User Manual

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Engineering Specification

Type 15. 0 XGA Color TFT/LCD Module

Model Name:N150X4-L05

Docume nt Control Number : OEM N150X 4-L05-0 1

Note:Specification is subject to change without notice. Consequently it is better to contact to

International Display Technology before proceeding with the design

of your product incorporating this module.

Sales Support

International Display Technology

Engineering Specification

i Contents

i Contents ii Record of Revision

1.0 Handling Precautions

2.0 General Description

2.1 Characteristics

2.2 Functional Block Diagram

3.0 Absolute Maximum Ratings

4.0 Optical Characteristics

5.0 Signal Interface

5.1 Connectors

5.2 Interface Signal Connector

5.3 Interface Signal Description

5.3.1 E-EDUD

5.4 Interface Signal Electrical Characteristics

5.4.1 Signal Electrical Characteristics for LVDS Receiver

5.4.2 LVDS Receiver Internal Circuit

5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection

5.5 Signal for Lamp connector

6.0 Pixel format image

7.0 Parameter guide line for CFL Inverter

8.0 Interface Timings

8.1 Timing Characteristics

8.2 Timing Definition

9.0 Power Consumption

10.0 Power ON/OFF Sequence

11.0 Mechanical Characteristics

12.0 National Test Lab Requirement

Engineering Specification

ii Record of Revision

SummaryPageDocument RevisionDate

AllOEM N150X4-L05-01February 03,2003

First Edition for customer. Based on Internal Spec."N150X4-IPI-01"

Engineering Specification

1.0 Handling Precautions

O If any signals or power lines deviate from the power on/off sequence, it may cause s horten the life of the

LCD module.

O The LCD panel and the CFL are made of glass and m ay break or crack if dropped on a hard surfac e, so

please handle them with care.

O CMOS ICs are included in the LCD panel. They should be handled with care, to prevent electrostatic

discharge.

O Do not press the reflector sheet at the LCD module to any directions. O Do not stick the adhesive tape on the reflector sheet at the back of the LCD module. O Please handle with care when mount in the system cover. Mechanical damage for lamp cable/lamp

connector may cause safety problems.

O Small amount of materials having no flammability grade is used in the LCD module. The LCD module

should be supplied by power complied with requirements of Limited Power Source (2.5, IEC60950 or UL60950), or be applied exemption conditions of flammability requirements (4.7.3.4, IEC60950 or UL60950) in an end product.

O The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit (2.4, IEC60950 or

UL60950).

O The fluorescent lamp in the liquid crystal display(LCD) contains mercury. Do not put it in trash that is

disposed of in landfills. Dispose of it as required by local ordinances or regulations.

O Never apply detergent or other liquid directly to the screen. O Wipe off water drop immediately. Long contact with water may cause discoloration or spots. O When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents or

abrasives.

O Do not touch the front screen surface in your system, even bezel. O Gently wipe the covers and the screen with a soft cloth.

O

The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by International Display Technology for any infringements of patents or other right of the third partied which m ay result from its use. No license is granted by implication or otherwise under any patent or patent rights of International Display Technology or others.

O

The information contained herein may be changed without prior notice. It is therefore advisable to contact International Display Technology before proceeding with the design of equipment incorporating this product.

Engineering Specification

2.0 General Description

This specification applies to the Type 15.0 Color TFT/LCD Module 'N150X4-L05'. This module is designed for a display unit of a notebook style personal computer. The screen format and electrical interface are intended to support the XGA (1024(H) x 768(V)) screen. Support color is native 262k colors ( RGB 6-bit data driver ). All input signals are LVDS(Low Voltage Differential Signaling) interface compatible. This module does not contain an inverter card for backlight.

Engineering Specification

2.1 Characteristics

The following item s are charac teris tics sum ma ry on the table under 25 degree C condition:

SPECIFICATIONSCHARACTERISTICS ITEMS 38Screen Diagonal [cm]

304.128(H) x 228.096(V)Active Area [mm] 1024(x3) x 768Pixels H x V [pixels]

0.297(per one triad) x 0.297Pixel Pitch [mm] R.G.B. Vertical StripePixel Arrangement Normally WhiteDisplay Mode

2

]

200 Typ. (Screen Center, ICFL = 6.0mA)White Luminance [cd/m 400 : 1 Typ. 300:1 Min Contrast Ratio

Viewing Angle

Electrical Interface

Temperature Range [deg. C]

CR>=10:1 H: +/-85 deg., V:+/-85 deg. Typ. CR>=100:1 H: +/-40 deg., V:+/-40 deg. Typ.

x:0.328 +/-0.030, y:0.337 +/- 0.030Color Chromaticity HardCoat Only (No Anti-Glare Treatment)Surface Treatment 60msec Typ.; 120ms Max. (@25degC)Optical Rise + Fall Time +3.3 VNominal Input Voltage [VDD]

1.6 Typ. (All White Pattern), 2.2 Max (worst pattern)Logic Power Consumption [watt]

3.8Typ.(@ICFL=6.0mA) CFL Power Consumption [watt] 585 Max.Weight [grams]

317.3(W) x 242.0(H) x 6.2(D) Typ.Physical Size [mm] 4 pairs Single LVDS(Single)

Native 262K colors ( RGB 6-bit data driver )Support Color 0 to +50 (Operating)

-20 to +60 (Storage, Shipping) 100 mmCFL cable length

V

r

Y

X

p

(

)

g

r

V

Engineering Specification

2.2 Functional Block Diagram

The following diagram shows the functional block of the Type 15.0 Color TFT/LCD Module.

Signal Connecto

<4

airs LVDS>

FI-XB30SL-HF10

LCD DRIVE CARD

-Driver

RxIN0 RxIN1 RxIN2

RxCLKIN

EEDID CLCEEDID DataEEDID

DD

DD VDD VDD

GND

LCD

Controlle

DC-DC

EEDID

Chip

Converte Ref circuit

-Driver

TFT ARRAY/CELL

1024(R/G/B) x 768

Backlight Unit

CCFL Connector

BHSR-02VS-1

CCFL High Voltate CCFL Low Volta

e

JST

y

Engineering Specification

3.0 Absolute Maximum Ratings

Absolute maximum ratings of the module is as follows :

mbol Item

Conditions Unit Max MinS

V+4.0-0.3VDDSupply Voltage VVDD+0.3-0.3Other InputsInput Voltage of Signal Vrms2,000-VinvLamp Ignition Voltage mArms7-ICFLCFL Current

A single pulse20mA / 50ms-ICFLPCFL Peak Inrush Current

Note :

1. Maximum Wet-Bulb should be 39 degree C and No condensation.

deg.C+500TOPOperating Temperature %RH958HOPOperating Relative Humidity deg.C+60-20TSTStorage Temperature %RH955HSTStorage Relative Humidity

(Note 1) (Note 1) (Note 1) (Note 1)

G Hz1.5 10-200Vibration

Rectangle waveG ms50 18Shock

Engineering Specification

4.0 Optical Characteristics

The optical characteristics are measured under stable conditions as follows under 25 degree C condition:

SpecificationConditionsItem

NoteTyp.

Viewing Angle (Degrees)

Response Time (ms)

White Luminance (cd/m2) ICFL 6.0 mA

Horizontal (Right) KP10 (Left)

Vertical (Upper) KP10 (Lower)K:Contrast Ratio

85 85

0.328White x

0.337White y

200Typ.

Center

-

-400Contrast ratio

120 Max.60Rising + Falling

--Red xColor

--Red yChromaticity

--Green x(CIE)

--Green y

--Blue x

--Blue y +0.030 +0.030

160Min

Center

Engineering Specification

5.0 Signal I nterf ace

5.1 Connectors

Physical interface is described as for the connector on module. These connectors are capable of accommodating the following signals and will be following components.

Connector Name / Designation Manufacturer Type / Part Number

For Signal Connector JAE FI-XB30SL-HF10 FI-X30M, FI-X30C2LMating Receptacle/Part Number

For Lamp Connector JST BHSR-02VS-1 SM02B-BHSS-1Mating Type / Part Number

Engineering Specification

5.2 Interface Signal Connector

Signal NamePin #Signal NamePin #

GND16GND1

RxCLKIN-17VDD2

RxCLKIN+18VDD3 4 5 6 7 8

VEDID (Note 2, 3)

Reserved (Note 1)

CLKEEDID (Note 2, 4)

DataEEDID (Note 2, 4)

RxIN0-

Note :

1. 'Reserved' pins are not allowed to connect any other line.

2. This LCD Module complies with "VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA

STANDARD Release A, Revision 1" and supports "EEDID version 1.3".

3. V

4. Both CLK

power source shall be the limited current circuit which has not exceeding 1A. (Reference Document :

EEDID

"Enhanced Display Data Channel (E-DDC

line and DATA

EEDID

line are pulled up with 10k ohm resistor to V

EEDID

TM

) Proposed Standard", VESA)

panel, respectively.

GND19

NC20 NC21

GND22

NC23 NC24RxIN0+9

GND25GND10

NC26RxIN1-11 NC27RxIN1+12

GND28GND13

NC29RxIN2-14 NC30RxIN2+15

power source line at LCD

EEDID

Voltage levels of all input signals are LVDS compatible (except VDD, EEDID). Refer to "Signal Electrical Characteristics for LVDS Receiver", for voltage levels of all input signals.

5.3 Interface Signal Description

Signal Description

DescriptionSignal Name LVDS differential data input (Red0-Red5, Green0)RxIN0+, RxIN0LVDS differential data input (Green1-Green5,Blue0-Blue1)RxIN1+, RxIN1LVDS differential data input (Blue2-Blue5, HSync, VSync, DSPTMG)RxIN2+, RxIN2LVDS differential clock inputRxCLKIN+, RxCLKIN+3.3V Power SupplyVDD GroundGND

Note :

O Input signals shall be low or Hi-Z state when VDD is off.

Engineering Specification

DescriptionSIGNAL NAME

+RED5 +RED4 +RED3 +RED2 +RED1 +RED0

+GREEN 5 +GREEN 4 +GREEN 3 +GREEN 2 +GREEN 1 +GREEN 0

+BLUE 5 +BLUE 4 +BLUE 3 +BLUE 2 +BLUE 1 +BLUE 0

Red Data 5 (MSB) Red Data 4 Red Data 3 Red Data 2 Red Data 1 Red Data 0 (LSB)

Red-pixel Data: Each red pixcel's brightness data consists of these 6 bits pixel data. Green Data 5 (MSB)

Green Data 4 Green Data 3 Green Data 2 Green Data 1 Green Data 0 (LSB)

Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel data. Blue Data 5 (MSB)

Blue Data 4 Blue Data 3 Blue Data 2 Blue Data 1 Blue Data 0 (LSB)

Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel data.

DTCLK

Data Clock:The typical frequency is 65.0 MHz. The signal is used to strobe the pixel data and the DSPTMG .

When the signal is high, the pixel data shall be valid to be displayed. +DSPTMG(DSP)

VSYNC(V-S)

Vertical Sync:The signal is synchronized to DTCLK . Both active high/low signal acceptable.

HSYNC(H-S)

Horizontal Sync:The signal is synchronized with DTCLK . Both active high/low signals are acceptable.

Power SupplyVDD GroundGND EEDID 3.3 V Power SupplyVEEDID EEDID ClockCLKEDID EEDID DataDataEEDID

Note : Output signals except VEEDID, CLKEEDID and DataEEDID from any system shall be Hi-Z state when VDD is off.

Engineering Specification

5.3.1 E-EDID

E-EDID detail in this LCD module is in the following table.

(hex)

Header00 - 07

00

12 - 13

/ Revision

14 - 18

26 - 35

36 - 47

48 - 59

5A - 6B

6C - 7D

Parameter / Features

Standard Timing Identification

Detailed Timing / Monitor Description #1

Monitor Description #2 Detailed Timing / Monitor Description #3

Detailed Timing / Monitor Description #4

80 1E 17 78 0ABasic Display

(Note 1)Color Characteristics19 - 22

01 01 01 01 01 01 01 01 01

30 18 88 36 00 30 E4 10 00 00 18 (Note 1)Detailed Timing /

00 00 00 FE 00 49 44 54 0A 20 20 20 20 20

20 20 20 20 00 00 00 FE 00 4E 31 35 30 58 34 0A 20 20 20 20 20 20

(Note 1)Checksum7F

RemarkData (hex)DescriptionAddress Header, Fixed00 FF FF FF FF FF FF "IDT"24 94ID Manufacturer Name08 - 09

Product Code0D 00 ID Product Code0A - 0B Unused00 00 00 00ID Serial Number0C - 0F Unused00Week of Manufacture10 Unused00Year of Manufacture11 Ver1.301 03EDID Structure Version

Active Area : 30.41cm x

22.81cm, Gamma : 2.2

Unused00 00 00Established Timing23 - 25 Unused01 01 01 01 01 01 01

Typical Timing64 19 00 40 41 00 26

Manufactuerer name "IDT"

Manufacturer P/N "N150X4"

No extension00Extension Flag7E

Note:

1.Detail data contents shall be determined with concurrence between user and International Display Technology(IDTech).

Engineering Specification

5.4 Interface Signal Electrical Characteristics

5.4.1 Signal Electrical Characteristics for LVDS Receiver

The LVDS receiver equipped in this LCD module is compatible with ANSI/TIA/TIA-644 standard. Electrical Characteristics

ConditionsUnit MaxTypMinSymbolParameter Vcm=+1.2VmV +100 VthDifferential Input High Threshold Vcm=+1.2VmV -100VtlDifferential Input Low Threshold

mV600100|Vid|Magnitude Differential Input Voltage

Vth - Vtl = 200mVV1.51.21.0VcmCommon Mode Voltage Vth - Vtl = 200mVmV+50-50VcmCommon Mode Voltage Offset

Note :

O Input signals shall be low or Hi-Z state when VDD is off.

Voltage Definitions

Engineering Specification

Measurement System

Timming Requirements

ConditionsUnitMaxTypMinSymbolParameter

MHz676550fcClock Frequency

ns20.0015.3814.93tcCycle Time

fc = 65MHz, tCCJ < 50ps,

ps500TsuData Setup Time (Note 1)

Vth-Vtl = 400mV,

ps500ThdData Hold Time (Note 2)

Vcm = 1.2V, Vcm = 0 fc = 65MHz, Tsu=Thd=900psps+150-150tCCJCycle-to-cycle jitter (Note 3) fc = 65MHz, Tsu=Thd=900psps/clk20tCJavgCycle Modulation Rate (Note 4)

Note :

1. All values are at VDD=3.3V, Ta=25 degree C.

2. See figure "Timing Definition" and "Timing Definition(detail A)" for definition.

3. Jitter is the magnitude of the change in input clock period.

4. This specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100

clock cycles. Figure "Cycle Modulation Rate" illustrates a case against this requirement. This specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps.

Timing Definition

Engineering Specification

Timing Definition(detail A)

Note: Tsu and Thd are internal data sampling window of receiver. Trskm is the system skew margin; i.e., the sum of cable skew, source clock jitter, and other inter-symbol interference, shall be less than Trskm.

Cycle Modulation Rate

Engineering Specification

5.4.2 LVDS Receiver Internal Circuit

The following figure shows the internal block diagram of the LVDS receiver. This LCD module equips termination resistors for LVDS link.

5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection

Following the suggestions below will help to achieve optimal results.

O Use controlled impedance media for LVDS signals. They should have a matched differential

impedance of 100 ohm.

O Match electrical lengths between traces to minimize signal skew. O Isolate TTL signals from LVDS signals. O For cables, twisted pair, twin, or flex circuit with close coupled differential traces are recommended.

Engineering Specification

5.5 Signal for Lamp Connector

Signal NamePin #

Lamp High Voltage1

2

Lamp Low Voltage

Engineering Specification

6.0 Pixel format image

Following figure shows the relationship of the input signals and LCD pixel format image. Even and odd pair of RGB data are sampled at a time

.

1st Line

768th Line

R

0

R

G

GB

B

1

RGB

RG

1022 1023

R

B

R

B

G

B

RG

R

B

G

Engineering Specification

7.0 Parameter guide line for CFL Inverter

MINPARAMETERSYMBOL

CONDITIONUNITSMAXD.P

(Note 1)

(L63)

White Luminance (Center)

2

200-

-

[mArms]7.06.03.0CFL currentICFL

]-

Ta=25[deg. C][cd/m

Ta=25[deg. C]

(Note 2,5)

ICFLP

[mA]20CFL Peak Inrush

Current

[kHz]7040CFL FrequencyFCFL

Ta=25[deg. C]

(Note 2,6)

Ta=25[deg. C]

(Note 3)

Ta=0[deg. C][Vrms]1,600Inverter Ignition VoltageVCFLi

VCFL

Ta=25[deg. C][Vrms]640CFL Voltage

(Reference)

PCFL

[W]3.8CFL Power

consumption

Ta=25[deg. C]

(Note 4)

Note :

1. Design Point

2. If it exceeds MIN/MAX values, then"CFL Life" , "ON/OFF Cycle", and "SAFETY" will not be guaranteed.

3. CFL Frequency should be carefully determined to avoid interference between inverter and TFT LCD.

4. Calculated value for reference (ICFL x VCFL = PCFL).

5. It should be employed the inverter which has `Duty Dimming`, if ICFL is less than 4[mA].

6. Duration: 50msec MAX

Engineering Specification

The following chart is Luminance versus Lamp Current for your reference.

Engineering Specification

8.0 Interface Timings

Basically, interface timings should match the VESA 1024x768 / 60 Hz (VG901101) manufacturing guide line timing. These timings described here are not actual input timings of LCD module but output timings of SN75LVDS86DGG(Texas Instruments) or equivalent.

8.1 Timing Characteristics

NoteUnitMAXTYPMINSymbol

MHz67.0065.0050.00DTCLK Frequencyfdck nsec20.0015.3814.93DTCLK cycle timetck

tck204713441206X total timetx tck102410241024X active timetacx

KHz48.363H frequencyHsync

2tck1368H-Sync widthHsw 2tck5101608H back porchHbp

tck240H front porchHfp

tx1023806777Y total timety tx768768768Y active timetacy

Hz616055Frame rateVsync

tx61V-sync WidthVw tx31V-sync front porchVfp

1tx63297V-sync back porchVbp

Note1 : Vbp should be static. Note2 : Hsw+Hbp> 32 [tck]

- The timing interval between V-Sync falling edge and H-Sync rising edge should be fixed between each V-Frame.(V-Sync and H-Sync polarity are assumed to be positive in this case.)

Engineering Specification

8.2 Timing Definition

1344 dot

H-Sync

DSPTMG

V-Sync

DSPTMG

3H

136 dot

6H

38H

160 dot24 dot

1024 dot

29H

768H

pp

ge

[V]

(

)

g

yp

Engineering Specification

9.0 Power Consump tion

Input power specifications are as follows;

MinPARAMETERSYMBOL

CONDITIONUNITSMaxT

VDD

VDDrp

Volta VDD PowerPDD

VDD CurrentIDD

Drive Ri

e

le Volta

TBD

(TBD)

Load Capacitance 20[uF][V]3.63.33.0Logic/LCD Drive

[W]1.6

All Black Pattern VDD=3.3

[W]2.2

Max. Pattern, VDD=3.6[V]

[mA]490

All Black Pattern, VDD=3.3[V]

[mA]640

Max Pattern, VDD=3.0[V]

[mVp-p]100Allowable Logic/LCD

Engineering Specification

10.0 Power ON/OFF Sequence

VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from any system shall be Hi-Z state or low level when VDD is off.

30ms min.

VDD

0 V

Signals

0 V

Lamp On

0 V

10%

90%

0.1ms min.

30ms max.

0 min. 0 min.

10%

200ms min. 0 min.

10%

90%

10% 10%

10%

Engineering Specification

11.0 Mechanical Characteri stics

Engineering Specification

12.0 National Test Lab Requirement

The display module will satisfy all requirements for compliance to UL 60950, 3rd Edition U.S.A. Information Technology Equipment

CAN/CSA-C22.2 No. 60950-00 Canada, Information Technology Equipment IEC 60950 (3rd. Ed.) International, Information Technology Equipment EN 60950 (3rd. Ed.) International, Information Technology Equipment (European Norm for IEC60950)

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IDTech N150X4-L05 User Manual

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