idtech ITUX97H Datasheet

Engineering Specification

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Engineering Specification

Type 15.0 UXGA Color TFT/LCD Module

Model Name:ITUX97H

Document Control Number : OEM I-97H-03

Note:Specification is subject to change without notice. Consequently it is better to contact to

International Display Technology before proceeding with the design

of your product incorporating this module.

Sales Support

International Display Technology

February 1,2002 OEM I-97H-03 1/34

Engineering Specification

i Contents

i Contents ii Record of Revision

1.0 Handling Precautions

2.0 General Description

2.1 Characteristics

2.2 Functional Block Diagram

3.0 Absolute Maximum Ratings

4.0 Optical Characteristics

5.0 Signal Interface

5.1 Connectors

5.2 Interface Signal Connector

5.3 Interface Signal Description

5.4 Interface Signal Electrical Characteristics

5.4.1 Signal Electrical Characteristics for LVDS Receiver

5.4.2 LVDS Receiver Internal Circuit

5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection

5.5 Inverter Signal connector

5.6 Inverter Signal Description

5.7 Inverter Signal Electrical Characteristics

6.0 Pixel format image

7.0 Interface Timings

7.1 Timing Characteristics

7.2 Timing Definition

8.0 Power Consumption

9.0 Power ON/OFF Sequence

10.0 Mechanical Characteristics

11.0 National Test Lab Requirement

February 1,2002 OEM I-97H-03 2/34

Engineering Specification

ii Record of Revision

Date

Revision

OEM I-97H-02December 10,2001

OEM I-97H-03February 1,2002

AllOEM I-97H-01October 30,2001

6 9 23 24

23 24

SummaryPageDocument

First Edition for customer. Based on Internal Specification EC F79204 as of September 7,2001. To adopt a "Burst mode Inverter".

To update Backlight Power Consumption. To add Min. value of White Luminance. To update Electrical Specifications and Dimming. To update the Luminance versus the SMBUS Data.

To update Inverter Signal Electrical Characteristics. To update Luminance versus SMBUS Data.

February 1,2002 OEM I-97H-03 3/34

Engineering Specification

1.0 Handling Precautions

1) Since front polarizer is easily damaged, pay attention not to scratch it.

2) Be sure to turn off power supply when inserting or disconnecting from input connector.

3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots.

4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents or abrasives.

5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface.

6) Since CMOS LSI is used in this module, take care of static electricity and insure human earth when handling.

7) Do not open nor modify the Module Assembly.

8) Do not press the reflector sheet at the back of the module to any directions.

9) In case if a Module has to be put back into the packing container slot after once it was taken out from the container, do not press the center of the CFL Reflector edge. Instead, press at the far ends of the CFL Reflector edge softly. Otherwise the TFT Module may be damaged.

10) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the Interface Connector of the TFT Module.

11) After installation of the TFT Module into an enclosure ( Notebook PC Bezel, for example), do not twist nor bent the TFT Module even momentary. At designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the TFT Module from outside. Otherwise the TFT Module may be damaged.

12) The fluorescent lamp in the liquid crystal display (LCD) contains mercury. Do not put it in trash that is disposed of in landfills. Dispose of it as required by local ordinances or regulations.

13) Small amount of materials having no flammability grade is used in the LCD module. The LCD module should be supplied by power complied with requirements of Limited Power Source (2.11, IEC60950 or UL1950), or be applied exemption conditions of flammability requirements (4.4.3.3, IEC60950 or UL1950) in an end product.

14) Never apply detergent or other liquid directly to the screen.

O

The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by International Display Technology for any infringements of patents or other right of the third partied which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of International Display Technology or others.

O

The information contained herein may be changed without prior notice. It is therefore advisable to contact International Display Technology before proceeding with the design of equipment incorporating this product.

February 1,2002 OEM I-97H-03 4/34

Engineering Specification

2.0 General Description

This specification applies to the Type 15.0 Color TFT/LCD Module 'ITUX97H'.

This module is designed for a display unit of notebook style personal computer.

The screen format and electrical interface are intended to support the UXGA (1600(H) x 1200(V))screen.

Support color is native 262k colors ( RGB 6-bit data driver ).

All input signals are LVDS interface compatible.This module contains an inverter card for backlight.

February 1,2002 OEM I-97H-03 5/34

Engineering Specification

2.1 Characteristics

The following items are characteristics summary on the table under 25 degree C condition:

SPECIFICATIONSITEMS

381 Screen Diagonal [mm]

304.8(H) x 228.6(V)Active Area [mm]

1600(x3) x 1200Pixels H x V

0.1905(per one triad) x 0.1905Pixel Pitch [mm]

R.G.B. Vertical StripePixel Arrangement

Normally WhiteDisplay Mode

2

Typical White Luminance [cd/m SMData=00H:

]

150 Typ.(Center) 140 Typ.(5 Points average)

200 : 1 Typ.Contrast Ratio

30Typ., 50Max.(each) Optical Rise Time/Fall Time [msec]

Nominal Input Voltage [Volt] VDD 5VSUS,5VALW line PWR_SRC line

Backlight Power Consumption [watt] PWR_SRC=14.4V SMData=00H

Electrical Interface (Logic)

Temperature Range (degree C) Operating Storage (Shipping)

+3.3 Typ. +5.0 Typ. +14.4 Typ.

2.4 Typ. 3.4 Max.Logic Power Consumption [watt]

5.6 Typ.

665 Typ. 700 Max.Weight [grams]

317.3(W) x 242.0(H) x 11.2(D) Typ.11.5(D)Max.Physical Size [mm]

6-bit digital video for each color R/G/B, 3 sync, Clock (8 pairs LVDS)

Panel IDs,SMB_CLK,SMB_DAT,FPVEEElectrical Interface (Inverter)

Native 262K colors ( RGB 6-bit data driver )Support Color

0 to +50

-20 to +60

February 1,2002 OEM I-97H-03 6/34

Engineering Specification

2.2 Functional Block Diagram

The following diagram shows the functional block of the Type 15.0 Color TFT/LCD Module.

X-Driver

Y-Driver

< 8 pairs LVDS >

6bit color data

for R/G/B (even/odd)

DTCLK(even/odd) DSPTMG Vsync Hsync

EEDID

V

EEDID

CLK

EEDID

Data

VDD

GND

LCD-DRIVE Connector

A

J

E

F

r

e

v

n

I

M

O

L

Panel IDsp

SMB_CLK SMB_DAT FPVEE PWR_SRC 5VSUS

5VALW GND

LCD DRIVE

CARD

EVEN

PIXEL

ODD PIXEL

Dual LVDS RECEIVER

LCD

Controller

TFT ARRAY/CELL

1600(R/G/B) x 1200

G/A

F

t

1

o

6

0

r

0

9

DC-DC

Converter Ref circuit

p

0

3

(

i

p

6

1

(

Backlight Unit

)

n

)

n

i

EEDID Chip

X

-

I

S

H

B

0

-

3

r

e

t

E

X

c

e

n

C

n

o

5

2

1

-

7

0

INVERTER

The first LVDS port transmits even pixels while the second LVDS port transmits odd pixels.

February 1,2002 OEM I-97H-03 7/34

Engineering Specification

3.0 Absolute Maximum Ratings

Absolute maximum ratings of the module is as follows :

5VALW

SMB_DAT

Conditions Unit Max MinSymbol Item

V+4.0-0.3VDDSupply Voltage

V+5.5-0.35VSUS,

V+25-0.3PWR_SRC

V+VDD+0.3-0.3VinInput Voltage of Signal

V+5.5-0.3FPVEE

V+7-1SMB_CLK

Operating Temperature

Operating Humidity

Note 1 : Maximum Wet-Bulb should be 39 degree C and No condensation.

Note 1deg.C+500TOP

Note 1%RH958HOP

Note 1deg.C+60-20TSTStorage Temperature

Note 1%RH955HSTStorage Humidity

G Hz1.5 10-200Vibration

G ms50 18Shock

Rectangle wave

February 1,2002 OEM I-97H-03 8/34

Engineering Specification

4.0 Optical Characteristics

The optical characteristics are measured under stable conditions as follows under 25 degree C condition:

SpecifiationConditionsItem

NoteTyp.

Viewing Angle (Degrees)

White Luminance

2

) SMData=00H

(cd/m

Horizontal (Right) K}10 (Left)

Vertical (Upper) K}10 (Lower)K:Contrast Ratio

40 40

15 30

150

(Center)

140 (5 Points Average)

-

100 Min.200Contrast ratio

50 Max.30RisingResponse Time

50 Max.30Falling(ms)

-0.569 Red xColor

-0.332 Red yChromaticity

-0.312 Green x(CIE)

-0.544 Green y

-0.149 Blue x

-0.132 Blue y

- 0.313 White x

- 0.329 White y

120 Min.

(Center) 112 Min. (5 Points

Average)

February 1,2002 OEM I-97H-03 9/34

Engineering Specification

5.0 Signal Interface

5.1 Connectors

Physical interface is described as for the connector on module. These connectors are capable of accommodating the following signals and will be following components.

Connector Name / Designation

Manufacturer

Type / Part Number

Mating Type / Part Number

For Signal Connector

JAE

FI-XB30S-HF10

FI-X30M

For Inverter ConnectorConnector Name / Designation

MolexManufacturer

52207-1690Type / Part Number

(FPC)Mating Type / Part Number

February 1,2002 OEM I-97H-03 10/34

)

(

)

(

)

Signa

e

#

Signa

#

Engineering Specification

5.2 Interface Signal Connector

l Name Pin

1

GND

l Nam

GND17FG

ReCLKIN-18GND2

ReCLKIN+19VDD3

GND20VDD4

5

7

8

(Note 2,3

Reserved, Note 1) 6

(Note 2,4

RoIN0-21V

RoIN0+22NC

GND23CLK

RoIN1-24Data

RoIN1+25ReIN0-9

GND26ReIN0+10

RoIN2-27GND11

RoIN2+28ReIN1-12

GND29ReIN1+13

RoCLKIN-30GND14

RoCLKIN+31ReIN2-15

32ReIN2+16

FG(GND

Note:

1. 'Reserved' pins are not allowed to connect any other line.

2. This LCD Module complies with "VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA

STANDARD Release A, Revision 1" and supports "EEDID version 1.3". This module uses Serial EEPROM BR24C02FV (ROHM) or compatible as a EEDID function.

3. V

4. Both CLK

power source shall be the current limited circuit which has not exceeding 1A. (Reference Document :

EEDID

"Enhanced Display Data Channel (E-DDC

line and Data

EEDID

line are pulled-up with 10K ohm resistor to V

EEDID

TM

) Proposed Standard", VESA)

power source line at LCD

EEDID

panel, respectively.

Voltage levels of all input signals are LVDS compatible (except VDD,EEDID). Refer to "Signal Electrical Characteristics for LVDS(*)", for voltage levels of all input signals.

February 1,2002 OEM I-97H-03 11/34

Engineering Specification

5.3 Interface Signal Description

PIN #

5

7 8

NAME

EEDID

Description SIGNAL

Frame Ground FG1 Ground GND2 +3.3V Power SupplyVDD3 +3.3V Power SupplyVDD4 EEDID 3.3V Power SupplyV Reserved Reserved6 EEDID ClockCLK EEDID DataData Negative LVDS differential data input (Even R0-R5, G0)ReIN0-9 Positive LVDS differential data input (Even R0-R5, G0)ReIN0+10 Ground GND11 Negative LVDS differential data input (Even G1-G5, B0-B1)ReIN1-12 Positive LVDS differential data input (Even G1-G5, B0-B1)ReIN1+13 Ground GND14 Negative LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)ReIN2-15 Positive LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)ReIN2+16 GroundGND17 Negative LVDS differential clock input (Even)ReCLKIN-18 Positive LVDS differential clock input (Even)ReCLKIN+19 GroundGND20 Negative LVDS differential data input (Odd R0-R5, G0)RoIN0-21 Positive LVDS differential data input (Odd R0-R5, G0)RoIN0+22 Ground GND23 Negative LVDS differential data input (Odd G1-G5, B0-B1)RoIN1-24 Positive LVDS differential data input (Odd G1-G5, B0-B1)RoIN1+25 GroundGND26 Negative LVDS differential data input (Odd B2-B5)RoIN2-27 Positive LVDS differential data input (Odd B2-B5)RoIN2+28 GroundGND29 Negative LVDS differential clock input (Odd)RoCLKIN-30 Positive LVDS differential clock input (Odd)RoCLKIN+31 Frame GroundFG32

Note:

1. Input signals of odd and even clock shall be the same timing.

2. The module uses a 100ohm resistor between positive and negative data lines of each receiver input.

3. Even: First Pixel , Odd: Second Pixel

February 1,2002 OEM I-97H-03 12/34

(EVEN/ODD)

Engineering Specification

DescriptionSIGNAL NAME

RED Data 5 (MSB)+RED 5 (ER5/OR5) RED Data 4+RED 4 (ER4/OR4) RED Data 3+RED 3 (ER3/OR3) RED Data 2+RED 2 (ER2/OR2) RED Data 1+RED 1 (ER1/OR1) RED Data 0 (LSB)+RED 0 (ER0/OR0)

Red-pixel Data: Each red pixel's brightness data consists of these 6 bits pixel data. GREEN Data 5 (MSB)+GREEN 5 (EG5/OG5) GREEN Data 4+GREEN 4 (EG4/OG4) GREEN Data 3+GREEN 3 (EG3/OG3) GREEN Data 2+GREEN 2 (EG2/OG2) GREEN Data 1+GREEN 1 (EG1/OG1) GREEN Data 0 (LSB)+GREEN 0 (EG0/OG0)

Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel data.

BLUE Data 5 (MSB)+BLUE 5 (EB5/OB5) BLUE Data 4+BLUE 4 (EB4/OB4) BLUE Data 3+BLUE 3 (EB3/OB3) BLUE Data 2+BLUE 2 (EB2/OB2) BLUE Data 1+BLUE 1 (EB1/OB1) BLUE Data 0 (LSB)+BLUE 0 (EB0/OB0)

(EVEN/ODD)

VSYNC (V-S)

HSYNC (H-S)

EEDID

Note: Output signals except V

Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel data. Data Clock: The typical frequency is 81MHz.DTCLK

The signal is used to strobe the pixel +data and the +DSPTMG

When the signal is high, the pixel data shall be valid to be displayed.+DSPTMG (DSP) Vertical Sync: This signal is synchronized with DTCLK. Both active high/low signals are acceptable. Horizontal Sync: This signal is synchronized with DTCLK. Both active high/low signals are acceptable. Power SupplyVDD Ground GND EEDID 3.3V Power SupplyV EEDID ClockCLK EEDID DataData

EEDID

,CLK

and Data

EEDID

from any system shall be Hi-Z state when VDD is off.

EEDID

February 1,2002 OEM I-97H-03 13/34

Engineering Specification

5.4 Interface Signal Electrical Characteristics

5.4.1 Signal Electrical Characteristics for LVDS Receiver

The LVDS receiver equipped in this LCD module is compatible with ANSI/TIA/TIA-644 standard.

Electrical Characteristics

mV600100|Vid|Magnitude Differential Input Voltage V | Vid |

mV+50-50VcmCommon Mode Voltage Offset

Note:

VcmCommon Mode Voltage

| Vid |

0.825+ 2

2.4 - 2

O Input signals shall be low or Hi-Z state when VDD is off.

O All electrical characteristics for LVDS signal are defined and shall be measured at the interface

connector of LCD (see "Measurement system").

ConditionsUnit MaxTypMinSymbolParameter

Vcm=+1.2VmV +100 VthDifferential Input High Threshold Vcm=+1.2VmV -100VtlDifferential Input Low Threshold

Vth - Vtl = 200mV Vth - Vtl = 200mV

Voltage Definitions

February 1,2002 OEM I-97H-03 14/34

Engineering Specification

Measurement system

February 1,2002 OEM I-97H-03 15/34

Engineering Specification

Switching Characteristics

ConditionsUnitMaxTypMinSymbolParameter

MHz83.081.075.0fcClock Frequency MHz69.066.461.0fcClock Frequency (FPT Mode)

ns13.312.312.0tcCycle Time

ns16.415.114.5tcCycle Time (FPT Mode) Data Setup Time (Note 2) Data Hold Time (Note 2)

ps500Tsu

ps500Thd

fc = 81MHz, tCCJ < 50ps, Vth-Vtl = 200mV, Vcm = 1.2V, Vcm = 0

ps600ThdData Setup Time (FPT Mode)

(Note 2)

ps600ThdData Hold Time (FPT Mode)

(Note 2)

Cycle-to-cycle jitter (Note 3)

fc = 66.4MHz, tCCJ < 50ps, Vth-Vtl = 200mV, Vcm = 1.2V, Vcm = 0

fc = 81MHz, Tsu=Thd=720psps+150-150tCCJ fc = 66.4MHz, Tsu=Thd=880psps+150-150tCCJCycle-to-cycle jitter

(FPT Mode) (Note 3)

Cycle Modulation Rate (Note 4)

ps/clk20tCJavg

Note 1: All values are at VDD=3.3V, Ta=25 degree C. Note 2: See "Timing Definition" and "Timing Definition(detail A)" for definition. Note 3: Jitter is the magnitude of the change in input clock period. Note 4: This specification defines maximum average cycle modulation rate in peak-to-peak transition within

any 100 clock cycles. This specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps.

February 1,2002 OEM I-97H-03 16/34

Engineering Specification

Timing Definition (Even Port)

February 1,2002 OEM I-97H-03 17/34

Engineering Specification

Timing Definition (Odd Port)

February 1,2002 OEM I-97H-03 18/34

Engineering Specification

Timing Definition(detail A)

Note: Tsu and Thd are internal data sampling window of receiver. Trskm is the system skew margin; i.e., the sum of cable skew, source clock jitter, and other inter-symbol interference, shall be less than Trskm.

February 1,2002 OEM I-97H-03 19/34

Engineering Specification

5.4.2 LVDS Receiver Internal Circuit

Below figure shows the internal block diagram of the LVDS receiver. This LCD module equips termination resistors for LVDS link.

Cycle Modulation Rate

5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection

Following the suggestions below will help to achieve optimal results.

O Use controlled impedance media for LVDS signals. They should have a matched differential

impedance of 100ohm.

O Match electrical lengths between traces to minimize signal skew.

O Isolate TTL signals from LVDS signals.

O For cables, twisted pair, twinax, or flex circuit with close coupled differential traces are recommended.

February 1,2002 OEM I-97H-03 20/34

Engineering Specification

5.5 Inverter Signal connector

Signal NamePin # Signal NamePin #

1 (Note*)

(Note*) Molex Connector No.1 Mark

5VALW9PANEL-ID0

5VSUS10PANEL-ID12

GND11PANEL-ID23

GND12PANEL-ID34

GND13NC5

PWR_SRC14FPVEE6

PWR_SRC15SMB_CLK7

PWR_SRC16SMB_DAT8

February 1,2002 OEM I-97H-03 21/34

Engineering Specification

5.6 Inverter Signal Description

Input connector

Molex

1*

14

15

52207-1690

( FFC/FPC)

FunctionPin

PANEL_ID0

NC5

FPVEE6

GND11 GND12 GND13

PWR_SRC

PWR_SRC16

Voltage

levels

(0,3.3V)typ

(0V,5V)typSMB_CLK7

(0V,5V)typSMB_DAT8

5V typ5VALW9

4.85V to 5.2V5VSUS10

(9V to 21V)

typ

(9V to 21V)

typ

(9V to 21V)

typ

DescriptionTypical(typ)

"1" Open "1" OpenPANEL_ID12

"0" Connect to GNDPANEL_ID23

"1" OpenPANEL_ID34

Control signal input into the inverter to turn the

backlight ON & OFF (3.3V-ON,0V-OFF)

SMBus interface for sending brightness &

contrast information to the inverter/panel

SMBus interface for sending brightness &

contrast information to the inverter/panel

This should be used as power source that stores

the brightness/contrast values & the circuit that

interfaces with SMB_CLK & SMB_DAT

This should be used as power source for the

control circuitry on the inverter.

This power rail should be used as a power rail to

drive the backlight DC-AC converter

This power rail should be used as a power rail to

drive the backlight DC-AC converter

This power rail should be used as a power rail to

drive the backlight DC-AC converter

Note(*) : Molex Connector No.1 Mark

February 1,2002 OEM I-97H-03 22/34

Engineering Specification

5.7 Inverter Signal Electrical Characteristics

Electrical Specifications

5VALW

CONDITIONUNITSMax.Typ.Min.SymbolItem

Ta=25[deg. C] [V]2114.49.0PWR_SRCInput Voltage

[V]5.25.04.855VSUS,

Dimming

*1 : Reference Only

SMBUS Data

SMBUS

[W]6.25.6P(PWR_SRC)Input Power

SMData=00H PWR_SRC=14.4[V]

[W]1.41.0

SMData=0FFH PWR_SRC=14.4[V]

[mW]2515P(5VSUS)

[mW]255P(5VALW)

ON[V]2.0FPVEEON/OFF

OFF[V]0.8FPVEE

[KHz]665952FLamp Frequency

[Hz]164160156FBBurst Frequency

Brightness [%]SMData

Max.Typ.Min.

Brightness

(center) [cd/m

2

]

Lamp Current

(Return side)[mA]

6.5 (*1)150 (*1)-100-00H

1.7 (*1)7.5 (*1)952FFH

Device AddressDevice Identifier

1000101

February 1,2002 OEM I-97H-03 23/34

Engineering Specification

The following chart is the Luminance versus the SMBUS Data for your reference.

February 1,2002 OEM I-97H-03 24/34

Engineering Specification

6.0 Pixel format image

Following figure shows the relationship of the input signals and LCD pixel format image.

Even and odd pair of RGB data are sampled at a time.

Even Odd Even Odd

0 1 1599

1598

1st Line

1200th Line

R

B R

G

B R

G

B

G

B

G

R

B R

G

B R

G

B

G

B

G

February 1,2002 OEM I-97H-03 25/34

Engineering Specification

7.0 Interface Timings

7.1 Timing Characteristics

(VESA UXGA Mode)

UnitMAX.TYP.MIN.SymbolItemSignal

[MHz]83.081.075.0FdckFreqencyDTCLK

[ns]13.312.312.0Tck

[Hz]60.0FvFrame Rate+V-Sync

[ms]16.67Tv

[lines]204612501208Nv

[us]839.840.013.33TvaV-Active Level

[lines]6331Nva

[lines]125466NvbV-Back Porch

[lines]12511NvfV-Front Porch

Note1 : Both positive Hsync and positive Vsync polarity is recommended.

Note2 : When there are invalid timing, Display appears black pattern.

Synchronous Signal Defects and enter Auto Refresh for LCD Module Protection Mode.

[lines]1200mV-Line+DSPTMG

[KHz]75.0FhScan Rate+H-Sync

[usec]13.33Th

[Tck]204710801024Nh

[usec]1.185ThaH-Active Level

[Tck]255968Tha

[Tck]5111528ThbH-Back Porch

[Tck]328ThfH-Front Porch

[usec]9.877ThdDisplay+DSPTMG

[dots]1600nData Even/Odd+DATA

February 1,2002 OEM I-97H-03 26/34

Engineering Specification

(VESA UXGA FPT Mode)

UnitMAX.TYP.MIN.SymbolItemSignal

[MHz]69.066.461.0FdckFreqencyDTCLK

[ns]16.415.114.5Tck

[Hz]60.0FvFrame Rate+V-Sync

[ms]16.67Tv

[lines]204612141208Nv

[us]13.713.7TvaV-Active Level

[lines]6311Nva

[lines]12511NvbV-Back Porch

[lines]125123NvfV-Front Porch

[lines]1200mV-Line+DSPTMG

[KHz]73.0FhScan Rate+H-Sync

[usec]13.74Th

Note1 : Both positive Hsync and positive Vsync polarity is recommended.

Note2 : When there are invalid timing, Display appears black pattern.

Synchronous Signal Defects and enter Auto Refresh for LCD Module Protection Mode.

[Tck]1023912873Nh

[usec]0.121ThaH-Active Level

[Tck]25588Tha

[Tck]511568ThbH-Back Porch

[Tck]488ThfH-Front Porch

[usec]12.053ThdDisplay+DSPTMG

[dots]1600nData Even/Odd+DATA

February 1,2002 OEM I-97H-03 27/34

Engineering Specification

(VESA UXGA Mode)

Typical Vertical Timing Table

Support mode

Tvblk Vertical Blanking

m Active Field

Tvf VSYNC Front Porch

Tv,Nv Frame Time

Tva VSYNC Width

Tvb VSYNC Back Porch

1600 x 1200 at 60Hz (H line rate : 13.3 us)

0.667 ms (50 lines)

Typical Horizontal Timing Table

Support mode

Thblk Horizontal Blanking

1600 x 1200 Dotclock : 162.000 MHz (81.000MHz x2)

3.457 us (560 dots)

(VESA UXGA FPT Mode)

Typical Vertical Timing Table

Support mode

1600 x 1200 at 60Hz (H line rate : 13.7 us)

Tvblk Vertical Blanking

0.192 ms (14 lines)

16.000 ms (1200 lines)

Thd Active Field

9.877 us (1600 dots)

m Active Field

16.440 ms (1200 lines)

0.013 ms (1 line)

Thf HSYNC Front Porch

0.395 us (64 dots)

Tvf VSYNC Front Porch

0.164 ms (12 line)

16.667 ms (1250 lines)

Th,Nh H Line Time

13.333 us (2160 dots)

Tv,Nv Frame Time

16.632 ms (1214 lines)

0.040 ms (3 lines)

Tha HSYNC Width

1.185 us (192 dots)

Tva VSYNC Width

0.014 ms (1 line)

0.613 ms (46 lines)

Thb HSYNC Back Porch

1.877 us (304 dots)

Tvb VSYNC Back Porch

0.014 ms (1 line)

Typical Horizontal Timing Table

Support mode

Thblk Horizontal

Thd Active Field

Blanking

1600 x 1200 Dotclock : 132.75 MHz (66.375MHz x2)

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1.687 us (224 dots)

12.053 us (1600 dots)

Thf HSYNC Front Porch

0.723 us (96 dots)

Th,Nh H Line Time

13.740 us (1824 dots)

Tha HSYNC Width

0.121 us (16 dots)

Thb HSYNC Back Porch

0.844 us (112 dots)

Engineering Specification

7.2 Timing Definition

DSPTMG

-VSYNC

+VSYNC

DSPTMG

-HSYNC

+HSYNC

VIDEO(Even)

Tvf

Thf

Tv

Tvblk

Tva

Thblk Thd

Tha

Tvb

Thb

Th

Tck

0

4

2

m

n-4 n-2

VIDEO(Odd)

DTCLK

5

3

1

n-3

n-1

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Engineering Specification

8.0 Power Consumption

Input power specifications are as follows;

VDD

Voltage

CONDITIONUNITSMaxTypMinPARAMETERSYMBOL

Load Capacitance 68uF[V]3.63.33.0Logic/LCD Drive

VDDrp

Drive Ripple Voltage

VDDns

Drive Ripple Noise

MAX. Pattern : 2dot Vertical sub-pixel Stripe.

[W]3.4VDD PowerPDD

MAX. Pattern, VDD=3.6[V]

[W]2.4VDD PowerPDD

All Black Pattern, VDD=3.3[V]

[mA]940VDD CurrentIDD

MAX Pattern, VDD=3.0[V]

[mA]730VDD CurrentIDD

All Black Pattern, VDD=3.3[V]

[mVp-p]100Allowable Logic/LCD

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Engineering Specification

9.0 Power ON/OFF Sequence

VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from any system shall be Hi-Z state or low level when VDD is off.

150ms min.

VDD

10%

0 V

Signals

0 V

1ms min.

30ms max.

PWR_SRC

0 V

10%

5VALW/5VSUS

0 V

90%

10ms max.

0 min.

90% 90%

10% 10%

100ms min.

20ms min.

180ms min.

0ms min.

90%

0ms min.

90%90%

10%

90%

10ms min.

0ms min.

10% 10%

0 min.

FPVEE

0 V

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10%10%

Engineering Specification

10.0 Mechanical Characteristics

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Engineering Specification

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Engineering Specification

11.0 National Test Lab Requirement

The display module is authorized to Apply the UL Recognized Mark.

Conditions of Acceptability

O This component has been judged on the basis of the required spacings in the Standard for Safety of

Information Technology Equipment, Including Electrical Business Equipment, CAN/CSA C22.2 No.950-95 *UL 1950, Third Edition, including revisions through revision date March 1,1998, which are based on the Fourth Amendment to IEC 950, Second Edition, which would cover the component itself if submitted for Listing.

O The inverter output circuit supplied with this model is a Limited Current Circuit. O The units are supplied by Limited Power Sources. O The terminals and connectors are suitable for factory wiring only. O The terminals and connectors have not been evaluated for field wiring. O A suitable Electrical and Fire enclosure shall be provided.

****** End Of Page ******

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idtech ITUX97H Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual