IDTech ITSX98E, R181E2-L01 Specification

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Issued Date: Feb. 02, 2006

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Doc No.:

Model No.: R181E2-L01

Approval

TFT LCD Approval Specification

MODEL NO.: R181E2-L01

(IDT ITSX98E)

Customer:

pproved by:

Note:



2007-02-02 21:00:32 CST

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Approve by Dept. Mgr.(QA RA)

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tomy_chen(ຫةԫ /52720/54140/43150)



Department Manager(QA RA)

Accept

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2007-02-02 17:08:26 CST

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Director Accept

Version 2.0

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Issued Date: Feb. 02, 2006

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Doc No.:

Model No.: R181E2-L01

Approval

REVISION HISTORY

Version Date Section Description

Ver 2.0 Feb. 02, 06’ All Index to IDT OEM I-98E-04

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Version 2.0

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Engineering Specification

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Engineering Specification

Type 18.1 SXGA Color TFT/LCD Module

Model Name: ITSX98E

Document Control Number: OEM I-98E-04

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Engineering Specification

i Contents

i Contents ii Record of Revision

1.0 Handling Precautions

2.0 General Description

2.1 Characteristics

2.2 Functional Block Diagram

3.0 Absolute Maximum Ratings

3.1 Component Temperature

4.0 Optical Characteristics

4.1 Luminance Uniformity

4.2 Image Retention

5.0 Signal Interface

5.1 Connectors

5.2 Interface Signal Connector

5.3 Interface Signal Description

5.4 Interface Signal Electrical Characteristics

5.5 Backlight Connector Signal Description

5.6 Backlight Input Signal Electrical Characteristics

6.0 Pixel format image

7.0 Interface Timings

7.1 Timing Characteristics

7.2 Timing Definition

8.0 Power Consumption

9.0 Power ON/OFF Sequence

10.0 Mechanical Characteristics

11.0 National Test Lab Requirement

12.0 Backlight Life

13.0 Packaging Specification

14.0 Label

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Engineering Specification

ii Record of Revision

Date Document Revision Page Summary

June 4,2001 OEM I-98E-01 All First Edition for customer.

September 28,2001 OEM I-98E-02 5,8 To update White Luminance

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Based on Internal Spec. as of May 11,2001.

October 19,2001

Feb. 2,2007 OEM I-98E-04

OEM I-98E-03

5

7

8

19

21

24,25

27,28

10

12

13

14

Updated by establishment of the New Company

as "International Display Technology".

Based on Internal Spec. EC H30912 as of

October 19,2001.

To update Weight, Optical Rise Time + Fall Time

and Power Consumption.

To update value of Shock Test Criteria.

To update Viewing Angle and Response Time.

To update Dimming Curve.

To add Note for Timing Characteristics.

To update Power Consumption.

To update Reference Drawings.

4.0 Optical Characteristics

Min Contrast spec add.

Optical equipment change.

4.2 Image Retention spec add.

5.1 Connectors

34

35,36

37,38

Feb. 2, 2007 OEM I-98E-04

Change IF connector type to RoHs.

Change Inverter connector type to RoHs.

12.0 Backlight Life spec add.

13.0 Packaging Specification add.

14.0 Label spec add.

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Engineering Specification

1.0 Handling Precautions

• Damage to the panel or the panel electronics may result from any deviation from the recommended

power on/off sequencing. The panel should not be hot plugged. Refer to the Power On/Off Sequence section in this Specification.

• Handle the panel with care. The LCD panel and CCFL (Cold Cathode Fluorescent Lamp)s are made of

glass and may crack or break if dropped or subjected to excessive force.

• The CCFLs contain a small amount of Mercury so should not be disposed of to landfill. Dispose of as

required by local ordinances or regulations.

• The LCD module contains small amounts of material having no flammability grade. The exemption

conditions of the flammability requirements (4.7.3.4, IEC60950 3rd.Ed. or UL60950 3rd.Ed.) should be applied.

• The panel may be damaged by the application of twisting or bending forces to the module

assembly.Care should be taken in the design of the monitor housing and the assembly procedure to prevent stress damage to the panel especially the lamp cable and the lamp connector..

• Use standard earthing/grounding procedures to prevent damage to the CMOS LSI while handling the

module.

• Use earthing/grounding procedures, an ionic shower, or similar to prevent static damage while

removing the protective front sheet.

• The front polarizer can be easily damaged. Take care not to scratch the front surface with any hard or

abrasive material. Dust, finger marks, grease etc. can be removed with a soft damp cloth (a small amount of mild detergent can be used on the damp cloth). Do not apply water or datergent directly to the front surface as this may cause staining or damage the electronic components.

• Never use any solvent on the front polarizer or module as this may cause permanent damage.

• Do not open or modify the module assembly.

• Continuous operation of the panel with the same screen content may result in some image sticking.

Over 10 hours operation with the same content is not recommended.

• Wipe off water drop immediately. Long contact with water may cause discoloration or spots.

• When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.

• Please do not use middle 3(three) screw holes on the upper(long) side and middle 3(three) screw holes

on the lower(long) side for panel fixing. These screw holes are for manufacturing purpose only.

 The information contained herein is presented only as a guide for the applications of our

products. No responsibility is assumed by International Display Technology for any infringements of patents or other right of the third partied which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of International Display Technology or others.

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Engineering Specification

2.0 General Description

This specification applies to the Type 18.1 Color TFT/LCD Module 'ITSX98E'. This module is designed for a LCD monitor style display unit.This module includes inverter card. The screen format and electrical interface are intended to support the VESA SXGA (1280(H) x 1024(V)at 60Hz) screen. Support color is native 16M colors(RGB 8-bit data driver). All input signals are LVDS(Low Voltage Differential Signaling) interface compatible. This model is meet RoHs requirements.

2.1 Characteristics

The following items are characteristics summary on the table under 25 degree C condition:

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CHARACTERISTICS ITEMS

Screen Diagonal [mm] 460

Pixels H x V 1280(x3) x 1024

Active Area [mm] 359.0(H) x 287.2(V)

Pixel Pitch [mm] 0.2805(per one triad) x 0.2805

Pixel Arrangement R,G,B Vertical Stripe

Weight [grams] 2,900 typ.

Physical Size [mm] 389.0(W) typ. x 317.2(H) typ. x 35.0 (D) max.

Display Mode Normally Black

Display Surface Treatment Anti-Glare

Support Color 16M (RGB 8-bit data)

White Luminance [cd/m2] 270 Typ

Contrast Ratio 400 : 1 Typ.

Optical Rise Time/Fall Time [msec] Rise Time + Fall Time : 40 Typ. (total)

Input Voltage [V] +12 +/- 5%

Power Consumption [W] 38.8 typ., 46.6 max.

SPECIFICATIONS

Electrical Interface

Temperature Range [degree C] Operating Storage (Shipping)

LVDS Dual (Even/Odd R/G/B Data(8bit), 3sync signals, Clock)

0 to +50

-20 to +60

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Engineering Specification

2.2 Functional Block Diagram

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The following diagram shows the functional block of this Type 18.1 Color TFT/LCD Module.

LCD module

Interface card

+12V

LVDS Signals

SELLVDS

Connector

HIROSE DF14-30P-1.25H(59)

Mating DF14-30S-1.25C

Connector JST S8B-PH-SM3

Mating JST PHR-8

Y-card

Gatearray

X-card

TFT/LCD

Array/Cell

1280x1024

Backlight unit

+12V VDIM

BLON

Inverter card

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y

Engineering Specification

3.0 Absolute Maximum Ratings

Absolute maximum ratings of the module is as follows:

Item

Logic/LCD Drive Voltage Vin -0.3 +13.2 V

Backlight Voltage VBL -0.3 +13.2 V

Select LVDS data order SELLVDS -0.3 3.3 V

Brightness control VDIM -0.3 5.3 V

Backlight on signal BLON -0.3 +5.3 V

Operating Temperature TOP 0 +50 deg.C

Operating Humidity HOP 8 80 %RH

Storage Temperature TST -20 +60 deg.C

Storage Humidity HST 5 95 %RH

Vibration 1.5 G Hz

Shock 50 11 G ms

Note 1: Maximum Wet-Bulb should be 39 degree C and No condensation. Note 2:

- Sign Vibration:10-200-10Hz, 1.5G, 30 min, X, Y, Z Axis, Each One Time. Shock Specification

- Half sine wave:50G 11msec. -X+/-, -Y+/-, -Z+/- (Total 6 directions), Each one time Shock.

3.1 Component Temperature

The table below shows the maximum component temperature to guarantee this specification.

Vibration Specification

S

mbol

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Min Max Unit Conditions

(Note 1)

(Note 2) (Note 2)

Half sine wave

Component Max. Temp. Spec (degree C)

Gate Array 95

X-Driver IC 85

Transformer(Inverter) 105

Inductor Coil (DC/DC) 100

Polarizer(Cell) 60

Note: If any cases of the operating condition, these components shall not exceed these temperature.

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Engineering Specification

4.0 Optical Characteristics

The optical characteristics are measured under stable conditions as follows under 25 degree C condition:

Item Conditions Specification

Typ. Note

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Viewing Angle (Degrees)

K:Contrast Ratio Horizontal (Right)

Vertical (Upper)

Contrast ratio 400 200

Response Time (ms) Rising (10%->90%)

Color Red x 0.640 +0.030

Chromaticity Red y 0.330 +0.030

(CIE) Green x 0.290 +0.030

Green y 0.600 +0.030

Blue x 0.150 +0.030

Blue y 0.060 +0.030

White x 0.313 +0.030

Horizontal (Right) K>

15 (Left)

Vertical (Upper) K>

15 (Lower)

K>

10 (Left)

K>

10 (Lower)

+

Falling (90%->10%)

85 85

-

40

-

85 Min. 85 Min.

-

White y 0.329 +0.030

Maximum White Luminance (cd/m2) VDIM=0V

Note:Measure center of the screen.

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270 230 Min.

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)

Engineering Specification

The following is the note for the Optical Characteristics:

Viewing or Measuring Direction

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Z

Viewing o r Measuring Direction

+h-v

LEFT

LOW ER

X

CENTER OF LCD

X=0,Y=0,Z=0

UPPER

RIGHT

Y

There is the Uniformity Measurement below: 'Lbright' represents the Luminance of the point that is brighter than the other point to be compared. 'Ldark' represents the Luminance of the point that is darker than the other point to be compared. Measuring points are shown in the following Fig. 9 circles are defined for 9 points.

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Engineering Specification

Chromaticity and White Balance are defined as the C.I.E. 1931 x,y coordinates at the center of LCD. The Standard Equipment are as shown below table.

Item Standard Equipment

Viewing Angle BM5A by Topcon Optical

Contrast USB 2000 Ocean Optics

Response Time 6030 Lecory

White Luminance USB 2000 Ocean Optics

Luminance Uniformity USB 2000 Ocean Optics

Chromaticity CS1000T by Konica Minolta

White Balance USB 2000 Ocean Optics

The measurement is to be done after 120 minutes of Power-on of BackLight. Unless otherwise specified, the ambient conditions are as following.

Ambient Temperature : 25 + 2 ( degreeC ) Ambient Humidity : 25 - 85 ( % ) Atmospheric Pressure : 86.0 - 104.0 ( kPa )

4.1 Luminance Uniformity

When the backlight is on with all pels in the selected state (white), the luminance uniformity is defined as follows;

Where:

L

: The luminance of the brightness part of the area

bright

: The luminance of the darkest part of the area

L

dark

1. Adjacent Area L

Luminance Uniformity = >

L

over a circular area of 10mm diameter placed anywhere on the screen.

2. Screen Total L

dark

bright

dark

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0.80

Luminance Uniformity = >

L

bright

0.60

over the entire screen.

3. Screen Total (9 points measurement)

L

Luminance Uniformity = >

L

dark

bright

0.80

over the entire screen.

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Engineering Specification

4.2 Image Retention

The panel spec of image retention is as follows.

Test method: The L0 IDT Log pattern on L255 background below is displayed for the display time

Then, change the pattern to L128 All gray pattern and count the time

until all IDT Log can’t read.

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Display Time 5sec 60sec

Time until disappearing

Definition of disappearing time: The time when the brightness will reach to 0.89% difference from background

level (L128).

| L logo − L128 |

x 100 <

 

L128

 

0.89%

5sec

15sec

1

2

1

2

1

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Engineering Specification

5.0 Signal Interface

5.1 Connectors

Physical interface is described as for the connector on module. These connectors are capable of accommodating the following signals and will be following components.

Connector Name / Designation Signal Connector

Manufacturer HIROSE

Type / Part Number DF14-30P-1.25H(56)

Mating Type / Part Number DF14-30S-1.25C

Contact / Part Number DF14-2628SCFA

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Connector Name / Designation For Backlight Connector on Inverter card

Manufacturer JST

Type / Part Number S8B-PH-SM3-TB(D)(LF) or

S8B-PH-SM4-TB(LF)(SN)

Mating Type / Part Number PHR-8

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Engineering Specification

5.2 Interface Signal Connector

Pin # Signal Name Pin # Signal Name

30 Vin(+12V) 29 Vin(+12V)

28 Vin(+12V) 27 VinRTN(GND)

26 VinRTN(GND) 25 VinRTN(GND)

24 SELLVDS 23 (RESERVED)

22 DGND 21 RxOIN3+

20 RxOIN3- 19 RxOCLKIN+

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18 RxOCLKIN- 17 RxOIN2+

16 RxOIN2- 15 RxOIN1+

14 RxOIN1- 13 RxOIN0+

12 RxOIN0- 11 RxEIN3+

10 RxEIN3- 9 RxECLKIN+

8 RxECLKIN- 7 RxEIN2+

6 RxEIN2- 5 RxEIN1+

4 RxEIN1- 3 RxEIN0+

2 RxEIN0- 1 LVDSGND

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Engineering Specification

5.3 Interface Signal Description

The module uses a pair of LVDS receiver SN75LVDS82(Texas Instruments) or compatible. LVDS is a differential signal technology for LCD interface and high speed data transfer device. Transmitter shall be SN75LVDS83(negative edge sampling) or compatible. The first LVDS port (RxExxx) transmits even pixels while the second LVDS port (RxOxxx) transmits odd pixels.

Please refer to the chart below for pin #1 of Signal Connector.

LCD Drive Connector No.1 Pin location

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Pin No.1

Module Back side view

Signal Connector

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Engineering Specification

PIN # SIGNAL NAME Description

30 Vin +12.0V Power Supply

29 Vin +12.0V Power Supply

28 Vin +12.0V Power Supply

27 VinRTN Ground for Vin line

26 VinRTN Ground for Vin line

25 VinRTN Ground for Vin line

24 SELLVDS Select LVDS data order. See the following figure.

23 (RESERVED) This pin should be left open.

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22 DGND Signal Ground

21 RxOIN3+ Positive LVDS differential data input (Odd data)

20 RxOIN3- Negative LVDS differential data input (Odd data)

19 RxOCLKIN+ Positive LVDS differential clock input (Odd Clock)

18 RxOCLKIN- Negative LVDS differential clock input (Odd Clock)

17 RxOIN2+ Positive LVDS differential data input (Odd data)

16 RxOIN2- Negative LVDS differential data input (Odd data)

15 RxOIN1+ Positive LVDS differential data input (Odd data)

14 RxOIN1- Negative LVDS differential data input (Odd data)

13 RxOIN0+ Positive LVDS differential data input (Odd data)

12 RxOIN0- Negative LVDS differential data input (Odd data)

11 RxEIN3+ Positive LVDS differential data input (Even data)

10 RxEIN3- Negative LVDS differential data input (Even data)

9 RxECLKIN+ Positive LVDS differential clock input (Even Clock)

8 RxECLKIN- Negative LVDS differential clock input (Even Clock)

7 RxEIN2+ Positive LVDS differential data input (Even data,H-Sync,V-Sync,DSPTMG)

6 RxEIN2- Negative LVDS differential data input (Even data,H-Sync,V-Sync,DSPTMG)

5 RxEIN1+ Positive LVDS differential data input (Even data)

4 RxEIN1- Negative LVDS differential data input (Even data)

3 RxEIN0+ Positive LVDS differential data input (Even data)

2 RxEIN0- Negative LVDS differential data input (Even data)

1 DGND Signal Ground

Note: Input signals of odd and even clock shall be the same timing.

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Engineering Specification

The interface card has a 100ohm resistor between positive and negative lines of each LVDS signal input on the internal circuit.

(SELLVDS=Low)

RxECLKIN+

RxECLKIN-

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1 cycle

RxEIN0+ RxEIN0-

RxEIN1+ RxEIN1-

RxEIN2+ RxEIN2-

RxEIN3+ RxEIN3-

RxOCLKIN+

RxOCLKIN-

RxOIN0+ RxOIN0-

RxOIN1+ RxOIN1-

ER1

EG2

EB3

ER7

OR1

OG2

ER0

EG1

EB2

ER6

OR0

OG1

EG0

EB1

DSP

NA

OG0

OB1

ER5

EB0

V-S

EB7

OR5

OB0

ER4

EG5

H-S

EB6

OR4

OG5

ER3

EG4

EB5

EG7

1 cycle

OR3

OG4

ER2

EG3

EB4

EG6

OR2

OG3

ER1

EG2

EB3

ER7

OR1

OG2

ER0

EG1

EB2

ER6

OR0

OG1

EG0

EB1

DSP

NA

OG0

OB1

RxOIN2+ RxOIN2-

RxOIN3+ RxOIN3-

OB3

OR7

OB2

OR6

NA

OB7

NA

OB6

OB5

OG7

OB4

OG6

OB3

OR7

OB2

OR6

Note: R/G/B data 7:MSB, R/G/B data 0:LSB

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Engineering Specification

(SELLVDS=High)

RxECLKIN+

RxECLKIN-

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1 cycle

RxEIN0+ RxEIN0-

RxEIN1+ RxEIN1-

RxEIN2+ RxEIN2-

RxEIN3+ RxEIN3-

RxOCLKIN+

RxOCLKIN-

RxOIN0+ RxOIN0-

RxOIN1+ RxOIN1-

ER3

EG4

EB5

ER1

OR3

OG4

ER2

EG3

EB4

ER0

OR2

OG3

EG2

EB3

DSP

NA

OG2

OB3

ER7

EB2

V-S

EB1

OR7

OB2

ER6

EG7

H-S

EB0

OR6

OG7

ER5

EG6

EB7

EG1

1 cycle

OR5

OG6

ER4

EG5

EB6

EG0

OR4

OG5

ER3

EG4

EB5

ER1

OR3

OG4

ER2

EG3

EB4

ER0

OR2

OG3

EG2

EB3

DSP

NA

OG2

OB3

RxOIN2+ RxOIN2-

RxOIN3+ RxOIN3-

OB5

OR1

OB4

OR0

NA

OB1

NA

OB0

OB7

OG1

OB6

OG0

OB5

OR1

OB4

OR0

Note: R/G/B data 7:MSB, R/G/B data 0:LSB

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Engineering Specification

The following is LVDS Signal description.

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LVDS DATA NAME Description

DSP

V-S

H-S

TI LVDS X'mitter (SN75LVDS83) Signal name

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27

Note: SELLVDS: Pin#7 of Signal connector

Display Timing

Vertical Sync

Horizontal Sync

ITSX98E LVDS Signal (SELLVDS=Low)

Red0 Red1 Red2 Red3 Red4 Red7 Red5 Green0 Green1 Green2 Green6 Green7 Green3 Green4 Green5 Blue0 Blue6 Blue7 Blue1 Blue2 Blue3 Blue4 Blue5 NA H Sync V Sync Disp Timing Red6

When the signal is high, the pixel data shall be valid to be

displayed.

Both Positive and negative polarity are acceptable.

ITSX98E LVDS Signal (SELLVDS=High)

Red2 Red3 Red4 Red5 Red6 Red1 Red7 Green2 Green3 Green4 Green0 Green1 Green5 Green6 Green7 Blue2 Blue0 Blue1 Blue3 Blue4 Blue5 Blue6 Blue7 NA H Sync V Sync Disp Timing Red0

Red0: LSB, Red7: MSB

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Engineering Specification

5.4 Interface Signal Electrical Characteristics

Input signals shall be low or Hi-Z state when Vin is off. It is recommended to refer the specifications of SN75LVDS82DGG(Texas Instruments) in detail.

Signal electrical characteristics are as follows;

Parameter Condition Min Max unit

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Vth

Vtl

LVDS Timing

Differential Input High Voltage (Vcm=+1.2V)

100 mV

-100 mV

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Engineering Specification

LVDS Macro AC characteristics.

Parameter Symbol Min Typ Max Unit

LVDS Clock Cycle Trxc 17.6 18.5 20 [ns]

LVDS Data Cycle Trxd Trxc/7 [ns]

Sample Data Setup Time

(Trxc=Typ.)

Sample Data Hold Time

(Trxc=Typ.)

Data Sample Time Trxs Trxc/14 [ns]

Data Sample Cycle Trxsc Trxc/7 [ns]

Name Description Min Typ Max Unit Note

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Trxss 600 [ps]

Trxsh 600 [ps]

SELLVDS High voltage 2 3 3.3 V

Low voltage -0.1 0 0.7 V

Current -1 - 1 mA

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Engineering Specification

5.5 Backlight Connector Signal Description

PIN # SIGNAL NAME Description

1 VBL +12.0V Power Supply for backlight

2 VBL +12.0V Power Supply for backlight

3 VBL +12.0V Power Supply for backlihgt

4 RTN Ground for VBL line, VDIM and BLON

5 RTN Ground for VBL line, VDIM and BLON

6 RTN Ground for VBL line, VDIM and BLON

7 VDIM Brightness control voltage input(0-4V), (0V:brightness MAX, 4V:brightness MIN)

8 BLON backlihgt on/off signal(Hi:backlight ON, Low:backlight OFF) TTL level

5.6 Backlight Input Signal Electrical Characteristics

Name Description Min Typ Max Unit Note

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BLON High voltage 2.0 5.0 5.25 V

Low voltage -0.1 0 0.8 V

Current -1.0 - 1.0 mA

VDIM Input Voltage Range 0 - 4.0 V

Current -1.0 - 1.0 mA

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0V:Brightness Max. 4V:Brightness Min.

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The following chart is the Dimming Signal (VDIM) versus Luminance curve for your reference.

ITSX98E Dimming Curve (VDIM vs Lumi.)

120.0%

100.0%

80.0%

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60.0%

Luminance(%)

40.0%

20.0%

0.0% 0 0.5 1 1.5 2 2.5 3 3.5 4

Lumi(%)

VDIM(V)

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6.0 Pixel format image

Following figure shows the relationship of the input signals and LCD pixel format image. Odd and even pair of RGB data are sampled at a time.

Even Odd Even Odd

1st Line

0 1 1279

RGB RGB

1278

R

B R

G

B

G

1024th Line

RGB RGB

R

B R

G

B

G

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p

f

(*1)

p

(*1)

p

f

Engineering Specification

7.0 Interface Timings

Basically, interface timings described here is not actual input timing of LCD module but output timing of SN75LVDS82DGG(Texas Instruments) or equivalent.

7.1 Timing Characteristics

Item Symbol MIN. TYP. MAX. Unit

Signal

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DTCLK Freq. Fdck

DTCLK Cycle Tck 17.6 18.5

+V-Sync Frame Rate

+V-Sync Cycle Tv 16.39 16.66 17.78 ms

+V-Sync Cycle Tv 1035 1066

+V-Sync active level Tva 3 3

+V-Sync V-back

+V-Sync V-front

+DSPTMG V-Line m - 1024

+H-Sync Scan Rate 1/Th

+H-Sync Cycle Th 844 844

+H-Sync active level

+H-Sync Back

+H-Sync Front

+DSPTMG Display Pixels n - 640

Note 1: Typical value is refer to VESA STANDARD.

Note 2: When there are invalid timing, Display appears black pattern.

Synchronous Signal Defects and enter Auto Refresh for LCD Module Protection Mode.

(*1): Tha+Thb should be less than 1024 Tck.

orch Tvb 7 38 63 lines

orch Tv

orch

orch Th

11/Tv

Tha

Thb

50

56.25 60.02 61 Hz

11

-

456

4 124

424

54 56.8 MHz

63.98

20

2047

-

1023

-

ns

lines

KHz

Tck

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(

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7.2 Timing Definition

Vertical Timing

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DSPTMG

-VSYNC

+VSYNC

Support mode T1 Vertical

1280 x 1024 at 60Hz (VESA STANDARD) (H line rate: 15.6 us)

Horizontal Timing

DSPTMG

-HSYNC

T3 T5 T6

T1 T2

T2

Blanking

0.656 ms (42 lines)

T9 T11 T12

Active Field

16.005 ms (1024 lines)

T7 T8

T4

T3 VSYNC Front Porch

0.016 ms (1 line)

T10

T4 Frame Time

16.661 ms (1066 lines)

T5 VSYNC Width

0.047 ms (3 lines)

T6 VSYNC Back Porch

0.594 ms (38 lines)

+HSYNC

Support mode T7

1280 x 1024 (VESA STANDARD)

Horizontal

3.778 us (408 dots)

T8 Active Field

11.852 us (1280 dots)

T9 HSYNC

0.444 us (48 dots)

T10 H line Time

15.630 us (1688 dots)

T11 HSYNC

1.037 us (112 dots)

T12 HSYNC

2.296 us (248 dots)

Dotclock: 108.000

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Interface Timing Definition

Tva

V-Sync

H-Sync

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Tv

DSPTMG

H-Sync

Dot clock

DSPTMG

Video(Even)

Video(Odd)

Tck

Tha

Tvb Tvf

01 m-1

Vsync, Hsync and Display Timing

Th

Thd

Thb Thf

0

1

2

3

Video signal, Hsync and Dot clock

n-2

n-1

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8.0 Power Consumption

Input power specifications are as follows;

SYMBOL PARAMETER Min Typ Max UNITS CONDITION

Vin Logic/LCD Drive

Voltage

Iin Vin Current

Pin(1) Vin Power

Pin(2)

Logic/LCD

DC current Waveform

Vin rp Allowable

Logic/LCD Drive Ripple Voltage

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11.4 12 12.6 V

550 mA

4.5 W

5.2 6.3 W

Refer to the Typical Logic/LCDCurrent Waveform shown in the following Figure. Waveform may vary in paticular application. Actual current waveform on user application must be evaluated and make sure the ripple current and/or peak current should be allowable to user power supply.

500 mVp-p

Maximum Load Condition

Vin=11.4V (All White Pattern) (This value indicates long term average.) Typical Load Condition (Vertical Gray Bar, 256 Scale) Maximum Load Condition (All White)

(All White)

VBL Backlight power

voltage

PBL Backlight Power

consumption

Note: A used DC power supply for this LCD module should be have a over current protection function to safety.

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11.4 12 12.6 V

33.6 40.3 W

Brightness=max

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Figure. Typical Logic/LCD Current Waveform

Condition: Maximum Load Condition(All White) Voltage: 12.0V measured at Interface Connector J1 Interface Cable: AWG28, 30 Conductors, L=500mm from Voltage Source to EUT

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9.0 Power ON/OFF Sequence

Vin and VBL power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from any system shall be Hi-Z state or low level when Vin and VBL are off. It is recommended that the BLON should be supplied after other signals are stable in order to avoid visible screen noise when power-on.

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Vin

0 V

Signals

0 V

VBL

0 V

BLON

0 V

10%

90%

30ms max. and 1ms min.

0 min. 0 min.

10%

90%

30ms max. and 1ms min.

5ms min. 0 min.

1.9V

0.9V

1uS max.

90%

10% 10%

10ms min.

10%

100ms min.

90%

10% 10%

1.9V

0.9V

1uS max.

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10.0 Mechanical Characteristics

Note: Please do not use middle 3(three) screw holes on the upper(long) side and middle 3(three) screw holes

on the lower(long) side for panel fixing. These screw holes are for manufacturing purpose only.

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11.0 National Test Lab Requirement

The display module is authorized to Apply the UL Recognized Mark.

Conditions of Acceptability

Conditions of Acceptability - When installed on the end-product, consideration shall be given to the following;

1. This component has been judged on the basis of the required spacings in the Standard for Safety of Information Technology Equipment, CAN/CSA C22.2 No. 60950-00 *UL60950, Third Edition, which are based on the IEC 60950, Third Edition, which would cover the component itself if submitted for Listing.

2. The inverter output circuits are Limited Current Circuits.

3. The units are intended to be supplied by SELV.

4. The terminals and connectors are suitable for factory wiring only.

5. A suitable Electrical enclosure shall be provided.

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12.0 Backlight Life

Backlight Life Time 50,000 Hours (Typ) condition 25 degree C

30,000 Hours (Min)

The assumed Backlight Life will be until the luminance becomes 105 cd/m luminance.

2

or more at maximum white

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13.0 Packaging Requirement

The packaging of the LCD meets 75 cm drop test. The following is the drawing of the package.

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14.0 Label

There are labels on the rear side of the Module.

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Serial Number Label

BARCODE CHARACTER AREA

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Date Label

YY and WW of the Week Code stand for the Year and the Week of the Year of manufacturing of the Module respectively.

UL Label

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****** End Of Page ******

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IDTech ITSX98E, R181E2-L01 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual