IDTech ITSX95E Specification

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Engineering Specification

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Engineering Specification

Type 15.0 SXGA+ Color TFT/LCD Module

Model Name:ITSX95E

Document Control Number : OEM I-95E-04

Note:Specification is subject to change without notice. Consequently it is better to contact to

International Display Technology before proceeding with the design

of your product incorporating this module.

Product Development

International Display Technology

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Engineering Specification

i Contents

i Contents
ii Record of Revision

1.0 Handling Precautions

2.0 General Description

2.1 Characteristics

2.2 Functional Block Diagram

3.0 Absolute Maximum Ratings

4.0 Optical Characteristics

5.0 Signal Interface

5.1 Connectors

5.2 Interface Signal Connector

5.3 Interface Signal Description

5.4 Interface Signal Electrical Characteristics

5.4.1 Signal Electrical Characteristics for LVDS Receiver

5.4.2 LVDS Receiver Internal Circuit

5.5 Inverter Signal connector

5.6 Inverter Signal Description

5.7 Inverter Signal Electrical Characteristics

6.0 Pixel format image

7.0 Interface Timings

7.1 Timing Characteristics

7.2 Timing Definition

8.0 Power Consumption

9.0 Power ON/OFF Sequence

10.0 Mechanical Characteristics

11.0 National Test Lab Requirement

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Engineering Specification

ii Record of Revision

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Date

Revision

OEM95E-02August 4,2000

OEM95E-03October 10,2000

OEM95E-04April 24,2001

AllOEM95E-01March 27,2000

6

12
14
16,17

18
21
23
24
25,26
27

7
8
9
11
12,13
14,15,16,17,18
26
28,29

1,5,6,7
6
28,29

SummaryPageDocument

First Edition for customer.
Based on Internal Specification EC F78950 as of March
10,2000.
Based on Internal Specification EC F78951 as of July
12,2000.
To update Nominal Input Voltage, Logic Power
Consumption, Weight and Physical Size.
To add Note for Even/Odd.
To update LVDS Macro AC characteristics.
To update by customer required subject for Inverter
signal.
To update Lamp Frequency.
To update Timing Characteristics.
To update Power Consumption.
To update Power ON/OFF Sequence.
To update Reference Drawing as of June 5,2000.
To add National Test Lab Requirement.
Based on Internal Specification EC F78952 as of
September 6,2000.
To update Functional Block Diagram.
To update Absolute Maximum (VDD).
To update Optical Characteristics.
To update Interface Signal Connector and add Note.
To update Interface Signal Description.
To update Interface Signal Electrical Characteristics.
To update Power Consumption.
To update Reference Drawing as of September 5,2000.
Based on Internal Specification EC H30700 as of January
31,2001.
To avoid using "inch" indication.
To update Weight.
To update Reference Drawings.

OEM I-95E-04Januray 15,2002

(C) Copyright International Display Technology 2002 All Rights reserved.

January 15,2002 OEM I-95E-04 3/30

Updated by establishment of the New Company as
"International Display Technology".

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Engineering Specification

1.0 Handling Precautions

1) Since front polarizer is easily damaged, pay attention not to scratch it.

2) Be sure to turn off power supply when inserting or disconnecting from input connector.

3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots.

4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.

5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface.

6) Since CMOS LSI is used in this module, take care of static electricity and insure human earth
when handling.

7) Do not open nor modify the Module Assembly.

8) Do not press the reflector sheet at the back of the module to any directions.

9) In case if a Module has to be put back into the packing container slot after once it was taken out
from the container, do not press the center of the CFL Reflector edge.
Instead, press at the far ends of the CFL Reflector edge softly. Otherwise the TFT Module may
be damaged.

10) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the
Interface Connector of the TFT Module.

11) After installation of the TFT Module into an enclosure ( Notebook PC Bezel, for example),
do not twist nor bent the TFT Module even momentary. At designing the
enclosure, it should be taken into consideration that no bending/twisting forces are applied
to the TFT Module from outside. Otherwise the TFT Module may be damaged.

12) The fluorescent lamp in the liquid crystal display (LCD) contains mercury. Do not put it in trash that is
disposed of in landfills. Dispose of it as required by local ordinances or regulations.

13) Small amount of materials having no flammability grade is used in the LCD module.
The LCD module should be supplied by power complied with requirements of
Limited Power Source (2.11, IEC60950 or UL1950), or be applied exemption
conditions of flammability requirements (4.4.3.3, IEC60950 or UL1950) in an end product.

O

The information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by International Display Technology for any
infringements of patents or other right of the third partied which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of International
Display Technology or others.

O

The information contained herein may be changed without prior notice. It is therefore
advisable to contact International Display Technology before proceeding with the design of
equipment incorporating this product.

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Engineering Specification

2.0 General Description

This specification applies to the Type 15.0 Color TFT/LCD Module 'ITSX95E'.

This module is designed for a display unit of notebook style personal computer.

The screen format and electrical interface are intended to support the SXGA+ (1400(H) x 1050(V))screen.

Support color is native 262k colors ( RGB 6-bit data driver ).

All input signals are LVDS interface compatible.This module contains an inverter card for backlight.

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Engineering Specification

2.1 Characteristics

The following items are characteristics summary on the table under 25 degree C condition:

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SPECIFICATIONSITEMS

381 Screen Diagonal [mm]

304.5(H) x 228.375(V)Active Area [mm]

1400(x3) x 1050Pixels H x V

0.2175(per one triad) x 0.2175Pixel Pitch [mm]

R.G.B. Vertical StripePixel Arrangement

Normally WhiteDisplay Mode

2

Typical White Luminance [cd/m

]

SMData=00H:

Nominal Input Voltage [Volt]
VDD
5VSUS,5VALW line
PWR_SCR line

Backlight Power Consumption [watt]
PWR_SCR line
SMData=00H

Electrical Interface (Logic)

150 Typ.(Center) 140 Typ.(5 Points average)

200 : 1 Typ.Contrast Ratio

30Typ. 50Max.(each) Optical Rise Time/Fall Time [msec]

+3.3 Typ.
+5.0 Typ.
+14.4 Typ.

1.8 Typ.Logic Power Consumption [watt]

5.2 Typ.

625( Typ.) 660(Max.)Weight [grams]

317.3(W) x 242.0(H) x 10.5(D) Typ. 10.8(D)Max.Physical Size [mm]

6-bit digital video for each color R/G/B, 3 sync, Clock
(8 pairs LVDS)

Panel IDs,SMB_CLK,SMB_DAT,FPVEEElectrical Interface (Inverter)

Native 262K colors ( RGB 6-bit data driver )Support Color

Temperature Range (degree C)
Operating
Storage (Shipping)

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0 to +50

-20 to +60

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Engineering Specification

2.2 Functional Block Diagram

The following diagram shows the functional block of the 38.1cm(15.0") Color TFT/LCD Module.

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X-Driver

Y-Driver

< 8 pairs LVDS >

6bit color data
for R/G/B

(even/odd)

DTCLK(even/odd)
DSPTMG
Vsync
Hsync

EEDID

V

EEDID

CLK

EEDID

Data

VDD

GND

LCD-DRIVE Connector

F

A

J

E

r

e

v

n

I

M

O

L

E

Panel IDsp
SMB_CLK
SMB_DAT
FPVEE
PWR_SRC
5VSUS
5VALW
GND

LCD DRIVE

CARD

EVEN

PIXCEL

ODD
PIXCEL

Dual LVDS
RECEIVER

LCD

Controller

TFT ARRAY/CELL

1400(R/G/B) x 1050

G/A

F

t

1

o

6

0

r

0

9

DC-DC

Converter
Ref circuit

p

0

3

(

i

p

6

1

(

Backlight Unit

n

)

)

n

i

EEPROM

X

-

I

e

t

X

H

B

S

0

-

3

r

c

C

e

n

n

o

5

2

2

1

-

7

0

INVERTER

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Engineering Specification

3.0 Absolute Maximum Ratings

Absolute maximum ratings of the module is as follows :

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Conditions Unit Max MinSymbol Item

V+4.0-0.3VDDSupply Voltage

V+5.5-0.35VSUS,

5VALW

V+25-0.3PWR_SRC

V+VDD+0.3-0.3VinInput Voltage of Signal

V+5.5-0.3FPVEE

V+7-1SMB_CLK

SMB_DAT

Operating Temperature

Operating Humidity

Note 1 : Maximum Wet-Bulb should be 39 degree C and No condensation.

Note 1deg.C+500TOP

Note 1%RH958HOP

Note 1deg.C+60-20TSTStorage Temperature

Note 1%RH955HSTStorage Humidity

G Hz1.5 10-200Vibration

G ms50 18Shock

Rectangle
wave

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Engineering Specification

4.0 Optical Characteristics

The optical characteristics are measured under stable conditions as follows under 25 degree C condition:

Viewing Angle
(Degrees)

White Luminance

2

) SMData=00H

(cd/m

Horizontal (Right)
K210 (Left)

Vertical (Upper)
K210 (Lower)K:Contrast Ratio

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SpecifiationConditionsItem

40
40

15
30

150

Center

140
5 Points
Average

NoteTyp.

-

-

-

-

-200Contrast ratio

50(Max)30RisingResponse Time

50(Max)30Falling(ms)

-0.569Red xColor

-0.332Red yChromaticity

-0.312Green x(CIE)

-0.544Green y

-0.149Blue x

-0.132Blue y

- 0.313 White x

- 0.329 White y

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Engineering Specification

5.0 Signal Interface

5.1 Connectors

Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following components.

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Connector Name / Designation

Manufacturer

Type / Part Number

Mating Type / Part Number

For Signal Connector

JAE

FI-XB30S-HF10

FI-X30M

For Inverter ConnectorConnector Name / Designation

MolexManufacturer

52207-1690Type / Part Number

(FPC)Mating Type / Part Number

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)

)

)

(

)

)

(

)

Signa

e

#

Signa

#

Engineering Specification

5.2 Interface Signal Connector

l Name Pin

1

GND

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Pin

l Nam

GND17FG

ReCLKIN-18GND2

ReCLKIN+19VDD3

GND20VDD4

5

6

7

8

(Note 2,3

Reserved, Note 1

(Note 2,4

(Note 2,4

RoIN0-21V

RoIN0+22NC

GND23CLK

RoIN1-24Data

RoIN1+25ReIN0-9

GND26ReIN0+10

RoIN2-27GND11

RoIN2+28ReIN1-12

GND29ReIN1+13

RoCLKIN-30GND14

RoCLKIN+31ReIN2-15

32ReIN2+16

FG (GND

Note:

1. 'Reserved' pins are not allowed to connect any other line.

2. This LCD Module complies with "VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA

STANDARD Release A, Revision 1" and supports "EEDID version 1.3".
This module uses Serial EEPROM BR24C02FV (ROHM) or compatible as a EEDID function.

3. V

4. Both CLK

power source shall be the current limited circuit which has not exceeding 1A. (Reference Document :

EEDID

"Enhanced Display Data Channel (E-DDC

line and Data

EEDID

line are pulled-up with 10K ohm resistor to V

EEDID

TM

) Proposed Standard", VESA)

power source line at LCD

EEDID

panel, respectively.

Voltage levels of all input signals are LVDS compatible (except VDD,EEDID). Refer to "Signal Electrical
Characteristics for LVDS(*)", for voltage levels of all input signals.

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5.3 Interface Signal Description

The module uses a pair of LVDS receiver SN75LVDS86(Texas Instruments) compatible. LVDS is a differential
signal technology for LCD interface and high speed data transfer device. Transmitter shall be
SN75LVDS84(negative edge sampling) or compatible.

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PIN
#

5

7
8

NAME

EEDID

EEDID

EEDID

Description SIGNAL

Frame Ground FG1
Ground GND2
+3.3V Power SupplyVDD3
+3.3V Power SupplyVDD4
EEDID 3.3V Power SupplyV
Reserved Reserved6
EEDID ClockCLK
EEDID DataData
Negative LVDS differential data input (Even R0-R5, G0)ReIN0-9
Positive LVDS differential data input (Even R0-R5, G0)ReIN0+10
Ground GND11
Negative LVDS differential data input (Even G1-G5, B0-B1)ReIN1-12
Positive LVDS differential data input (Even G1-G5, B0-B1)ReIN1+13
Ground GND14
Negative LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)ReIN2-15
Positive LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)ReIN2+16
GroundGND17
Negative LVDS differential clock input (Even)ReCLKIN-18
Positive LVDS differential clock input (Even)ReCLKIN+19
GroundGND20
Negative LVDS differential data input (Odd R0-R5, G0)RoIN0-21
Positive LVDS differential data input (Odd R0-R5, G0)RoIN0+22
Ground GND23
Negative LVDS differential data input (Odd G1-G5, B0-B1)RoIN1-24
Positive LVDS differential data input (Odd G1-G5, B0-B1)RoIN1+25
GroundGND26
Negative LVDS differential data input (Odd B2-B5)RoIN2-27
Positive LVDS differential data input (Odd B2-B5)RoIN2+28
GroundGND29
Negative LVDS differential clock input (Odd)RoCLKIN-30
Positive LVDS differential clock input (Odd)RoCLKIN+31
Frame GroundFG32

Note:

Input signals of odd and even clock shall be the same timing.

1.

2. The module uses a 100ohm resistor between positive and negative data lines of each receiver input.

3. Even : First Pixel Data, Odd : Second Pixel Data

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Engineering Specification

DescriptionSIGNAL NAME

RED Data 5 (MSB)+RED 5 (ER5/OR5)
RED Data 4+RED 4 (ER4/OR4)
RED Data 3+RED 3 (ER3/OR3)
RED Data 2+RED 2 (ER2/OR2)
RED Data 1+RED 1 (ER1/OR1)
RED Data 0 (LSB)+RED 0 (ER0/OR0)

(EVEN/ODD)

Red-pixel Data: Each red pixel's brightness data consists of these 6 bits pixel data.
GREEN Data 5 (MSB)+GREEN 5 (EG5/OG5)
GREEN Data 4+GREEN 4 (EG4/OG4)
GREEN Data 3+GREEN 3 (EG3/OG3)
GREEN Data 2+GREEN 2 (EG2/OG2)
GREEN Data 1+GREEN 1 (EG1/OG1)
GREEN Data 0 (LSB)+GREEN 0 (EG0/OG0)

(EVEN/ODD)

Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel
data.

BLUE Data 5 (MSB)+BLUE 5 (EB5/OB5)
BLUE Data 4+BLUE 4 (EB4/OB4)
BLUE Data 3+BLUE 3 (EB3/OB3)
BLUE Data 2+BLUE 2 (EB2/OB2)
BLUE Data 1+BLUE 1 (EB1/OB1)
BLUE Data 0 (LSB)+BLUE 0 (EB0/OB0)

(EVEN/ODD)

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(EVEN/ODD)

VSYNC (V-S)

HSYNC (H-S)

EEDID

EEDID

EEDID

Note : Output signals except V

Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel
data.
Data Clock: The typical frequency is 54MHz.DTCLK

The signal is used to strobe the pixel +data and the +DSPTMG

When the signal is high, the pixel data shall be valid to be displayed.+DSPTMG (DSP)
Vertical Sync: This signal is synchronized with DTCLK. Both active high/low signals
are acceptable.
Horizontal Sync: This signal is synchronized with DTCLK. Both active high/low
signals are acceptable.
Power SupplyVDD
Ground GND
EEDID Power SupplyV
EEDID ClockCLK
EEDID dataData

EEDID

,CLK

EEDID

and Data

from any system shall be Hi-Z state when VDD is off.

EEDID

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5.4 Interface Signal Electrical Characteristics

5.4.1 Signal Electrical Characteristics for LVDS Receiver

Table . Electrical Characteristics

Note:

O Input signals shall be low or Hi-Z state when VDD is off.

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VcmCommon Mode Voltage

0.825
+|Vid|/2

ConditionsUnit MaxTypMinSymbolParameter

mV +100 VthDifferential Input High Threshold
mV -100VtlDifferential Input Low Threshold
mV600100|Vid|Magnitude Differential Input Voltage
V2.4

-|Vid|/2
mV+50-50VcmCommon Mode Voltage Offset

Figure. Voltage Definitions

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Table . Switching Characteristics

Note: This specification defines maximum average cycle modulation rate in peak-to-peak transition within any
100 clock cycles. This specification is applied only if input clock peak jitter within any 100 clock cycles is
greater than 300ps.

Figure . Timing Definition (Even)

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ConditionsUnitMaxTypMinSymbolParameter

MHz575451fcClock Frequency

ns19.618.517.5tcCycle Time

fc = 54MHz, jitter < 50psps700TsuData Setup Time

ps700ThdData Hold Time

ps/clk20tCJavgCycle modulation rate(Note)

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Engineering Specification

Figure. Timing Definition (Odd)

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Figure . Timing Definition(detail A)

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Engineering Specification

5.4.2 LVDS Receiver Internal Circuit

Below figure shows the internal block diagram of the LVDS receiver.

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5.5 Inverter Signal connector

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Signal NamePin # Signal NamePin #

1 (Note*)

(Note*) Molex Connector No.1 Mark

5VALW9PANEL-ID0

5VSUS10PANEL-ID12

GND11PANEL-ID23

GND12PANEL-ID34

GND13NC5

PWR_SRC14FPVEE6

PWR_SRC15SMB_CLK7

PWR_SRC16SMB_DAT8

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Engineering Specification

5.6 Inverter Signal Description

Input connector

Molex

1*

52207-1690

( FFC/FPC)

FunctionPin

PANEL_ID0

NC5

GND11
GND12
GND13

PWR_SRC14

PWR_SRC15

PWR_SRC16

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Voltage

levels

(0,3.3V)typFPVEE6

(0V,5V)typSMB_CLK7

(0V,5V)typSMB_DAT8

5V typ5VALW9

4.85V to 5.2V5VSUS10

(9V to 21V)

typ

(9V to 21V)

typ

(9V to 21V)

typ

Control signal input into the inverter to turn the

This should be used as power source that stores

the brightness/contrast values & the circuit that

This should be used as power source for the

This power rail should be used as a power rail to

This power rail should be used as a power rail to

This power rail should be used as a power rail to

DescriptionTypical(typ)

"0" Connect to GND

"1" OpenPANEL_ID12
"1" OpenPANEL_ID23

"0" Connect to GNDPANEL_ID34

backlight ON & OFF (3.3V-ON,0V-OFF)

SMBus interface for sending brightness &

contrast information to the inverter/panel

SMBus interface for sending brightness &

contrast information to the inverter/panel

interfaces with SMB_CLK & SMB_DAT

control circuitry on the inverter.

drive the backlight DC-AC converter

drive the backlight DC-AC converter

drive the backlight DC-AC converter

Note (*) : Molex Connector No.1 Mark

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Engineering Specification

5.7 Inverter Signal Electrical Characteristics

5VALW

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CONDITIONUNITSMax.Typ.Min.SymbolItem

(Ta=25 degree C) V2114.49.0PWR_SRCInput Voltage

V5.25.04.855VSUS,

W5.85.2P(PWR_SRC)Input Power

mW5P(5VSUS)

mw5P(5VALW)

KHz6840FLamp Frequency

SMData=00H,
PWR_SRC=14.4V

ONV2.0FPVEEON/OFF

OFFV0.8FPVEE

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Engineering Specification

6.0 Pixel format image

Following figure shows the relationship of the input signals and LCD pixel format image.

Even Odd Even Odd

0 1 1399

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1398

1st Line

1050th Line

R

R

B R

G

B R

G

B

G

B

G

R

R

B R

G

B R

G

B

G

B

G

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The following chart is the Luminance versus the Lamp current for your reference.(Center)

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FFH

(

)

(00H)

(SMBUS Data)

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Engineering Specification

7.0 Interface Timings

7.1 Timing Characteristics

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UnitMAX.TYP.MIN.SymbolItemSignal

[MHz]575451FdckFreqencyDTCLK

[ns]18.5Tck

[Hz]60FvFrame Rate+V-Sync

[ms]16.67Tv

[lines]2046 10661058Nv

[us]46.715.78TvaV-Active Level

Note:Both positive Hsync and positive Vsync polarity is recommended.

[lines]62 31 Nva

[lines]125 126 NvbV-Back Porch

[lines]11 NvfV-Front Porch

[lines]1050mV-Line+DSPTMG

[KHz]63.98FhScan Rate+H-Sync

[usec]15.63Th

[Tck]1023 844762 Nh

[usec]1.037ThaH-Active Level

[Tck]250 568 Tha

[Tck]300 6426ThbH-Back Porch

[Tck]248 ThfH-Front Porch

[usec]12.96ThdDisplay+DSPTMG

[dots]1400nData Even/Odd+DATA

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Engineering Specification

Typical Vertical Timing Table

Support mode

Tvblk
Vertical
Blanking

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m
Active Field

Tvf VSYNC
Front Porch

Tv,Nv
Frame
Time

Tva
VSYNC
Width

Tvb
VSYNC
Back Porch

1400 x 1050 at 60Hz
(H line rate : 15.63 us)

0.250 ms
(16 lines)

Typical Horizontal Timing Table

Support mode

Thblk
Horizontal
Blanking

1400 x 1050
Dotclock : 108.000
MHz (54.000MHz x2)

2.667 us
(288 dots)

7.2 Timing Definition

DSPTMG

-VSYNC

+VSYNC

Tvf

Tvblk

Tva

16.411 ms
(1050 lines)

Thd
Active Field

12.963 us
(1400 dots)

Tvb

0.016 ms
(1 line)

Thf
HSYNC
Front Porch

0.444 us
(48 dots)

Tv

16.661 ms
(1066 lines)

Th,Nh
H Line
Time

15.630 us
(1688 dots)

m

0.047 ms
(3 lines)

Tha
HSYNC
Width

1.037 us
(112 dots)

0.188 ms
(12 lines)

Thb
HSYNC
Back Porch

1.185 us
(128 dots)

DSPTMG

Th

Thf

Thblk Thd

Tha

Thb

-HSYNC

+HSYNC

Tck

VIDEO(Even)

VIDEO(Even)

VIDEO(Odd)

VIDEO(Odd)

0

1

4

2

5

3

n-4 n-2

n-3

n-1

DTCLK

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Engineering Specification

8.0 Power Consumption

Input power specifications are as follows;

VDD

Voltage

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CONDITIONUNITSMaxTypMinPARAMETERSYMBOL

Load Capacitance 40uF[V]3.63.33.0Logic/LCD Drive

VDDrp

Drive Ripple Voltage

VDDns

Drive Ripple Noise

MAX. Pattern : 2dot Vertical sub-pixel Stripe

[W]3.2VDD PowerPDD

[W]1.8VDD PowerPDD

[mA]890VDD CurrentIDD

[mA]545VDD CurrentIDD

[mVp-p]100Allowable Logic/LCD

[mVp-p]100Allowable Logic/LCD

MAX. Pattern,
VDD=3.6[V]

All Black Pattern,
VDD=3.3[V]

MAX Pattern,
VDD=3.6[V]

All Black Pattern,
VDD=3.3[V]

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Engineering Specification

9.0 Power ON/OFF Sequence

VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from
any system shall be Hi-Z state or low level when VDD is off.

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150ms min.

VDD

10%

0 V

Signals

0 V

1ms min.

30ms max.

PWR_SRC

0 V

10%

5VALW/5VSUS

0 V

90%

90%

10ms max.

0 min.

90% 90%

10% 10%

100ms min.

20ms min.

180ms min.

0ms min.

90%

0ms min.

90%90%

10%

90%

10ms min.

0ms min.

0ms min.

10% 10%

0 min.

FPVEE

10%10%

0 V

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Engineering Specification

10.0 Mechanical Characteristics

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Engineering Specification

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Engineering Specification

11.0 National Test Lab Requirement

The display module is authorized to Apply the UL Recognized Mark.

Conditions of Acceptability

O This component has been judged on the basis of the required spacings in the Standard for Safety of

Information Technology Equipment, Including Electrical Business Equipment, CAN/CSA C22.2 No.950-95
*UL 1950, Third Edition, including revisions through revision date March 1,1998, which are based on the
Fourth Amendment to IEC 950, Second Edition, which would cover the component itself if submitted for
Listing.

O The inverter output circuit supplied with this model is a limited Current Circuit.
O The units are supplied by Limited Power Sources.
O The terminals and connectors are suitable for factory wiring only.
O The terminals and connectors have not been evaluated for field wiring.
O A suitable Electrical and Fire enclosure shall be provided.

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