idtech ITSX95C Datasheet

Engineering Specification

Type 15.0 SXGA+ Color TFT/LCD Module

Model Name:ITSX95C

Document Control Number : OEM I-95C-02

Note:Specification is subject to change without notice. Consequently it is better to contact to

International Display Technology before proceeding with the design

of your product incorporating this module.

Product Development

International Display Technology

October 16,2001 OEM I-95C-02 1/29

Engineering Specification

i Contents

i Contents ii Record of Revision

1.0 Handling Precautions

2.0 General Description

2.1 Characteristics

2.2 Functional Block Diagram

3.0 Absolute Maximum Ratings

4.0 Optical Characteristics

5.0 Signal Interface

5.1 Connectors

5.2 Interface Signal Connector

5.3 Interface Signal Description

5.4 Interface Signal Electrical Characteristics

5.4.1 Signal Electrical Characteristics for LVDS Receiver

5.4.2 LVDS Receiver Internal Circuit

5.5 Signal for Lamp connector

6.0 Pixel format image

7.0 Parameter guide line for CFL Inverter

8.0 Interface Timings

8.1 Timing Characteristics

8.2 Timing Definition

9.0 Power Consumption

10.0 Power ON/OFF Sequence

11.0 Mechanical Characteristics

12.0 National Test Lab Requirement

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Engineering Specification

ii Record of Revision

Date

Revision

OEM95C-02April 24,2001

OEM I-95C-02October 15,2001

AllOEM95C-01January 10,2001

1,5,6,7 6 27,28

SummaryPageDocument

First Edition for customer. Based on Internal Specification EC F78952 as of September 6,2000. Cable Length : 125mm

Based on Internal Specification EC H30700 as of January 31,2001. To avoid using "inch" indication. To update Weight. To update Reference Drawings.

Updated by establishment of the New Company as "International Display Technology".

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Engineering Specification

1.0 Handling Precautions

1) Since front polarizer is easily damaged, pay attention not to scratch it.

2) Be sure to turn off power supply when inserting or disconnecting from input connector.

3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots.

4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.

5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface.

6) Since CMOS LSI is used in this module, take care of static electricity and insure human earth when handling.

7) Do not open nor modify the Module Assembly.

8) Do not press the reflector sheet at the back of the module to any directions.

9) Do not stick the adhesive tape on the reflector sheet at the back of the LCD module.

10) In case if a Module has to be put back into the packing container slot after once it was taken out from the container, do not press the center of the CFL Reflector edge. Instead, press at the far ends of the CFL Reflector edge softly. Otherwise the TFT Module may be damaged.

11) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the Interface Connector of the TFT Module.

12) After installation of the TFT Module into an enclosure ( Notebook PC Bezel, for example), do not twist nor bent the TFT Module even momentary. At designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the TFT Module from outside. Otherwise the TFT Module may be damaged.

13) The fluorescent lamp in the liquid crystal display (LCD) contains mercury. Do not put it in trash that is disposed of in landfills. Dispose of it as required by local ordinances or regulations.

14)Small amount of materials having no flammability grade is used in the LCD module. The LCD module should be supplied by power complied with requirements of Limited Power Source (2.11, IEC60950 or UL1950), or be applied exemption conditions of flammability requirements (4.4.3.3, IEC60950 or UL1950) in an end product.

15)The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit (2.4, IEC60950 or UL1950). Do not connect the CFL in Hazardous Voltage Circuit.

O

The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by International Display Techlonogy for any infringements of patents or other right of the third partied which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of International Display Technology or others.

O

The information contained herein may be changed without prior notice. It is therefore advisable to contact International Display Technology before proceeding with the design of equipment incorporationg this product.

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Engineering Specification

2.0 General Description

This specification applies to the Type 15.0 Color TFT/LCD Module 'ITSX95C'. This module is designed for a display unit of notebook style personal computer. The screen format and electrical interface are intended to support the SXGA+(1400(H) x 1050(V)) screen. Support color is native 262K colors(RGB 6-bit data driver). All input signals are LVDS(Low Voltage Differential Signaling) interface compatible. This module does not contain an inverter card for backlight.

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Engineering Specification

2.1 Characteristics

The following items are characteristics summary on the table under 25 degree C condition:

SPECIFICATIONSCHARACTERISTICS ITEMS

381Screen Diagonal [mm]

1400(x3) x 1050Pixels H x V

304.5(H) x 228.375(V)Active Area [mm]

0.2175(per one triad) x 0.2175Pixel Pitch [mm]

R,G,B Vertical StripePixel Arrangement

590 Typ.,625 MAX.Weight [grams]

317.3(W) x 242.0(H) x 6.0(D) typ./6.3(D) MAX. Physical Size [mm]

Normally WhiteDisplay Mode

Native 262K colors(RGB 6-bit data driver)Support Color

2

White Luminance [cd/m Design Point 1:(ICFL=3.5mA) Design Point 2:(ICFL=6.5mA)

]

90 Typ(center) 85 Typ(5 points average) 150 Typ(center)140 Typ(5 points average)

Lamp Power Consumption [Watt] (VCFL Line) Design Point 1:(ICFL=3.5mA) Design Point 2:(ICFL=6.5mA)

Typical Power Consumption [Watt] (VDD Line + VCFL Line) Design Point 1:(ICFL=3.5mA) Design Point 2:(ICFL=6.5mA)

Temperature Range [degree C] Operating Storage (Shipping)

200 : 1 Typ. Contrast Ratio

30Typ.,50 Max.Optical Rise Time/Fall Time [msec]

+3.3 Typ. Nominal Input Voltage VDD [Volt]

1.8 Typ.,3.2MAX.Power Consumption [Watt](VDD Line)

2.6Typ.,(W /o inverter loss)

4.2Typ.,(W/o inverter loss)

4.5Typ.5.9MAX,(W/o inverter loss)

6.0Typ.7.7MAX,(W/o inverter loss)

8 pairs LVDS(Even/Odd R/G/B Data(6bit), 3sync signals, Clock)Electrical Interface

0 to +50

-20 to +60

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Engineering Specification

2.2 Functional Block Diagram

The following diagram shows the functional block of this Type 15.0 Color TFT/LCD Module. The first LVDS port

transmits even pixels while the second LVDS port transmits odd pixels.

X-Driver

Y-Driver

< 8 pairs LVDS >

6bit color data for R/G/B

(even/odd)

DTCLK(even/odd) DSPTMG Vsync Hsync

VDD

GND

LCD-DRIVE Connector

JAE FI-XB30S-HF10 (30pin)

EVEN

PIXCEL

ODD PIXCEL

Dual LVDS RECEIVER

G/A

LCD DRIVE

CARD

LCD

Controller

DC-DC

Converter Ref circuit

TFT ARRAY/CELL

1400(R/G/B) x 1050

Backlight Unit

Lamp Connector

JST BHSR-02VS-1 (2pin)

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y

Engineering Specification

3.0 Absolute Maximum Ratings

Absolute maximum ratings of the module is as follows :

mbol Item

Conditions Unit Max MinS

V+4.0-0.3VDDLogic/LCD Drive Voltage

VVDD+0.3-0.3VINInput Signal Voltage

Note 2Vrms+1,600-VsCFL Ignition Voltage

mAms+7-ICFLCFL Current

mA20-ICFLPCFL Peak Inrush Current

Note 1deg.C+500TOPOperating Temperature

Note 1%RH958HOPOperating Relative Humidity

Note 1deg.C+60-20TSTStorage Temperature

Note 1%RH955HSTStorage Relative Humidity

G Hz1.5 10-200Vibration

Rectangle waveG ms50 18Shock

Note 1 : Maximum Wet-Bulb should be 39 degree C and No condensation. Note 2 : Duration : 50msec Max. Ta=0 degree C

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Engineering Specification

4.0 Optical Characteristics

The optical characteristics are measured under stable conditions as follows under 25 degree C condition:

SpecificationConditionsItem

NoteTyp.

Viewing Angle (Degrees)

White Luminance (cd/m ICFL 6.5 mA

Horizontal (Right) K210 (Left)

Vertical (Upper) K210 (Lower)K:Contrast Ratio

2

)

40 40

15 30

150Typ.

Center 140Typ. 5 points average

-

-200Contrast ratio

50Max30RisingResponse Time

50Max30Falling(ms)

-0.569Red xColor

-0.332Red yChromaticity

-0.312Green x(CIE)

-0.544Green y

-0.149Blue x

-0.132Blue y

-0.313 White x

-0.329 White y

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Engineering Specification

5.0 Signal Interface

5.1 Connectors

Physical interface is described as for the connector on module. These connectors are capable of accommodating the following signals and will be following components.

Connector Name / Designation

Manufacturer

Type / Part Number

Mating Receptacle Manufacture

Mating Receptacle/Part Number

Connector Name / Designation

Manufacturer

Type / Part Number

For Signal Connector

JAE

FI-XB30S-HF10

JAE

FI-X30M

For Lamp Connector

JST

BHSR-02VS-1

SM02B-BHSS-1Mating Type / Part Number

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)

(

)

Signa

e

#

Signa

#

Engineering Specification

5.2 Interface Signal Connector

l Name Pin

1

GND

l Nam

GND17FG

ReCLKIN-18GND2

ReCLKIN+19VDD3

GND20VDD4

RoIN0-21Reserved5

RoIN0+22Reserved6

GND23Reserved7

RoIN1-24Reserved8

RoIN1+25ReIN0-9

GND26ReIN0+10

RoIN2-27GND11

RoIN2+28ReIN1-12

GND29ReIN1+13

RoCLKIN-30GND14

RoCLKIN+31ReIN2-15

32ReIN2+16

FG (GND

Note: 'Reserved' pins are not allowed to connect any other line. Voltage levels of all input signals are LVDS compatible (except VDD). Refer to "Signal Electrical Characteristics for LVDS(*)", for voltage levels of all input signals.

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Engineering Specification

5.3 Interface Signal Description

The module uses a pair of LVDS receiver SN75LVDS86(Texas Instruments) compatible. LVDS is a differential signal technology for LCD interface and high speed data transfer device. Transmitter shall be SN75LVDS84/85 or compatible.

PIN #

NAME

Description SIGNAL

Frame Ground FG1 Ground GND2 +3.3V Power SupplyVDD3 +3.3V Power SupplyVDD4 Reserved Reserved5 Reserved Reserved6 Reserved Reserved7 Reserved Reserved8 Negative LVDS differential data input (Even R0-R5, G0)ReIN0-9 Positive LVDS differential data input (Even R0-R5, G0)ReIN0+10 Ground GND11 Negative LVDS differential data input (Even G1-G5, B0-B1)ReIN1-12 Positive LVDS differential data input (Even G1-G5, B0-B1)ReIN1+13 Ground GND14 Negative LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)ReIN2-15 Positive LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)ReIN2+16 GroundGND17 Negative LVDS differential clock input (Even)ReCLKIN-18 Positive LVDS differential clock input (Even)ReCLKIN+19 GroundGND20 Negative LVDS differential data input (Odd R0-R5, G0)RoIN0-21 Positive LVDS differential data input (Odd R0-R5, G0)RoIN0+22 Ground GND23 Negative LVDS differential data input (Odd G1-G5, B0-B1)RoIN1-24 Positive LVDS differential data input (Odd G1-G5, B0-B1)RoIN1+25 GroundGND26 Negative LVDS differential data input (Odd B2-B5)RoIN2-27 Positive LVDS differential data input (Odd B2-B5)RoIN2+28 GroundGND29 Negative LVDS differential clock input (Odd)RoCLKIN-30 Positive LVDS differential clock input (Odd)RoCLKIN+31 Frame GroundFG32

Note:

Input signals of odd and even clock shall be the same timing. The module uses a 100ohm resistor between positive and negative data lines of each receiver input. Even : First Pixel data Odd : Second Pixel Data

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(EVEN/ODD)

Engineering Specification

Description SIGNAL NAME

RED Data 5 (MSB)+RED 5 RED Data 4+RED 4 RED Data 3+RED 3 RED Data 2+RED 2 RED Data 1+RED 1 RED Data 0 (LSB)+RED 0

Red-pixel Data: Each red pixel's brightness data consists of these 6 bits pixel data. GREEN Data 5 (MSB)+GREEN 5 GREEN Data 4+GREEN 4 GREEN Data 3+GREEN 3 GREEN Data 2+GREEN 2 GREEN Data 1+GREEN 1 GREEN Data 0 (LSB)+GREEN 0

Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel data. BLUE Data 5 (MSB)+BLUE 5

BLUE Data 4+BLUE 4 BLUE Data 3+BLUE 3 BLUE Data 2+BLUE 2 BLUE Data 1+BLUE 1 BLUE Data 0 (LSB)+BLUE 0

Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel data. Data Clock: The typical frequency is 54MHz.-DTCLK

The signal is used to strobe the pixel +data and the +DSPTMG (EVEN/ODD) Display Timing:+DSPTMG When the signal is high, the pixel data shall be valid to be displayed.

VSYNC

Vertical Sync: This signal is synchronized with -DTCLK. Both active high/low signals are acceptable.

HSYNC

Horizontal Sync: This signal is synchronized with -DTCLK. Both active high/low signals are acceptable.

+3.3V Power SupplyVDD Ground GND

Note: Output signals from any system shall be Hi-Z state when VDD is off.

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Engineering Specification

5.4 Interface Signal Electrical Characteristics

5.4.1 Signal Electrical Characteristics for LVDS Receiver

Table . Electrical Characteristics

VcmCommon Mode Voltage

Note:

O Input signals shall be low or Hi-Z state when VDD is off.

Figure . Voltage Definitions

0.825 +|Vid|/2

ConditionsUnit MaxTypMinSymbolParameter

mV +100 VthDifferential Input High Threshold mV -100VtlDifferential Input Low Threshold mV600100|Vid|Magnitude Differential Input Voltage V2.4

-|Vid|/2 mV+50-50VcmCommon Mode Voltage Offset

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Engineering Specification

Table . Switching Characteristics

ConditionsUnitMaxTypMinSymbolParameter

MHz575451fcClock Frequency

ns19.618.517.5tcCycle Time

fc = 54MHz, jitter < 50psps700TsuData Setup Time

ps700ThdData Hold Time

ps/clk20tCJavgCycle modulation rate(Note)

Note: This specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100 clock cycles. This specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps.

Figure . Timing Definition (Even)

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Engineering Specification

Figure . Timing Definition (Odd)

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Engineering Specification

Figure . Timing Definition(detail A)

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Engineering Specification

5.4.2 LVDS Receiver Internal Circuit

Below figure shows the internal block diagram of the LVDS receiver.

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Engineering Specification

5.5 Signal for Lamp Connector

Signal NamePin #

Lamp High Voltage1

2

Lamp Low Voltage

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Engineering Specification

6.0 Pixel format image

Following figure shows the relationship of the input signals and LCD pixel format image. Even and odd pair of RGB data are sampled at a time

Even Odd Even Odd

0 1 1399

.

1398

1st Line

1050th Line

R

B R

G

B R

G

B

G

B

G

R

B R

G

B R

G

B

G

B

G

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Engineering Specification

7.0 Parameter guide line for CFL Inverter

CONDITIONUNITSMAXDP-2DP-1 MINPARAMETER

White Luminance (Center) (5 Points average)

-

90 85

150 140

-

2

(Ta=25 deg.C)cd/m

(Ta=25 deg.C)mArms7.06.53.53.0CFL current(ICFL)

KHz6040CFL Frequency(FCFL)

(Ta=25 deg.C)

Note 1

Vrms---1,500CFL Ignition Voltage(Vs)

(Ta= 0 deg.C)

Note 3

Vrms-635730-CFL Voltage (Reference)(VCFL)

(Ta=25 deg.C)

Note 2

W-4.22.6-CFL Power consumption(PCFL)

(Ta=25 deg.C)

Note 2

Note 1: CFL discharge frequency should be carefully determined to avoid interference between inverter and TFT

LCD.

Note 2:

Calculated value for reference (ICFL x VCFL = PCFL).

Note 3: CFL inverter should be able to give out a power that has a generating capacity of over 1,500 voltage. Lamp units need 1,500 voltage minimum for ignition. Note 4: DP-1 and DP-2 are recommended Design Points. *1 All of characteristics listed are measured under the condition using the Test inverter. *2 In case of using an inverter other than listed, it is recommended to check the inverter carefully. Sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. *3 In designing an inverter, it is suggested to check safety circuit very carefully. Impedance of CFL, for instance, becomes more than 1 [M ohm] when CFL is damaged. *4 Generally, CFL has some amount of delay time after applying kick-off voltage. It is recommended to keep on applying kick-off voltage for 1 [Sec] until discharge. *5 CFL discharge frequency must be carefully chosen so as not to produce interfering noise stripes on the screen. *6 Reducing CFL current increases CFL discharge voltage and generally increases CFL discharge frequency. So all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter. *7 It should be employed the inverter which has 'Duty Dimming', if ICFL is less than 4[mA].

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Engineering Specification

The following chart is CFL current versus the luminance for your reference.

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Engineering Specification

8.0 Interface Timings

Basically, interface timings described here is not actual input timing of LCD module but output timing of SN75LVDS86(Texas Instruments) or equivalent.

8.1 Timing Characteristics

UnitMAX.TYP.MIN.SymbolItemSignal

[MHz]575451FdckFreqencyDTCLK

[ns]18.5Tck

[Hz]60FvFrame Rate+V-Sync

[ms]16.67Tv

[lines]204610661058Nv

[us]46.715.78TvaV-Active Level

[lines]6231Nva

[lines]125126NvbV-Back Porch

Note:Both positive Hsync and positive Vsync polarity is recommended

[lines]11NvfV-Front Porch

[lines]1050mV-Line+DSPTMG

[KHz]63.98FhScan Rate+H-Sync

[usec]15.63Th

[Tck]1023844762Nh

[usec]1.037ThaH-Active Level

[Tck]250568Tha

[Tck]3006426ThbH-Back Porch

[Tck]248ThfH-Front Porch

[usec]12.96ThdDisplay+DSPTMG

[dots]1400nData Even/Odd+DATA

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Engineering Specification

8.2 Timing Definition

Vertical Timing

Support mode

1400 x 1050 at 60Hz (H line rate : 15.63 us)

DSPTMG

-VSYNC

+VSYNC

Horizontal Timing

Support mode

1400 x 1050 Dotclock : 108.000 MHz (54.000MHz x2)

Tvblk Vertical Blanking

0.250 ms (16 lines)

Tvf

Thblk Horizontal Blanking

2.667 us (288 dots)

Tvblk

Tva

m Active Field

16.411 ms (1050 lines)

Tvb

Thd Active Field

12.963 us (1400 dots)

Tvf VSYNC Front Porch

0.016 ms (1 line)

Tv

Thf HSYNC Front Porch

0.444 us (48 dots)

Tv,Nv Frame Time

16.661 ms (1066 lines)

m

Th,Nh H Line Time

15.630 us (1688 dots)

Tva VSYNC Width

0.047 ms (3 lines)

Tha HSYNC Width

1.037 us (112 dots)

Tvb VSYNC Back Porch

0.188 ms (12 lines)

Thb HSYNC Back Porch

1.185 us (128 dots)

DSPTMG

Th

Thf

Thblk Thd

Tha

Thb

-HSYNC

+HSYNC

Tck

VIDEO(Even)

VIDEO(Odd)

0

1

4

2

5

3

n-4 n-2

n-3

n-1

DTCLK

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Engineering Specification

9.0 Power Consumption

Input power specifications are as follows;

VDD

Voltage

CONDITIONUNITSMaxTypMinPARAMETERSYMBOL

V3.63.33Logic/LCD Drive

Load Capacitance 40uF

VDDrp

Drive Ripple Voltage

VDDns

Drive Ripple Noise

Note:Max Pattern:2 dot Vertical sub-pixel stripe.

W3.2VDD Power MaxPDD

MAX Pattern

VDD=3.6V

W1.8VDD PowerPDD

All Black Pattern

VDD=3.3V

mA890IDD Current MaxIDD Max

MAX Pattern

VDD=3.6V

mA545IDD Current IDD

All Black Pattern

VDD=3.3V

mVp-p100Allowable Logic/LCD

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Engineering Specification

10.0 Power ON/OFF Sequence

VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from

any system shall be Hi-Z state or low level when VDD is off.

150ms min.

VDD

10%

0 V

Signals

0 V

(Recommended).

Lamp

90%

10ms max.

0 min.

90% 90%

10% 10%

100ms min.

20ms min.

180ms min.

On

10% 10%

0 min.

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Engineering Specification

11.0 Mechanical Characteristics

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Engineering Specification

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Engineering Specification

12.0 National Test Lab Requirement

The display module is authorized to Apply the UL Recognized Mark.

Conditions of Acceptability

O This component has been judged on the basis of the required spacings in the Standard for Safety of

Information Technology Equipment, Including Electrical Business Equipment, CAN/CSA C22.2 No.950-95 *UL 1950, Third Edition, including revisions through revision date March 1,1998, which are based on the Fourth Amendment to IEC 950, Second Edition, which would cover the component itself if submitted for Listing.

O CF Lamp circuit for this model should be supplied from Limited Current Circuit. O The units are supplied by Limited Power Sources. O The terminals and connectors are suitable for factory wiring only. O The terminals and connectors have not been evaluated for field wiring. O A suitable Electrical and Fire enclosure shall be provided.

****** End Of Page ******

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