Note:Specification is subject to change without notice. Consequently it is better to contact to
International Display Technology before proceeding with the design
of your product incorporating this module.
Product Development
International Display Technology
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Engineering Specification
i Contents
i Contents
ii Record of Revision
1.0 Handling Precautions
2.0 General Description
2.1 Characteristics
2.2 Functional Block Diagram
3.0 Absolute Maximum Ratings
4.0 Optical Characteristics
5.0 Signal Interface
5.1 Connectors
5.2 Interface Signal Connector
5.3 Interface Signal Description
5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
5.4.2 LVDS Receiver Internal Circuit
5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection
5.5 Signal for Lamp connector
6.0 Pixel format image
7.0 Parameter guide line for CFL Inverter
8.0 Interface Timings
8.1 Timing Characteristics
8.2 Timing Definition
9.0 Power Consumption
10.0 Power ON/OFF Sequence
11.0 Mechanical Characteristics
12.0 National Test Lab Requirement
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ii Record of Revision
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Date
Revision
OEM I-901M-02January 16,2002
OEM I-901M-03May 28,2002
AllOEM I-901M-01December 21,2001
21
22
6
23
27,28
SummaryPageDocument
First Edition for customer.
Based on Internal Spec. EC H30861 as of December
11,2001.
Based on Internal Spec. EC H30861.
To update the following items.
Min. value of CFL Current
Max. value of CFL Frequency
Min. value of CFL Ignition voltage
Note
To update Luminance versus Lamp Power.
To update Weight.
To update Min. value of Frame Rate.
To update Reference Drawings.
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1.0 Handling Precautions
O If any signals or power lines deviate from the power on/off sequence, it may cause shorten the life of
the LCD module.
O The LCD panel and the CFL are made of glass and may break or crack if dropped on a hard surface,
so please handle them with care.
O CMOS-ICs are included in the LCD panel. They should be handled with care, to prevent electrostatic
discharge.
O Do not press the reflector sheet at the back of the LCD module to any directions.
O Do not stick the adhesive tape on the reflector sheet at the back of the LCD module.
O Please handle care when mount in the system cover. Mechanical damage for lamp reflector, for lamp
cable and for lamp connector may cause safety problems.
O Small amount of materials having no flammability grade is used in the LCD module. The LCD module
should be supplied by power complied with requirements of Limited Power Source (2.5, IEC60950 or
UL60950), or be applied exemption conditions of flammability requirements (4.7.3.4, IEC60950 or
UL60950) in an end product.
O The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit (2.4,
IEC60950 or UL60950).
O The fluorescent lamp in the liquid crystal display(LCD) contains mercury. Do not put it in trash that is
disposed of in landfills. Dispose of it as required by local ordinances or regulations.
O Never apply detergent or other liquid directly to the screen.
O Wipe off water drop immediately. Long contact with water may cause discoloration or spots.
O When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents
or abrasives.
O Do not touch the front screen surface in your system, even bezel.
O Gently wipe the covers and the screen with a soft cloth.
O
The information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by International Display Technology for any
infringements of patents or other right of the third partied which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of International
Display Technology or others.
O
The information contained herein may be changed without prior notice. It is therefore
advisable to contact International Display Technology before proceeding with the design of
equipment incorporationg this product.
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2.0 General Description
This specification applies to the Type 12.1 Color TFT/LCD Module 'IAXG01M'.
This module is designed for a display unit of notebook style personal computer.
The screen format and electrical interface are intended to support the XGA(1024(H) x 768(V)) screen.
Support color is native 262K colors(RGB 6-bit data driver).
All input signals are LVDS(Low Voltage Differential Signaling) interface compatible.
This module does not contain an inverter card for backlight.
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2.1 Characteristics
The following items are characteristics summary on the table under 25 degree C condition:
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SPECIFICATIONSCHARACTERISTICS ITEMS
307.2Screen Diagonal [mm]
1024(x3) x 768Pixels H x V
245.76(H) x 184.32(V)Active Area [mm]
0.240(per one triad) x 0.240Pixel Pitch [mm]
R,G,B Vertical StripePixel Arrangement
295 Typ.Weight [grams]
2
] (center)
Power Consumption [Watt]
Temperature Range [degree C]
Operating
Storage (Shipping)
261.0(W) x 198.0(H) x 5.0(D) Typ. Physical Size [mm]
Normally WhiteDisplay Mode
Native 262K colors(RGB 6-bit data driver)Support Color
150 Typ. White Luminance [cd/m
250 : 1 Typ. Contrast Ratio
30 Typ., 50 Max.Optical Rise Time / Fall Time [msec]
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2.2 Functional Block Diagram
The following diagram shows the functional block of this Type 12.1 Color TFT/LCD Module.
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<4 pairs LVDS>
RxIN0
RxIN1
RxIN2
RxCLKIN
VDD
GND
DF19KR-20P-1H
LCD DRIVE
CARD
LCD
Controller
DC-DC
Converter
Ref circuit
TFT ARRAY/CELL
1024(R/G/B) x 768
Y-Driver
Backlight Unit
X-Driver
BHSR-02VS-1
Lamp
Connector
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y
Engineering Specification
3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as follows :
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mbol Item
Conditions Unit Max MinS
V+4.0-0.3VDDLogic/LCD Drive Voltage
VVDD+0.3-0.3VINInput Signal Voltage
Vrms+1,500-VsCFL Ignition Voltage
mAms7-ICFLCFL Current
mA20-ICFLPCFL Peak Inrush Current
deg.C+500TOPOperating Temperature
%RH958HOPOperating Relative Humidity
deg.C+60-20TSTStorage Temperature
%RH955HSTStorage Relative Humidity
G Hz1.5 10-200Vibration
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Rectangle waveG ms50 18Shock
Note :
1.Maximum Wet-Bulb should be 39 degree C and No condensation.
2.Duration : 50msec Max. Ta=0 degree C
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4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25 degree C condition:
Viewing Angle
(Degrees)
White Luminance (cd/m2)
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Horizontal (Right)
K}10 (Left)
Vertical (Upper)
K}10 (Lower)K:Contrast Ratio
SpecificationConditionsItem
150 Typ.
40
40
15
30
(Center)
NoteTyp.
-
-
-
-
-250Contrast ratio
-30RisingResponse Time
-30Falling(ms)
-0.577Red xColor
-0.338Red yChromaticity
-0.310Green x(CIE)
-0.554Green y
-0.158Blue x
-0.124Blue y
-0.313 White x
-0.329 White y
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(
)
Engineering Specification
5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following components.
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Connector Name / Designation
Manufacturer
Type / Part Number
Mating Receptacle/Part Number
Connector Name / Designation
Manufacturer
Type / Part Number
For Signal Connector
HIROSE
DF19KR-20P-1H
DF19G-20S-1F (FPC Type)
DF19G-20S-1C
For Lamp Connector
JST
BHSR-02VS-1
SM02B-BHSS-1Mating Type / Part Number
Cable Type
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5.2 Interface Signal Connector
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SignalPin#SignalPin#
GND11GND1
RxIN1+12GND2
RxIN1-13Reserved3
GND14Reserved4
RxIN0+15GND5
RxIN0-16RxCLKIN+6
GND17RxCLKIN-7
GND18GND8
VDD19RxIN2+9
VDD20RxIN2-10
Note:
•'Reserved' pins are not allowed to connect any other line.
•Voltage levels of all input signals are LVDS compatible (except VDD,). Refer to "Signal Electrical
Characteristics for LVDS", for voltage levels of all input signals.
5.3 Interface Signal Description
DescriptionSignal Name
LVDS differential data input (Red0-Red5, Green0)RxIN0+, RxIN0LVDS differential data input (Green1-Green5,Blue0-Blue1)RxIN1+, RxIN1LVDS differential data input (Blue2-Blue5, HSync, VSync, DSPTMG)RxIN2+, RxIN2LVDS differential clock inputRxCLKIN+, RxCLKIN+3.3V Power SupplyVDD
GroundGND
Note :
OThe module uses a 100ohm resistor between positive and negative data lines of each receiver input.
OInput signals shall be low or Hi-Z state when VDD is off
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Red Data 5 (MSB)
Red Data 4
Red Data 3
Red Data 2
Red Data 1
Red Data 0 (LSB)
Red-pixel Data
Green Data 5 (MSB)
Green Data 4
Green Data 3
Green Data 2
Green Data 1
Green Data 0 (LSB)
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Each red pixel's brightness data consists of these 6 bits
pixel data.
Each green pixel's brightness data consists of these 6 bits
pixel data.
Green-pixel Data
+BLUE 5
+BLUE 4
+BLUE 3
+BLUE 2
+BLUE 1
+BLUE 0
-DTCLK
DSPTMG
VSYNC
HSYNC
Note : Output signals from any system shall be low or Hi-Z state when VDD is off.
Blue Data 5 (MSB)
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0 (LSB)
Blue-pixel Data
Data Clock
Display Timing
Vertical Sync
Horizontal Sync
Each blue pixel's brightness data consists of these 6 bits
pixel data.
The typical frequency is 65.0 MHz. The signal is used to
strobe the pixel data and DSPTMG signals.
This signal is strobed at te falling edge of -DTCLK. W hen
the signal is high, the pixel data shall be valid to be
displayed.
The signal is synchronized to -DTCLK .
The signal is synchronized to -DTCLK .
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5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
Table. Electrical Characteristics
Note:
O Input signals shall be low or Hi-Z state when VDD is off.
O All electrical characteristics for LVDS signal are defined and shall be measured at the interface connector
2.See figure "Timing Definition" and "Timing Definition(detail A)" for definition.
3.Jitter is the magnitude of the change in input clock period.
4.This specification defines maximum average cycle modulation rate in peak-to-peak transition within
any 100 clock cycles.
This specification is applied only if input clock peak jitter within any 100 clock cycles is greater than
300ps.
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ConditionsUnitMaxTypMinSymbolParameter
MHz676550fcClock Frequency
ns20.0015.3814.93tcCycle Time
fc = 65MHz, tCCJ < 50ps,
ps500Tsu
Vth-Vtl = 400mV,
ps500Thd
Vcm = 1.2V, Vcm = 0
ps+150-150tCCJ
ps/clk20tCJavg
Figure. Timing Definition (Even)
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Figure. Timing Definition (Odd)
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Figure. Timing Definition(detail A)
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Note: Tsu and Thd are internal data sampling window of receiver. Trskm is the system skew margin; i.e., the sum
of cable skew, source clock jitter, and other inter-symbol interference, shall be less than Trskm.
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5.4.2 LVDS Receiver Internal Circuit
The following figure shows the internal block diagram of the LVDS receiver.
This LCD module equips termination resistors for LVDS link.
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5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection
Following the suggestions below will help to achieve optimal results.
O Use controlled impedance media for LVDS signals. They should have a matched differential
impedance of 100ohm.
O Match electrical lengths between traces to minimize signal skew.
O Isolate TTL signals from LVDS signals.
OFor cables, twisted pair, twinax, or flex circuit with close coupled differential traces are recommended.
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5.5 Signal for Lamp Connector
Signal NamePin #
Lamp High Voltage1
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2
Lamp Low Voltage
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6.0 Pixel format image
Following figure shows the relationship of the input signals and LCD pixel format image.
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1st Line
768th Line
R
0
R
G
GB
B
1
RGB
RG
1022 1023
R
G
B
B
RG
R
B
B
R
G
B
G
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7.0 Parameter guide line for CFL Inverter
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CONDITIONUNITSMAXD.P-2
2
]
Ta=25[deg. C][cd/m
2
]
Ta=25[deg. C]
(L63)
White Luminance
(Center)
(5 points average)
-
-
D.P-1
(Note1)
95
90
(Note2)
150
140
-
-
[cd/m
MINPARAMETERSYMBOL
[mArms]7.06.03.52.0CFL currentICFL
Note3, 4(*7, *8)
[mA]20CFL Peak Inrush CurrentICFLP
Ta=25[deg. C]
Note3, 4(*7)
[kHz]7040CFL FrequencyFCFL
Ta=25[deg. C]
Note 1, 4(*5)
[Vrms]1,350Inverter Ignition Voltage Vinv
Ta=0[deg. C]
Note 3
[Vrms]560655CFL Voltage (Reference)VCFL
Ta=25[deg. C]
Note 2
[W]3.42.3CFL Power consumptionPCFL
Ta=25[deg. C]
Note 2, 4(*6)
Note 1: CFL discharge frequency should be carefully determined to avoid interference between inverter and TFT
LCD.
Note 2:
Calculated value for reference (ICFL x VCFL = PCFL).
Note 3: CFL inverter should be able to give out a power that has a generating capacity of over 1,350 voltage.
Lamp units need 1,350 voltage minimum for ignition.
Note 4: DP-1(Design Point-1) and DP-2(Design Point-2) are recommended Design Point.
*1 All of characteristics listed are measured under the condition using the Test inverter.
*2 In case of using an inverter other than listed, it is recommended to check the inverter
carefully. Sometimes, interfering noise stripes appear on the screen, and substandard
luminance or flicker at low power may happen.
*3 In designing an inverter, it is suggested to check safety circuit very carefully.
Impedance of CFL, for instance, becomes more than 1 [M ohm] when CFL is damaged.
*4 Generally, CFL has some amount of delay time after applying kick-off voltage. It is recommended
to keep on applying kick-off voltage for 1 [Sec] until discharge.
*5 CFL discharge frequency must be carefully chosen so as not to produce interfering noise stripes on the
screen.
*6 Reducing CFL current increases CFL discharge voltage and generally increases CFL discharge
frequency. So all the parameters of an inverter should be carefully designed so as not to produce
too much leakage current from high-voltage output of the inverter.
*7 It should be employed the inverter which has 'Duty Dimming', if ICFL is less than 4[mA].
*8 ICFL = (ICFL Peak) x (Duty Dimming Rate)
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The following chart is Luminance versus Lamp Power for your reference.
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8.0 Interface Timings
Basically, interface timings described here is not actual input timing of LCD module but output timing of
SN75LVDS86(Texas Instruments) or equivalent.
8.1 Timing Characteristics
Timing Characteristics
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NoteUnitMAXTYPMINSymbol
MHz67.0065.00 50.00DTCLK Frequencyfdck
nsec20.0015.3814.93DTCLK cycle timetck
tck204713441324X total timetx
tck102410241024X active timetacx
KHz48.363H frequencyHsync
tck1368H-Sync widthHsw
tck1608H back porchHbp
tck240H front porchHfp
tx1023806779Y total timety
Hz616055Frame rateVsync
tx61V-sync WidthVw
tx31V-sync front porchVfp
Note:
1. Vbp should be static
2. When there are invalid timing, Display appears black pattern.
Synchronous Signal Defects and enter Auto Refresh for LCD Module protection Mode.
tx768768768Y active timetacy
1tx63299V-sync back porchVbp
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8.2 Timing Definition
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1344 dot
H-Sync
DSPTMG
V-Sync
DSPTMG
3H
136 dot
6H
38H
160 dot24 dot
1024 dot
29H
768H
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9.0 Power Consumption
Input power specifications are as follows;
VDD
Voltage
VDDrp
Drive Ripple Voltage
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CONDITIONUNITSMaxTypMinPARAMETERSYMBOL
[V]3.63.33.0Logic/LCD Drive
[W]1.6VDD PowerPDD
[W]1.2VDD PowerPDD
[mA]480VDD CurrentIDD
[mA]360VDD CurrentIDD
[mVp-p]100Allowable Logic/LCD
Load Capacitance
20 uF
MAX. Pattern,
VDD=3.3[V]
All Black Pattern,
VDD=3.3[V]
MAX Pattern,
VDD=3.3[V]
All Black Pattern,
VDD=3.3[V]
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10.0 Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from
any system shall be Hi-Z state or low level when VDD is off .
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30ms min.
VDD
0 V
Signals
0 V
Lamp On
0 V
10%
90%
0.1ms min.
30ms max.
0 min.0 min.
10%
200ms min.0 min.
10%
90%
10%10%
10%
10%
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11.0 Mechanical Characteristics
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12.0 National Test Lab Requirement
The display module is satisfied all requirements for compliance to
UL60950 3rd. Ed. U.S.A. Information Technology Equipment
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