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TO: LG Electronics Inc.
Accepted By: Date :
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Customer's Acceptance Specification
Type 15.0 UXGA Color TFT/LCD Module
Model Name:IAUX14P
Document Control Number : CAS I-914P-L01
Issued By : T. TOKUDA Date: December 5,2002
Sales Support
International Display Technology
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i Contents
i Contents
ii Record of Revision
1.0 Handling Precautions
2.0 General Description
2.1 Characteristics
2.2 Functional Block Diagram
3.0 Absolute Maximum Ratings
4.0 Optical Characteristics
4.1 Luminance Uniformity
5.0 Signal Interface
5.1 Connectors
5.2 Interface Signal Connector
5.3 Interface Signal Description
5.3.1 E-EDID
5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
5.4.2 LVDS Receiver Internal Circuit
5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection
5.5 Signal for Lamp connector
6.0 Pixel format image
7.0 Parameter guide line for CFL Inverter
8.0 Interface Timings
8.1 Timing Characteristics
8.2 Timing Definition
9.0 Power Consumption
10.0 Power ON/OFF Sequence
11.0 Mechanical Characteristics
12.0 National Test Lab Requirement
13.0 Packaging Specification
14.0 Label
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ii Record of Revision
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SummaryPageDocument RevisionDate
AllCAS I-914P-L01December 5,2002
First Edition for LG Electronics Inc.
Based on Engineering Spec. OEM I-914P-01.
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1.0 Handling Precautions
O If any signals or power lines deviate from the power on/off sequence, it may cause shorten the life of the
LCD module.
O The LCD panel and the CFL are made of glass and may break or crack if dropped on a hard surface, so
please handle them with care.
O CMOS-ICs are included in the LCD panel. They should be handled with care, to prevent electrostatic
discharge.
O Do not press the reflector sheet at the back of the LCD module to any directions.
O Do not stick the adhesive tape on the reflector sheet at the back of the LCD module.
O Please handle care when mount in the system cover. Mechanical damage for lamp cable and for lamp
connector may cause safety problems.
O Small amount of materials having no flammability grade is used in the LCD module. The LCD module
should be supplied by power complied with requirements of Limited Power Source (2.5, IEC60950 or
UL60950), or be applied exemption conditions of flammability requirements (4.7.3.4, IEC60950 or
UL60950) in an end product.
O The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit (2.4, IEC60950 or
UL60950).
O The fluorescent lamp in the liquid crystal display(LCD) contains mercury. Do not put it in trash that is
disposed of in landfills. Dispose of it as required by local ordinances or regulations.
O Never apply detergent or other liquid directly to the screen.
O Wipe off water drop immediately. Long contact with water may cause discoloration or spots.
O When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents or
abrasives.
O Do not touch the front screen surface in your system, even bezel.
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O
The information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by International Display Technology for any
infringements of patents or other right of the third partied which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of International
Display Technology or others.
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2.0 General Description
This specification applies to the Type 15.0 Color TFT/LCD Module 'IAUX14P'.
This module is designed for a display unit of notebook style personal computer.
The screen format and electrical interface are intended to support the UXGA (1600(H) x 1200(V)) screen.
Support color is native 262K colors(RGB 6-bit data driver).
All input signals are LVDS(Low Voltage Differential Signaling) interface compatible.
This module does not contain an inverter card for backlight.
2.1 Characteristics
The following items are characteristics summary on the table under 25 degree C condition:
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SPECIFICATIONSCHARACTERISTICS ITEMS
381Screen Diagonal [mm]
2
] (center)
Power Consumption [Watt](VDD)
1600(x3) x 1200Pixels H x V
304.8(H) x 228.6(V)Active Area [mm]
0.1905(per one triad) x 0.1905Pixel Pitch [mm]
R,G,B Vertical StripePixel Arrangement
690 Typ., 725 Max.Weight [grams]
317.3(W) x 242.0(H) x 7.2(D) Typ./7.5(D) Max. Physical Size [mm]
Normally BlackDisplay Mode
Native 262K colors(RGB 6-bit data driver)Support Color
200 Typ.White Luminance [cd/m
400 : 1 Typ. Contrast Ratio
60 Typ., 150 Max.Optical Rise Time + Fall Time [msec]
+3.3 Typ.Nominal Input Voltage VDD [Volt]
2.9 Typ., 3.8 Max.
Lamp Power Consumption [Watt]
Typical Power Consumption [Watt]
Temperature Range [degree C]
Operating
Storage (Shipping)
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4.5 Typ.,(W/o inverter loss)
5.0 Max.,(W/o inverter loss)
7.4 Typ., 8.8 Max.(W/o inverter loss)
8 pairs LVDS(Even/Odd R/G/B Data(6bit), 3sync signals, Clock)Electrical Interface
0 to +50
-20 to +60
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2.2 Functional Block Diagram
The following diagram shows the functional block of this Type 15.0 Color TFT/LCD Module.
The first LVDS port transmits even pixels while the second LVDS port transmits odd pixels.
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X-Driver
Y-Driver
< 8 pairs LVDS >
6bit color data
for R/G/B
(even/odd)
DTCLK(even/odd)
DSPTMG
Vsync
Hsync
EEDID
V
EEDID
CLK
EEDID
Data
VDD
GND
LCD-DRIVE Connector
JAE FI-XB30S-HF10 (30pin)
EVEN
PIXEL
ODD
PIXEL
Dual LVDS
RECEIVER
G/A
EEDID
Chip
LCD DRIVE
CARD
LCD
Controller
DC-DC
Converter
Ref circuit
TFT ARRAY/CELL
1600(R/G/B) x 1200
Backlight Unit
Lamp Connector
JST BHSR-02VS-1 (2pin)
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y
Customer's Acceptance Specification
3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as follows :
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mbol Item
Conditions Unit Max MinS
V+4.0-0.3VDDLogic/LCD Drive Voltage
VVDD+0.3-0.3VINInput Signal Voltage
Vrms+1,600-VsCFL Ignition Voltage
mAms8-ICFLCFL Current
mA20-ICFLPCFL Peak Inrush Current
deg.C+500TOPOperating Temperature
%RH958HOPOperating Relative Humidity
deg.C+60-20TSTStorage Temperature
%RH955HSTStorage Relative Humidity
G Hz1.5 10-200Vibration
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Rectangle waveG ms50 18Shock
Note :
1. Maximum Wet-Bulb should be 39 degree C and No condensation.
2. Duration : 50msec Max. Ta=0 degree C
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4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25 degree C condition:
Viewing Angle
(Degrees)
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Horizontal (Right)
K}10 (Left)
Vertical (Upper)
K}10 (Lower)K:Contrast Ratio
SpecificationConditionsItem
NoteTyp.
85
85
85
85
-
-
-
-
-400Contrast ratio
-30RisingResponse Time
-30Falling(ms)
0.0300.569Red xColor
+
0.0300.332Red yChromaticity
+
0.0300.312Green x(CIE)
+
0.0300.544Green y
+
0.0300.149Blue x
+
0.0300.132Blue y
+
0.0300.313White x
+
0.0300.329White y
+
170 Min.200 Typ.White Luminance (cd/m2)
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The following is the note for the Optical Characteristics:
Viewing or Measuring
Direction
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Z
Viewing or Measuring
Direction
+h-v
LEFT
LOWER
X
CENTER OF LCD
(X=0,Y=0,Z=0)
UPPER
RIGHT
Y
w Chromaticity and White Balance are defined as the C.I.E. 1931 x,y coordinates at the center of
LCD. The Standard Equipments are as shown below table.
Standard EquipmentItem
MCPD-7000 by Ohtsuka ElecViewing Angle
MCPD-7000 by Ohtsuka ElecContrast
BM5A by TOPCON OPTICAL Co.,Ltd.Response Time
MCPD-7000 by Ohtsuka ElecWhite Luminance
MCPD-7000 by Ohtsuka ElecLuminance Uniformity
MCPD-7000 by Ohtsuka ElecChromaticity
MCPD-7000 by Ohtsuka ElecWhite Balance
The measurement is to be done after 30 minutes of Power-on of BackLight.
Unless otherwise specified, the ambient conditions are as following.
Ambient Temperature : 25 +__ 2 ( degreeC )
Ambient Humidity : 25 - 85 ( % )
Atmospheric Pressure : 86.0 - 104.0 ( kPa )
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4.1 Luminance Uniformity
When the backlight is on with all pels in the unselected state (white), the luminance uniformity is defined as
follows;
Average luminance is defined as follows.
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L
Average Luminance =
5
1 + L2 + L3 + L4 + L5
Luminance variation is measured by dividing the maximum luminance values of the 13 or 5 test points by the
minimum luminance of the 13 or 5 test points.
Maximum Luminance 13 Points
Luminance Uniformity w1.65
Minimum Luminance 13 Points (L1-L13)
Maximum Luminance 5 Points
Luminance Uniformity w1.25
Minimum Luminance 5 Points (L1-L5)
(L1-L13)
(L1-L5)
Figure. Average luminance and Luminance uniformity test points
L6 L7
L9
L11
L1 L2
L3
L12 L13
L5
L8
L10
L4
10mm
300
600
900
10mm
400
10mm
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800
1200
1
mm
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5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following components.
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Connector Name / Designation
Manufacturer
Type / Part Number
Mating Receptacle Manufacture
Mating Receptacle/Part Number
Connector Name / Designation
Manufacturer
Type / Part Number
For Signal Connector
JAE
FI-XB30S-HF10
JAE
FI-X30M
For Lamp Connector
JST
BHSR-02VS-1
SM02B-BHSS-1Mating Type / Part Number
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5.2 Interface Signal Connector
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Signal NamePin #Signal Name Pin #
GND16GND1
ReCLKIN-17VDD2
ReCLKIN+18VDD3
4
5
6
7
V
(Note 2,3)
EEDID
Reserved (Note 1)
CLK
Data
EEDID
EEDID
(Note 2,4)
(Note 2,4)
GND19
RoIN0-20
RoIN0+21
GND22
RoIN1-23ReIN0-8
RoIN1+24ReIN0+9
GND25GND10
RoIN2-26ReIN1-11
RoIN2+27ReIN1+12
GND28GND13
RoCLKIN-29ReIN2-14
RoCLKIN+30ReIN2+15
Note :
1. 'Reserved' pins are not allowed to connect any other line.
2. This LCD Module complies with "VESA ENHANCED EXTENDED DISPLAY IDENTIFICATION DATA
STANDARD Release A, Revision 1" and supports "EEDID version 1.3".
This module uses Serial EEPROM BR24C02FV (ROHM) or compatible as a EEDID function.
3. V
4. Both CLK
power source shall be the current limited circuit which has not exceeding 1A. (Reference Document :
EEDID
"Enhanced Display Data Channel (E-DDC
line and Data
EEDID
line are pulled-up with 10K ohm resistor to V
EEDID
TM
) Proposed Standard", VESA)
power source line at LCD
EEDID
panel, respectively.
Voltage levels of all input signals are LVDS compatible (except VDD,EEDID). Refer to "Signal Electrical
Characteristics for LVDS", for voltage levels of all input signals.
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5.3 Interface Signal Description
The LVDS receiver equipped in this LCD module is compatible with ANSI/TIA/TIA-644 standard.
PIN
#
4
6
7
NAME
EEDID
EEDID
EEDID
Note :
1. Input signals of odd and even clock shall be the same timing.
2. The module uses a 100ohm resistor between positive and negative data lines of each receiver input.
3. Even : First Pixel data Odd : Second Pixel Data
DescriptionSIGNAL
GroundGND1
+3.3V Power SupplyVDD2
+3.3V Power SupplyVDD3
EEDID 3.3V Power SupplyV
ReservedReserved5
EEDID ClockCLK
EEDID DataData
Negative LVDS differential data input (Even R0-R5, G0)ReIN0-8
Positive LVDS differential data input (Even R0-R5, G0)ReIN0+9
GroundGND10
Negative LVDS differential data input (Even G1-G5, B0-B1)ReIN1-11
Positive LVDS differential data input (Even G1-G5, B0-B1)ReIN1+12
GroundGND13
Negative LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)ReIN2-14
Positive LVDS differential data input (Even B2-B5, HSYNC, VSYNC, DSPTMG)ReIN2+15
GroundGND16
Negative LVDS differential clock input (Even)ReCLKIN-17
Positive LVDS differential clock input (Even)ReCLKIN+18
GroundGND19
Negative LVDS differential data input (Odd R0-R5, G0)RoIN0-20
Positive LVDS differential data input (Odd R0-R5, G0)RoIN0+21
GroundGND22
Negative LVDS differential data input (Odd G1-G5, B0-B1)RoIN1-23
Positive LVDS differential data input (Odd G1-G5, B0-B1)RoIN1+24
GroundGND25
Negative LVDS differential data input (Odd B2-B5)RoIN2-26
Positive LVDS differential data input (Odd B2-B5)RoIN2+27
GroundGND28
Negative LVDS differential clock input (Odd)RoCLKIN-29
Positive LVDS differential clock input (Odd)RoCLKIN+30
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DescriptionSIGNAL NAME
RED Data 5 (MSB)+RED 5
RED Data 4+RED 4
RED Data 3+RED 3
RED Data 2+RED 2
RED Data 1+RED 1
RED Data 0 (LSB)+RED 0
(EVEN/ODD)
Red-pixel Data: Each red pixel's brightness data consists of these 6 bits pixel data.
GREEN Data 5 (MSB)+GREEN 5
GREEN Data 4+GREEN 4
GREEN Data 3+GREEN 3
GREEN Data 2+GREEN 2
GREEN Data 1+GREEN 1
GREEN Data 0 (LSB)+GREEN 0
(EVEN/ODD)
Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel data.
BLUE Data 5 (MSB)+BLUE 5
BLUE Data 4+BLUE 4
BLUE Data 3+BLUE 3
BLUE Data 2+BLUE 2
BLUE Data 1+BLUE 1
BLUE Data 0 (LSB)+BLUE 0
(EVEN/ODD)
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Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel data.
Data Clock: The typical frequency is 81MHz.-DTCLK
The signal is used to strobe the pixel +data and the +DSPTMG (EVEN/ODD)
Display Timing:+DSPTMG
When the signal is high, the pixel data shall be valid to be displayed.
VSYNC
Vertical Sync: This signal is synchronized with -DTCLK. Both active high/low signals are
acceptable.
HSYNC
Horizontal Sync: This signal is synchronized with -DTCLK. Both active high/low signals are
acceptable.
Power SupplyVDD
GroundGND
EEDID
EEDID
EEDID
Note : Output signals except V
EEDID Power SupplyV
EEDID ClockCLK
EEDID DataData
EEDID
,CLK
and Data
EEDID
from any system shall be Hi-Z state when VDD is off.
EEDID
VSYNC should start with active high ( positive pulse ) signal from when VDD is supplied and its polarity
should not be changed.
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5.3.1 E-EDID
E-EDID detail in this LCD module is in the following table.
Addres
Description Data (hex) Remark
s (hex)
00 - 07 Header 00 FF FF FF FF FF FF 00 Header, Fixed
08 - 09 ID Manufacturer Name 24 94 "IDT"
0A - 0B ID Product code D2 22 Product code "8914"
0C - 0F ID Serial Number 01 01 01 01 Unused
10 Week of Manufacture 00 Unused
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11 Year of Manufacture 00 Unused
12 - 13 EDID Structure Version/Revision 01 02 Ver1.2
14 - 18 Basic Display Parameters/Features 80 1E 17 78 0A
19 - 22 Color Characteristics CD 75 91 55 4F 8B 26 21 50 54
23 - 25 Established Timings 00 00 00 Unused
26 - 35 Standard Timing Identification A9 40 01 01 01 01 01 01 01 01
01 01 01 01 01 01
36 - 47 Detailed Timing/Monitor Description #1 48 3F 40 30 62 B0 32 40 40 C0
13 00 31 E5 10 00 00 18
48 - 59 Detailed Timing/Monitor Description #2 00 00 00 0F 00 3B 3D 4A 4C 11
00 0A 20 20 20 20 20 01
5A - 6B Detailed Timing/Monitor Description #3 00 00 00 FE 00 49 44 54 45 43
48 0A 20 20 20 20 20 20
6C - 7D Detailed Timing/Monitor Description #4 00 00 00 FE 00 49 41 55 58 31
34 50 0A 20 20 20 20 20
7E Extension Flag 00 No extension
7F Checksum 86
VESA 1600x1200 @ 60Hz, Negative H/V-sync
polarity
Video timing min/max parameters,EDID version=1
Supplier Name "IDTECH"
Monitor Name "IAUX14P"
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5.4 Interface Signal Electrical Characteristics
5.4.1 Signal Electrical Characteristics for LVDS Receiver
The LVDS receiver equipped in this LCD module is compatible with ANSI/TIA/TIA-644 standard.
Table. Electrical Characteristics
Note:
O Input signals shall be low or Hi-Z state when VDD is off.
O All electrical characteristics for LVDS signal are defined and shall be measured at the interface
connector of LCD (see Figure "Measurement system").
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ConditionsUnitMaxTypMinSymbolParameter
Vcm=+1.2VmV+100VthDifferential Input High Threshold
Vcm=+1.2VmV-100VtlDifferential Input Low Threshold
mV600100|Vid|Magnitude Differential Input Voltage
Vth - Vtl = 200mVV1.41.21.0VcmCommon Mode Voltage
Vth - Vtl = 200mVmV+50-50VcmCommon Mode Voltage Offset
Figure. Voltage Definitions
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Figure. Measurement system
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Table. Switching Characteristics
Note 1: All values are at VDD=3.3V, Ta=25 degree C.
Note 2: See figure "Timing Definition" and "Timing Definition(detail A)" for definition.
Note 3: Jitter is the magnitude of the change in input clock period.
Note 4: This specification defines maximum average cycle modulation rate in peak-to-peak transition within
any 100 clock cycles.
This specification is applied only if input clock peak jitter within any 100 clock cycles is greater than
300ps.
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ConditionsUnitMaxTypMinSymbolParameter
MHz83.081.053.0fcClock Frequency
ns18.912.312.0tcCycle Time
fc = 81MHz, tCCJ < 50ps,
ps500TsuData Setup Time(Note 1)
Vth-Vtl = 200mV,
ps500ThdData Hold Time(Note 2)
Vcm = 1.2V, Vcm = 0
fc = 81MHzps+150-150tCCJCycle-to-cycle jitter(Note 3)
fc = 81MHzps/clk20tCJavgCycle Modulation Rate(Note 4)
Figure. Timing Definition (Even)
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Figure. Timing Definition (Odd)
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Figure. Timing Definition(detail A)
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Note: Tsu and Thd are internal data sampling window of receiver. Trskm is the system skew margin; i.e., the sum
of cable skew, source clock jitter, and other inter-symbol interference, shall be less than Trskm.
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5.4.2 LVDS Receiver Internal Circuit
Below figure shows the internal block diagram of the LVDS receiver.
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5.4.3 Recommended Guidelines for Motherboard PCB Design and Cable Selection
Following the suggestions below will help to achieve optimal results.
O Use controlled impedance media for LVDS signals. They should have a matched differential
impedance of 100ohm.
O Match electrical lengths between traces to minimize signal skew.
O Isolate TTL signals from LVDS signals.
O For cables, twisted pair, twinax, or flex circuit with close coupled differential traces are recommended.
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5.5 Signal for Lamp Connector
Signal NamePin #
Lamp High Voltage1
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2
Lamp Low Voltage
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6.0 Pixel format image
Following figure shows the relationship of the input signals and LCD pixel format image. Even and odd pair of
RGB data are sampled at a time
Even Odd Even Odd
0 1 1599
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.
1598
1st Line
1200th Line
R
R
B R
G
B R
G
B
G
B
G
R
R
B R
G
B R
G
B
G
B
G
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7.0 Parameter guide line for CFL Inverter
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CONDITIONUNITSMAXDP-1MINPARAMETER
White Luminance
-1,500CFL Ignition Voltage(Vs)
Note 1: CFL discharge frequency should be carefully determined to avoid interference between inverter and TFT
LCD.
Note 2: Calculated value for reference (ICFL x VCFL = PCFL).
Note 3: CFL inverter should be able to give out a power that has a generating capacity of over 1,500 voltage.
Lamp units need 1,500 voltage minimum for ignition.
Note 4: DP-1(Design Point-1) is recommended Design Point.
*1 All of characteristics listed are measured under the condition using the Test inverter.
*2 In case of using an inverter other than listed, it is recommended to check the inverter
carefully. Sometimes, interfering noise stripes appear on the screen, and substandard
luminance or flicker at low power may happen.
*3 In designing an inverter, it is suggested to check safety circuit very carefully.
Impedance of CFL, for instance, becomes more than 1 [M ohm] when CFL is damaged.
*4 Generally, CFL has some amount of delay time after applying kick-off voltage. It is recommended
to keep on applying kick-off voltage for 1 [Sec] until discharge.
*5 Reducing CFL current increases CFL discharge voltage and generally increases CFL discharge
frequency. So all the parameters of an inverter should be carefully designed so as not to produce
too much leakage current from high-voltage output of the inverter.
*6 It should be employed the inverter which has 'Duty Dimming', if ICFL is less than 4[mA].
-200-
-
KHz6040CFL Frequency(FCFL)
Vrms
Vrms-590-CFL Voltage (Reference)(VCFL)
W5.04.5-CFL Power consumption(PCFL)
2
(Ta=25 deg.C)cd/m
(Ta=25 deg.C)mArms8.07.653.0CFL current(ICFL)
(Ta=25 deg.C)
(Note 1)
(Ta= 0 deg.C)
(Note 3)
(Ta=25 deg.C)
(Note 2)
(Ta=25 deg.C)
(Note 2)
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The following chart is Luminance versus Lamp Power for your reference.
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8.0 Interface Timings
Basically, interface timings described here is not actual input timing of LCD module but output timing of
SN75LVDS86(Texas Instruments) or equivalent.
8.1 Timing Characteristics
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UnitMAX.TYP.MIN.SymbolItemSignal
FdckFreqencyDTCLK
31Nva
1528ThbH-Back Porch
63
511
[MHz]83.081.053.0
[ns]18.912.312.0Tck
[Hz]-60.0-FvFrame Rate+V-Sync
[ms]-16.67-Tv
[lines]204612501208Nv
[us]839.840.013.33TvaV-Active Level
[lines]
[lines]125 466NvbV-Back Porch
[lines]125 11NvfV-Front Porch
[lines]1200mV-Line+DSPTMG
[KHz]-75.0-FhScan Rate+H-Sync
[us]-13.33-Th
[Tck]2046 10801024 Nh
[us]1.185ThaH-Active Level
[Tck]255 968Tha
[Tck]
[Tck]328ThfH-Front Porch
[us]9.877ThdDisplay+DSPTMG
[dots]1600nData Even/Odd+DATA
Note: Both positive Hsync and positive Vsync polarity is recommended.
Disp Timing Period (Th, Nh) must be constant by each every line.
If Disp timing are not constant due to Spread Spectrum, the following expression has to be satisfied.
DeltaDT x Tvblk < 300 [Tck]
DTmax : Disp Timing Period MAX [Tck]
DTmin : Disp Timing Period MIN [Tck]
DeltaDT = DTmax - DTmin
Tvblk : V Blanking [lines]
Tck : DTCLK
When there are invalid timing, Display appears black pattern.
Synchronous Signal Defects and enter Auto Refresh for LCD Module protection Mode.
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8.2 Timing Definition
Vertical Timing
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Support mode
1600 x 1200 at 60Hz
(H line rate : 13.3 us)
DSPTMG
+VSYNC
Horizontal Timing
Support mode
1600 x 1200
Dotclock : 162.000
MHz (81.000MHz x2)
Tvblk
Vertical
Blanking
0.667 ms
(50 lines)
Tvf
Thblk
Horizontal
Blanking
3.457 us
(560 dots)
Tvblk
Tva
m
Active Field
16.000 ms
(1200 lines)
Tvb
Thd
Active Field
9.877 us
(1600 dots)
Tvf VSYNC
Front Porch
0.013 ms
(1 line)
Tv
Thf
HSYNC
Front Porch
0.395 us
(64 dots)
Tv,Nv
Frame
Time
16.667 ms
(1250 lines)
m
Th,Nh
H Line
Time
13.333 us
(2160 dots)
Tva
VSYNC
Width
0.040 ms
(3 lines)
Tha
HSYNC
Width
1.185 us
(192 dots)
Tvb
VSYNC
Back Porch
0.613 ms
(46 lines)
Thb
HSYNC
Back Porch
1.877 us
(304 dots)
DSPTMG
Th
Thf
Thblk Thd
Tha
Thb
-HSYNC
+HSYNC
Tck
VIDEO(Even)
VIDEO(Even)
VIDEO(Odd)
VIDEO(Odd)
0
1
4
2
5
3
n-4 n-2
n-3
n-1
DTCLK
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9.0 Power Consumption
Input power specifications are as follows;
VDD
Voltage
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CONDITIONUNITSMaxTypMinPARAMETERSYMBOL
Load Capacitance
V3.63.33.0Logic/LCD Drive
68uF
W3.8VDD PowerPDD
MAX Pattern
VDD=3.6V
VDDrp
Drive Ripple Voltage
VDDns
Drive Ripple Noise
Note : Max Pattern: Sub-pixel checker
W2.9VDD PowerPDD
mA1,250VDD Current IDD
mA880VDD Current IDD
mVp-p100Allowable Logic/LCD
mVp-p100Allowable Logic/LCD
All White Pattern
VDD=3.3V
MAX Pattern
VDD=3.0V
All White Pattern
VDD=3.3V
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10.0 Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals from
any system shall be Hi-Z state or low level when VDD is off.
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150ms min.
VDD
10%
0 V
Signals
0 V
(Recommended).
Lamp
90%
10ms max.
0 min.
90% 90%
10% 10%
100ms min.
180ms min.
90%
20ms min.
On
10% 10%
0 min.
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11.0 Mechanical Characteristics
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12.0 National Test Lab Requirement
The display module is authorized to Apply the UL Recognized Mark.
Conditions of Acceptability
Conditions of Acceptability - When installed on the end-product, consideration shall be given to the
following;
1. This component has been judged on he basis of he required spacings in the Standard for Safety of
Information Technology Equipment, CAS/CSA C22.2 No. 60950-00 *UL 60950, Third Edition, which are
based on the IEC 60950, Third Edition, which would cover the component itself if submitted for Listing.
2. The unit is supplied by Limited Power Sources.
3. The terminals and connectors are suitable for factory wiring only.
4. The terminals and connectors have not been evaluated for field wiring.
5. A suitable Electrical and Fire enclosure shall be provided.
Panel back should be separated from source of fire at least 13 mm of air or solid barrier of material of
Flammability Class V-1.
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13.0 Packaging Specification
The packaging of the LCD meets 75 cm drop test.
The following is the drawing of the package.
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14.0 Label
There are labels on the rear side of the Module.
Serial Number Label
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BARCODE CHARACTER AREA
11S ppppppp Z 1Z hhh SSSSSS
1
11S = FIXED
1
Starting identifier which
is common to component
level serial numbers.
2
Seven digit IBM part number
Assigned by the IBM laboratory
releasing the part
3
Z = FIXED
Automatically given
when using the
11S-Z format
Date Label
YY and WW of the Week Code stand for the Year and the Week of the Year of manufacturing of the Module
respectively.
2 3 4 5
1Z = FIXED
4
Location code
5
hhh = Header code
(Depend on EC Level and
Manufacturing Location)
SSSSSS = Serial Number
6
6
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UL Label
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