IDT Tsi84 User Manual

®

™

Tsi384

Evaluation Board User Manual

60E1000_MA001_08

September 2009

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: [phone] • [phone] • FAX: [phone]

©2009 Integrated Device Technology, Inc.

Printed in U.S.A.

Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

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Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely
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any applicable laws or regulations.

Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
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IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

CODE DISCLAIMER

LIFE SUPPORT POLICY

Contents

About this Document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Related Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1. Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2 PCI/X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.2.2 IDSEL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2.3 Interrupt Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2.4 PCI Pull-up Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2.5 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3 PCIe Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.4.1 Power Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.4.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.4.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.4.4 System Power Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.5 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.5.1 PCI/X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.5.2 System Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.6 Other Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.6.1 JTAG Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.6.2 EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.7 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.8 Logic Analyzer Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3

2. Configurable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.1 DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.2 Shunt Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.2.1 J1 Shunt Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2.2 J6 Shunt Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2.3 J21 Shunt Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.3 Debug Headers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3.1 J22 Tsi384 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.3.2 J23 Logic Analyzer PADs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.3.3 J38 CPLD JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.4 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.4.1 J2-J36-J37 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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Contents4

2.4.2 J3 ATX Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.4.3 P1 x4 PCIe Finger Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.5 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

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About this Document

This document describes how to test the key features of the Tsi384 using the Tsi384 evaluation board.
It can be used in conjunction with the Tsi384 Evaluation Board Schematics.

Related Information

• Tsi384 User Manual

• Tsi384 Evaluation Board Schematics

• PCI Express Base Specification (Revision 1.1)

• PCI Express CEM Specification (Revision 1.1)

• PCI Express-to-PCI/PCI-X Bridge Specification (Revision 1.0)

• PCI-X Addendum to PCI Local Bus Specification (Revision 1.0a)

Acronyms

5

Term Definition

PCIe PCI Express
PCI/X PCI or PCI-X bus mode
SerDes Serial/De-serializer

Revision History

60E1000_MA001_08, Formal, September 2009

This document was rebranded as IDT. It does not include any technical changes.

60E1000_MA001_07, Formal, May 2008

The following changes were made to this version:

• Completed various changes in response to the Tsi384 evaluation board’s removal of support for an
external arbiter (see “Arbitration”).

• Updated the document to support Revision 1.0, Assembly number E1000_AS001_05 of the Tsi384
evaluation board. This assembly version includes the hardware changes listed in the following
table.

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About this Document6

Evaluation Board Changes – Assembly E1000_AS001_03

Item Previous Usage/Definition New Usage/Definition

U11/T si384 Bridge Tsi384-133CLVZ Tsi384-133ILVZ2
PCI_LOCKn pull-up None Add 4.7K +/-1K size 0603 resistor

between pin B39 (LOCK#) and pin B41
(3.3V) on J2

3.3Vaux on J2 No connection Short pin A14 (3.3Vaux) to pin A21
(3.3V) by wiring

3.3Vaux on J36 and J37 No connection Short pin A14 (3.3Vaux) to pin A21
(3.3V) by wiring

JTAG signals pull-up 2K pull-up on R288, R293, R294,

R295

PCI reset C231 was 1uF (0603)

(0603ZD105KAT2A)

Change to 10K instead

Changed to 10uF (0603)
MFR P/N: ECJ-1VB0J106M

60E1000_MA001_06, Formal, January 2008

Corrected the descriptions of the S7 and S8 switches. Previously, these descriptions were reversed.

60E1000_MA001_05, Formal, October 2007

Added PCI pull-up resistor values to Table 3.

60E1000_MA001_04, Formal, May 2007

This document supports the Revision 1.0, Assembly number E1000_AS001_03 version of the Tsi384
evaluation board. This assembly version includes the hardware changes listed in the following table.

Evaluation Board Changes – Assembly E1000_AS001_03

Reference Designator Description

Removals

R13 Removed

Add 10 K Ohm pull-down to PCI_RST#

60E1000_MA001_03, Formal, April 2007

This is the general release version of the document. There are no technical differences between this
document and the previous version.

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Reworks

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About this Document 7

60E1000_MA001_02, Formal, March 2007

This document includes “Bill of Materials” for the Tsi384 evaluation board. It supports the
Revision 1.0, Assembly number E1000_AS001_02 version of the Tsi384 evaluation board. This
assembly version includes the hardware changes listed in the following table.

Evaluation Board Changes – Assembly E1000_AS001_02

Reference Designator Description

Changes

R88 Change to .015ohm

R242,R272,R6 Change to 1Kohm

C182,C183,C193,

C189,C207,C202

R148 Populate
R150 Populate

C77,C45 Install

C235 Change to 300nF
R208 130 Ohm
R215 220 Ohm
R220 441 Ohm
R139 2260 Ohm
R144 220 Ohm
R196 441 Ohm

Removals

R141 Remove

Reworks

Change to 2.2uF

60E1000_MA001_01, Formal, March 2007

This is the first version of the Tsi384 Evaluation Board User Manual. This document supports the
Revision 1.0, Assembly number E1000_AS001_01 version of the Tsi384 evaluation board.

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Add 1kohm resistor pull-up to LOCK#

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About this Document8

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1. Board Design

Topics discussed include the following:

• “Overview” on page 9

• “PCI/X Interface” on page 10

• “PCIe Interface” on page 12

• “Power Management” on page 13

• “Clock Management” on page 16

• “Other Interfaces” on page 18

• “Hardware Reset” on page 18

• “Logic Analyzer Connectivity” on page 18

9

1.1 Overview

The key features of the Tsi384 evaluation board include the following:

• Single x4 lane, 2.5 Gbps PCIe 1.1 compatible riser card (extended height form factor)

• Three PCI/X slots

• 32-/64-bit PCI/X bus, 25–133 MHz operation

• PCI/X power support through system or external supply

• PCIe compliance/debugging test points

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Figure 1: Evaluation Board Block Diagram

EEPROM

TSI384

3.3V PCI/X 64bit 133Mhz Edge Connector
R/A Mount Slot 0 (Top)

PCI/X

Power

Management

PCI Express Card Edge X4

PCIe

LA Probe

JTAG

Header

ATX

Connectors

EEPROM

3.3V PCI/X 64bit 133Mhz Edge Connector

Slot 1 (Middle )

PCI/X Isolation Buffer

3.3V PCI/X 64bit 133Mhz Edge Connector

Slot 2 (Lower)

Clock

Management

PCI/X bus

arbiter

1. Board Design10

1.2 PCI/X Interface

1.2.1 Overview

Tsi384 Evaluation Board User Manual
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The PCI/X Interface is implemented on the board with three slots, in which one is an R/A mounted
connector on the top of the board. All PCI/X connectors are compliant with the PCI/X 2.0b
specification. Appropriate clearance is provided such that up to three PCI/X cards can be inserted for
testing while the board is in an open-chassis standard ATX case.

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1. Board Design 11

The PCI/X Interface supports the configurations listed in Table 1.

Table 1: PCI/X Interface — Supported Configurations

Protocol

PCI 25, 33, 50, 66 3
PCI-X 50, 66 3
PCI-X 100 2
PCI-X 133 1

The support for PCI-X 133 MHz operation is possible with the use of an isolation buffer. The R/A
connector located on the top of board is available in this maximum frequency. The PCI bus is routed
forward and returned to the other slots to expand the bus for multi-slot support.

1.2.2 IDSEL Signals

IDSEL signals are connected in the following order:

• Slot 0 – R/A connector top slot: 2K ohms to AD16 (Device 0)

• Slot 1 – Vertical middle slot: 2K ohms to AD19 (Device 3)

• Slot 2 – Vertical lower slot: 2K ohms to AD18 (Device 2)
The 2K ohm resistor value is consistent with the ability of the Tsi384 to drive the AD lines 2 clock

cycles prior in PCI mode, and 4 clock cycles prior in PCI-X mode. The PCI/X Interface is unterminated
with the exception of the clock signals.

Operating

Speed (MHz)

Number of Slots

Supported

1.2.3 Interrupt Signals

The PCI interrupt signals are connected to the slots as shown in Table 2.

Table 2: PCI Interrupt Routing

Tsi384 Slot 0 Slot 1 Slot 2

AADC
BBAD
CCBA
DDCB

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1.2.4 PCI Pull-up Signals

The following signals have a pull-up resistor on the PCI bus.

Table 3: PCI Pull-up Signals

Signal Description Resistor Value

PCI_CBE#[4:7] Byte enables for upper 32-bit AD lines 8.2K
PCI_REQ#[0:3] Bus request 8.2K
PCI_GNT#[0:3] Bus grant 8.2K
PCI_FRAME# Control signal 8.2K
PCI_IRDY#, PCI_TRDY# Control signal 8.2K
PCI_STOP# Control signal 8.2K
PCI_SERR# System error 8.2K
PCI_PERR# Parity error 8.2K

1. Board Design12

PCI_PAR Parity of lower 32-bit lines and CBE bus 8.2K
PCI_PAR64 Parity of upper 32-bit AD lines and CBE bus 8.2K
PCI_DEVSEL# Device select line 8.2K
PCI_INT#[A:D] Interrupt line 2.4K
PCI_PME# PCI Power Management Event occurred 8.2K

1.2.5 Arbitration

The Tsi384 evaluation board has provisions to implement an external arbiter; however, the current PCB
assembly does not have the external arbiter implemented. Therefore, the only valid mode of operati on
is internal arbiter enabled.

1.3 PCIe Interface

The Tsi384 evaluation board implements a four-line PCIe interface. It is designed to connect onto a
PCIe system with a standard x4 finger connector. The system must provide the REFCLK and PERSTN
signals. The PCIe interface has the following design elements:

• Supports Hot insertion and removal

• Mid-bus logic analyzer pads for PCIe RXD/TXD signal probing

• AC coupling on the TXD lanes

• JTAG TDI - TDO loopback for chain continuity

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1. Board Design 13

1.4 Power Management

1.4.1 Power Regulation

The evaluation board’s power regulation is implemented as follows:

• Digital 3.3V power supply available from DC/ D C re gu lator or ATX supply

• Digital 1.2V switching regulator

• PCIe supplies filtered using EMI ferrite networks
To support PCI/X cards, the following additional power resources are included:

• 12V to 5V DC/DC converter

• 12V to 3.3V DC/DC converter

• External power connectors – ATX 20-pin connector for supplying all power from an ATX power
supply

1.4.2 Power Requirements

The power requirements and implementation for the Tsi384 is as follows.

Table 4: Tsi384 Power Requirements

Supply Name Symbol Supplied Source

Device Core 1.2V_384 DC/DC switching regulator w/Enable pin
PCIe 1.2V Core 1.2V_A_384 Passive Filter
PCI 3.3v supply 3.3V_384 Power switch w optional Ferrite filter to reduce

PCIe 3.3v supply 3.3V_A_384 Passive Filter

The target power draw of the Tsi384 is a maximum of 2 Watts, all supplies combined. The supplies to
the Tsi384 are controlled during ramp up using enable pins on regulators and switches.

1.4.2.1 PCIe

The PCIe CEM Specification 1.1 defines power limits on PCIe slots according to the number of lanes
available on the card. Power rules regarding x4 PCIe slots are a maximum of 25W slot. Current limits
are included in Table 5.

Table 5: PCIe Connector Current Limits

EMI/noise from PCI environment

Rail Current

3.3V 3A
12V 2.1A

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