IDT Tsi620 User Manual

IDT

Tsi620 Evaluation Board

User Manual

60D7000_MA001_03

August 7, 2009

6024 Silver Creek Valley Road San Jose, California 95138

Telephone: [phone] • FAX: [phone]

Printed in U.S.A.

©2009 Integrated Device Technology, Inc.

Integrated Device Technology, Inc. ("IDT") reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or
performance. IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information
herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may
contain errata which can affect product performance to a minor or immaterial degree. Current characterized errata will be made available upon request. Items identified
herein as "reserved" or "undefined" are reserved for future definition. IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition
of such items. IDT products have not been designed, tested, or manufactured for use in, and thus are not warranted for, applications where the failure, malfunction, or
any inaccuracy in the application carries a risk of death, serious bodily injury, or damage to tangible property. Code examples provided herein by IDT are for illustrative
purposes only and should not be relied upon for developing applications. Any use of such code examples shall be at the user's sole risk.

Copyright © 2009 Integrated Device Technology, Inc.
All Rights Reserved.

The IDT logo is registered to Integrated Device Technology, Inc. IDT and CPS are trademarks of Integrated Device
Technology, Inc.

.

“Accelerated Thinking” is a service mark of Integrated Device Technology, Inc.

GENERAL DISCLAIMER

Contents

1. Board Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Board Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2.1 Baseband Processing Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2.2 Board Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2.3 Board Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3 Board Hardware Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3.1 sRIO Switching and PrPMC Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.3.2 FPGA Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.3.3 DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.3.4 System Management Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.3.5 Clocking Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.3.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.3.7 JTAG Port and I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.4 PCB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.4.1 PCB Form Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.5 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.5.1 DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.5.2 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.5.3 Push Button and Toggle Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.6 Board Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.6.1 JTAG and FPGA Programming Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.6.2 Communication Interface Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.6.3 SMA Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.6.4 MISC Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.7 LEDs and Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.7.1 Power Good Indicators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.7.2 AMC MMC LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.7.3 LED Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.7.4 Tri-color LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.7.5 SFP Optical Transceiver LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

1.7.6 GPIO LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3

2. Board Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.1 PMC Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.1.1 Running the Software Using Ramdisk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.1.2 Running the Software Using NFS Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.1.3 Installing the PMC Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.1.4 Modifying the PMC Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.2 FPGA Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.2.1 Installing the FPGA Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.2.2 Running the FPGA Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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2.2.3 FPGA Hardware Load Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.2.4 Software Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.3 DSP Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.3.1 Installing the DSP Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.3.2 Running the DSP Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.3.3 DSP Hardware Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.4 PMC/DSP/FPGA Software Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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About this Document

This document discusses the functional characteristics of the Tsi620 evaluation board. It describes the
board’s key specifications, system architecture, and hardware implementation approaches. In addition,
it discusses the board’s configuration options, connectors, and LEDs.

The next version of this document will explain how the board’s software can be used to test the board’s
PMC, FPGA, and DSP capabilities.

Terms

AIF Antenna Interface

AMC Advanced Mezzanine Card

BB Baseband

5

bps Bit per second

BW Bandwidth (Usually means row data including encryption and service)

CPRI Common Public Radio Interface

DDR2 Double Data Rate 2 SDRAM

DFT Design for Testing

DSP Digital Signal Processor

EVB Evaluation Board

H/W Hardware

I/F Interface

LE Logic Element (FPGA programmable logic unit)

MMC MicroTCA AMC module management controller

OBSAI Open Base Station Air Interface

RF Radio Frequency

S/W Software

SFP Small Form Factor Pluggable

SPI Serial Peripheral Interface

SRIO Serial RapidIO

PrPMC Processor PMC

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6

Revision History

60D7000_MA001_03, Formal, August 2009

There are no technical changes to this document.

60D7000_MA001_02, Formal, November 2008

This version was updated to include information about the software on the Tsi620 evaluation board
(see “Board Software”).

60D7000_MA001_01, Preliminary, June 2008

This is the first version of the Tsi620 Evaluation Board Manual.

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1. Board Hardware

This section discusses the following topics:

• “Overview” on page 7

• “Board Architecture” on page 7

• “Board Hardware Functional Description” on page 12

• “PCB Characteristics” on page 30

• “Configuration Options” on page 31

1.1 Overview

This chapter discusses the functional characteristics of the Tsi620 evaluation board. It describes the
board’s key specifications, system architecture, and hardware implementation approaches.

7

The Tsi620 evaluation board serves the following purposes:

• To demonstrate the Tsi620’s potential application in a typical wireless baseband processing system

• To provide a hardware platform for customers to assess the Tsi620’s major features and to evaluate
the performance of the device in a real wireless base station system

• To function as a design reference for customer’s Tsi620 hardware development

1.2 Board Architecture

1.2.1 Baseband Processing Data Flow

The Tsi620 evaluation board can function as a baseband processing module in a wireless base station
application. The board can connect to an RF module with OBSAI/CPRI links. It is assumed that the
board will be functioning in an MicroTCA chassis with AMC-sRIO backplane, which provides
networking and system management interconnection.

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8

AMC Finger Connector

Tsi620

SRIO Swi tch

SFP

Cage

SFP

Cage

TCI6488

DSP

BB Processing

Stratix3

FPGA

BB Processing

PrPMC Connector

AMC Vertical Connector

DDR2 256MB

x4 SRIO

PCI 32b/66M

‘XGMII

DDR2 32b/614M

x2 SRIO

RJ45

x1 SGMI I

1000BaseT

1x OBSAI/CPRI

1x OBSAI/CPRI

768Mb-BW

3Gb-BW

10Gb-BW

5Gb-BW

10Gb-BW

1Gb-BW

10Gb-BW

PowerPC

Processor

RF

Module

OBSAI/CPRIx4

RJ45

4x 768Mb-BW

RJ45

x4 SRIO

x1 SGMII

1x OBSAI/C PRI

3Gb-BW

RJ45

100BaseTx1 MII

Figure 1: Baseband Processing Data Flow

The major baseband processing engine on the evaluation board is a TI triple-core DSP TCI6488 with
3-GHz processing capability. Altera’s Stratix3 FPGA with up to 150K LE functions as the DSP
accelerator of the baseband data processing. Two antenna OBSAI/CPRI links provide the interface to
an RF module through SFP optical transceiver over optical cable. The low-speed OBSAI link with
780 Mbps is directly connected to the FPGA, and another high-speed OBSAI with up to 3 Gbps is fed
directly into the DSP antenna interface. One OBSAI/CPRI link is also supported between the AMC
backplane at port 17 and the DSP antenna interface.

The Tsi620 functions as the central traffic hub to provide high-bandwidth data flow of the AMC
backplane, FPGA, DSP, and PrPMC module. The processed data can be transmitted to the AMC sRIO
backplane through the Tsi620 sRIO switch. Both upstream and downstream data flow can be
implemented. The data transfer between the DSP and FPGA is through the Tsi620 using two 1x sRIO
links so that the FPGA can function as a powerful accelerator to assist DSP baseband processing. The

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on-board PrPMC connector, which can function as the system management host and Ethernet
networking interface, supports all standard PrPMC modules.

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1.2.2 Board Specification

1.2.2.1 Baseband Processing Engine

• TI TCI6488 DSP

— Triple 1-GHz core fixed-point DSP with enhanced baseband processing capability

— 64-KB L1 cache, 3-MB L2 cache, and 64-KB L3 ROM

— External 256 MB, 32-bit DDR2 SDRAM at 614 M DDR speed

— External 4 MB serial Flash through the McBSP/SPI interface

— One OBSAI/CPRI link from the SPF connector

— One OBSAI/CPRI link from the AMC backplane port 17

— OBSAI speed: 768 Mbps, 1536 Mbps, 3072 Mbps

— CPRI speed: 614.4 Mbps, 1228.8 Mbps, 2457.6 Mbps

— Four OBSAI/CPRI links to the FPGA support OBSAI at 768 Mbps or CPRI at 614.4 Mbps

— One GigE SGMII port to RJ45 connector

— Dual x1 sRIO ports to Tsi620 sRIO switch with 5 Gb bandwidth

9

•Altera Stratix3 FPGA

— EP3SL150, 488 IOs, 780 FBGA 29 x 29 mm

— 150K LE

— 9.4-Mb embedded RAM

— XGMII-like Interface to sRIO switch with 10 Gb bandwidth

— One OBSAI/CPRI link to SFP port supports OBSAI at 768 Mbps or CPRI at 614.4 Mbps

— Four OBSAI/CPRI links to DSP supports OBSAI at 768 Mbps or CPRI at 614.4 Mbps

— One 10/100BaseT Ethernet to RJ45 connector

— System clocking synchronization interface and management

1.2.2.2 Antenna Interface

• Supports OBSAI/CPRI protocols on antenna interface

• Two OBSAI/CPRI links through the SFP connectors

• One OBSAI/CPRI link from AMC port 17

• Low-speed OBSAI/CPRI link to FPGA supports OBSAI at 786 Mbps and CPRI at 614.4 Mbps

• High-speed OBSAI/CPRI link to DSP supports OBSAI up to 3072 Mbps and CPRI up to

2457.6 Mbps

• Supports system frame synchronization through SMA connectors or AMC backplane

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1.2.2.3 sRIO Fabric

• Tsi620 functions as the central hub to provide high-bandwidth data traffic of backplane, FPGA,
DSP, and PrPMC

• Tsi620 sRIO switch with dedicated PCI Interface and RIO XGMII port

• 4x sRIO link to AMC-sRIO backplane with 10-Gb bandwidth

• 4x sRIO link to AMC vertical slot for AMC to AMC connection in stand-alone mode

• 32-bit, 66-MHz PCI interface to PrPMC module

• XGMII-like 4x RIO port to FPGA with 10-Gb bandwidth

• Dual 1x sRIO links to DSP with 5-Gb bandwidth

1.2.2.4 Ethernet Network Interface

• GigE RJ45 port to DSP SGMII EMAC for external network connection

• PrPMC module can bridge between the external Ethernet network and Tsi620’s sRIO switch

• Supports AMC backplane port 0 GigE (1000Base-BX) to RJ45 to facilitate system management
networking connection

• 10M/100M Base-T RJ45 to Stratix3 FPGA

1.2.2.5 Board Form Factor

• Single width, full height, and custom length AMC card (73.8W x 350L x 29H mm)

• Supports a standard PrPMC module on the extension segment

• Available vertical AMC connector for another AMC card in stand-alone operation mode

• Front panel connectors: 2 x SFP cages, 2xRJ45(GigE), and 1xMINI-USB

• Additional connectors: RJ45 (100BaseT) and 12V DC input barrel plug

• Supports DSP emulation port and FPGA JTAG port on board

• AMC physical Hot Swap function with the manual toggle switch

1.2.2.6 Design for Testing Features

• 4x sRIO to AMC vertical connector for stand-alone operation

• USB based JTAG port on Tsi620 for the internal register access

• Tsi620 on-die scope support with standard JTAG port (Wiggler)

• 60-pin DSP emulator connector for DSP development

• Single JTAG header for both Altera FPGA and Actel FPGA programming and debugging

• GPIO signal network of Tsi620, FPGA, and DSP

• Two LED-display attached to FPGA

• LEDs, DIP switches, and test points, for testing support

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1.2.2.7 Clocking Distribution

• On-board clock generation and distribution for sRIO domain, GigE domain, and OBSAI domain

• On-board clock generation and distribution for FPGA, DSP, and Tsi620

• SMT connectors for the base station system frame synchronization

• AMC backplane system clocking synchronization

1.2.2.8 Board System Controller

• Actel Flash-based FPGA, AFS600-FBGA256

• Board reset control

• Power sequence control and monitoring

• Board status report

• AMC MMC support

• Multiple voltage interface conversion

1.2.2.9 Power Management

11

• Meets AMC.0 specification for power management

• 12V power supply from AMC finger connector

• 12V@5A DC input connector for stand-alone operation

• 60W maximum power consumption including PrPMC module

• 3.3V@100mA for AMC management power

1.2.3 Board Architecture

Figure 2 displays the architecture of the Tsi620 evaluation board. The board includes the following

functional blocks; each block’s architectural features are discussed in the next section (see “Board

Hardware Functional Description”):

• sRIO switching and PrPMC module

• Stratix3 FPGA block

• TCI6488 DSP block

• GigE interface

• Clocking distribution

• Power management

• System controller

• AMC backplane and front panel connectors

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12

AMC Finger Connector

Tsi620

SRIO Switch

SFP

Cage

SFP

Cage

TCI6488

DSP

Stratix3

FPGA

PrPMC Connector

AMC Ver tical Connector

DDR2 256MB

DSP

Emulator

x4 SRIO

x4 SRIO

PCI 32b/66M

‘XGMII

DDR2 32b/614M

x2 SRIO

OBSAI/CPRI

RJ45

x1 SGMI I

1000BaseT

OBSAI/CPRI (High Speed)

OBSAI /CPRI ( Low Sp eed)

POWER

Management

USB

SGMII

PHY

SPROM

SFLASH

4MB

CLOCK Management

RESET Contr ol

SPI

I2C

USB--

JTAG

Sync_SMA

PushButton

GPIO x 16

I2C

4x OBSAI/CPRI

Low Speed

AFS600

System

Controller

+12V@5A

Power Monitor

JTAG

RJ45

SGMII

PHY

x1 1000BASE- BX

LED

DIS

MMC

SYSCLK

JTAG

+12V

3.3V_MP

Mictor

AIF Port 1x OBSAI/CPRI

High Speed

MII

PHY

RJ45

100BaseT

Header

GPIO x6

GPIO x6

GPIO x4

Figure 2: Evaluation Board Architecture

1.3 Board Hardware Functional Description

1.3.1 sRIO Switching and PrPMC Module

Tsi620 sRIO switch provides the high-speed interconnection of AMC backplane, on-board vertical
AMC slot, Stratix3 FPGA, TI DSP, and the processor module (see Figure 3).

1.3.1.1 sRIO Switch

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• Tsi620 sRIO switch with an endpoint to PCI interface

• 4x sRIO link to AMC backplane with speed at 1.25 Gbaud. 2.5 Gbaud, and 3.125 Gbaud

• AMC finger connector with MMC support

• 4x sRIO link to on-board AMC slot connector with speed at 1.25 Gbaud, 2.5 Gbaud, and

3.125 Gbaud

• Conforms to AMC.1 and AMC.4 specification by PCIMG

• AMC.4 fabric port assignment support: Type4 (4x) only

• Two 1x sRIO links between TCI6488 and Tsi620

• XGMII interface to FPGA with 4x RapidIO protocol

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Figure 3: sRIO Switch and PrPMC Interface

SP0

SP2

4x SRIO

4x SRIO

SP4

SP5

1x SRIO

1x SRIO

SP6

4x FMAC

XGMI I R x 37pin

XGMI I Tx 37pin

SREP

PCI 32b 66M

AMC Finger

Connector

AMC Vertical

Connector

TCI6488

DSP

Stratix3

FPGA

Pr PMC 32 b

Connector

I2C

EEPROM

I2C_Master

PCI_CLK

PCI_Arbiter

TSI620 SRIO Switch

USB to

JTAG

JTAG

USB

S_CLK

156.25MHz
REF_CLK

CRSTn BRSTn

Reset

Controller

GPIO[0:15]

PCI_Reset

Pull-up/down

Resistors

PWRUP

CONFIG

GPIO[16:23]

1.2V3.3V 1.5V

INT(a,b,c,d)

MMC

156.25MHz

RX_CLK

JTAG

PHY

1x SGMII

RJ45

13

Table 1: sRIO Switch Power-Up Configuration Setting

Pin Name Setting Description

SP_HOST 0/1 0 = Not host

1 = Host (PrPMC is supposed to be the host) (S4 bit[1])

SP_MAST_EN 1 EndPoint can issue RapidIO Request packets

SP0_MODE_SEL 0 0 = 4x Connect to AMC vertical connector

SP2_MODE_SEL 0 0 = 4x Connect to AMC finger connector

SP4_MODE_SEL 1 1 = SP4 1x and SP5 1x connect to dual DSP 1x sRIO

SP6_MODE_SEL 1 1 = SP6 4x mode for FPGA I/F

SP_IO_SPEED[1:0] (10),01,00 10 = 3.125 Gb (Default)

SP_CLK_SEL[1:0] 01 01 = 156.25 MHz

SP(n)_PWRDN n=2,4,5,6 0 0 = Port 2, 4, 5, 6 are powered up (assuming SP(0) is always powered up)

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01 = 2.5 Gb

00 = 1.25 Gb (S4 bit[4:3])

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Table 1: sRIO Switch Power-Up Configuration Setting (Continued)

Pin Name Setting Description

SP(n)_PWRDN n=1,3 1 1 = Port 1 and 3 are powered down

SP_TX_SWAP 1 1 = Ports [0, 2, 4] Tx lane order is D, C, B, A

SP_RX_SWAP 1 1 = Ports [0, 2, 4] Rx lane order is D, C, B, A

1.3.1.2 Processor PMC (PrPMC) Interface

The PrPMC module is a high-performance, processor-based intelligent controller that can perform the
following functions:

• On-board system management

• Board software configuration

• Board booting control

• System interrupt handling

• Interface bridging between the module and the external networking system

• System operation status report and maintenance

• Baseband data processing assistance in real time

The PrPMC interface has the following features:

• Compliant to the following specifications:

— PCI Local Bus Specification (Revision 2.3)

— PCI Bus Power Management Specification (Revision 1.1)

— IEEE1386.1

— ANSI/VITA 32-2003

• PCI interface:

— 32-bit bus

— 33MHz/66MHz

— 3.3V signal only

— Tsi620 internal PCI arbiter

— Tsi620 PCI clock generator performs PCI clocking

— PCI interrupt handler: PrPMC module

— Tsi620 drives reset to PrPMC (PrPMC may issue system reset from PMC_RESETOUT#)

• PrPMC: system host for sRIO switching and monarch for PCI bus

• Physical position: PrPMC module located on AMC extension segment out of chassis

• Physical connector: 3x 64-pin CMC connectors (Jn1, Jn2, Jn3)

• Maximum power consumption: 24W

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Table 2: PCI Interface Power-Up Configuration Setting

Pin Name Setting Description

PCI_RSTDIR 1 1 = PCI_RSTn is an output

PCI_M66EN 1/0 1 = 66MHz (PrPMC card could force it to 0 to 33 MHz operation using

S3 bit [1])

PCI_PLL_BYPASS 0 0 = PCI PLL is enabled

PCI_ARBEN 1 1 = PCI internal arbiter is used

PCI_HOLD_BOOT 0 0 = Release PCI software reset immediately after a Tsi620 reset is

completed

SPARE[1:0] 00 00 = Tsi620 (pull-up/down required for BOM selection)

Table 3: PrPMC Interrupt Routing

Interrupt Line Source Description

15

INTA Tsi620 Tsi620 interrupt output to PrPMC

INTB FPGA FPGA real-time events

INTC System Controller System administration coordination

INTD DSP DSP real-time events

1.3.1.3 XGMII FPGA Interface

• Tx/Rx clocking: synchronous 156.25, 125, or 62.5 MHz

• Tx_CLK: source to FPGA for RIO-XGMII interface clocking

• Signaling: HSTL-1.5V DDR

• Transmit: Tx_CLK, Tx_D[31:0], Tx_CTL[3:0], Tx_PHY_DISABLE

• Receive: Rx_CLK, Rx_D[31:0], Rx_CTL[3:0], Rx_ERROR

• The FPGA provides both on-chip parallel and serial termination for the XGMII interface.
Note: This feature is not supported on revision 1 of the prototype board.

1.3.1.4 JTAG, GPIO, and I2C

• Tsi620 supports I2C master mode or optional slave mode with jumper setting

• External socket I2C device with 8 DIP package (AT24C64B)

• Supports I2C configuration loading

• Uses FT2233D, USB to UART/FIFO controller, as USB to JTAG port converter

• Supports Tsi620 register access through JTAG port (mini-USB connector)

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• Mini USB connector on front panel with USB2.0 compatible

• Tsi620 GPIO[0:15] connection to DSP and FPGA

• Standard JTAG header for Tsi620 on-die scope support

Table 4: I2C Power-Up Configuration Setting

Pin Name Setting Description

I2C_MA (PU) 0 1 = Multi-byte peripheral addressing

I2C_SA[6:0] (PU) 0000000 I2C port slave address

I2C_SLAVE (PU) 0 0 = Disable the I2C slave mode

I2C_SEL (PU) 0 only 0 = Asserted, I2C_SA[1,0] are used as the lower 2 bits of EEPROM

I2C_DISABLE (PD) 0/1 0 = Enable I2C register loading

1 = Disable I2C register loading (DIP Switch, S4 bit [2])

Table 5: Tsi620 GPIO Signal Assignment

GPIO Signal Connect To Description

GPIO[0:15] FPGA Intercommunicating between Tsi620 and FPGA

GPIO[16:23] DIP Switch and LED GPIO[16:19] connected to DIP Switch S2[1:4]

GPIO[20:23] connected to LED D3, D5, D6, and D4, respectively

GPIO[24:31] LED, Test point Intercommunicating between Tsi620 and the system controller (AFS600)

1.3.1.5 AMC Interfaces

• AMC finger connector supports sRIO AMC backplane

• AMC finger connector supports MMC including I2C

• AMC finger connector supports port 0 GigE (1000Base-BX) interface to RJ45 through the
VSC8221 PHY (AMC.2)

• AMC finger connector does not support JTAG

• 3.3V management power; maximum 100 mA from figure connector

• AMC vertical slot connector does not support JTAG, I2C, and MMC functions

• AMC vertical slot shared with 12V power and local 3.3V

• Total power consumption including PrPMC and AMC slot should not be more than 60W

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1.3.2 FPGA Block

30.72MHz_REF

Stratix3 FPGA

780FBGA

EP C S64 AS-CF GHeader

RIO

XGMI I

OBSAI

Frame_Sync

XGMI I R x 38pi n

XGMI I Tx 38pin

Tsi620

GPIO[0:15]

156. 25M

DDR

PLL

x1

RX_CLK

PLL
x10

PLL

x8/10

GigE_ REF(p,n)

SFP

SMT_IN

FSYNC_OUT

FSYNC_IN

156. 25MHz

Mictor

Switching

Fabric

LED

Display

OBSAI

SERDES

O

B

S

A

I

7

6

8

M

b

/

C

P

R

I

6

1

4

.

4

M

b

DSP

JTAG

EMAC

10/100M

PHY

MII

RJ45

100B aseT

The Altera Stratix3 FPGA can function as either a baseband data processing engine or as an accelerator
to assist DSP baseband data processing (see Figure 4). The FPGA block includes a 780-pin FPGA,
FPGA configuration, RIO XGMII interface, and an antenna interface.

1.3.2.1 FPGA Device

• Altera Stratix3 EP3SL150 in 780-pin BGA

• Package: 29 x 29 mm, 780-pin FBGA with 1 mm pitch

• Speed grade: -3

• Core voltage: 1.1V

• Clock tree performance: 450 MHz for -4 grade

• Maximum IO pins: 480

• Maximum allowed power consumption: 10W

Figure 4: FPGA Block Diagram

17

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