IDT TSI384 User Manual

®

IDT

®

Tsi384 PCIe®-to-PCI Bridge

User Manual

May 5, 2014

Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

GENERAL DISCLAIMER

Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely
at your own risk. IDT MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITA BIL IT Y
OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICU­LAR PURPOSE, OR NON-INFRINGEMENT. FURTHER, IDT MAKES NO REPRESENTATIONS OR WARRANTIES AS TO THE TRUTH, ACCURACY OR COMPLETENESS
OF ANY STATEMENTS, INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR
THAT IS CONTAINED ON ANY IDT INTERNET SITE. IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, INCIDENTAL, INDIRECT, PUNITIVE OR
SPECIAL DAMAGES, HOWEVER THEY MAY ARISE, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code
examples also may be subject to United States export control laws and may be subject to the export or import laws of other countries and it is your responsibility to comply with
any applicable laws or regulations.

Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.

IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

CODE DISCLAIMER

LIFE SUPPORT POLICY

Contents

About this Document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1. Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.2.1 General Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.2.2 PCIe Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.2.3 PCI-X Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.2.4 PCI Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.3 Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2 PCIe Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3 PCI/X Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.4 EEPROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.5 JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.6 Power-up Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.7 Power Supply Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3

3. Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1.1 Upstream Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1.2 Downstream Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2 Transaction Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.2.1 Upstream Transaction Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.2.2 Downstream Transaction Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.3 Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.3.1 Upstream Non-posted Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.3.2 Upstream Posted Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.3.3 Downstream Non-posted Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.3.4 Downstream Posted Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.4 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.5 Prefetching Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.6 Short Term Caching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.7 Lane Reversal and Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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4. Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.2 Memory-mapped I/O Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.3 Prefetchable Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.4 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.5 VGA Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.6 ISA Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.7 Non-transparent Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.7.1 PCIe to PCI/X Non-prefetchable Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.7.2 PCIe to PCI/X Prefetchable Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.7.3 PCI/X to PCIe Address Remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.8 Opaque Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5. Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.2 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.2.1 Type 0 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.2.2 Type 1 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.2.3 Type 1 to Type 0 Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.2.4 Type 1 to Type 1 Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.2.5 Type 1 to Special Cycle Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3 PCIe Enhanced Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.4 Configuration Retry Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6. Bridging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.2 Flow Control Advertisements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.3 Buffer Size and Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.4 Assignment of Requestor ID and Tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.5 Forwarding of PCIe to PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.5.1 PCIe Memory Write Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.5.2 PCIe Non-posted Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.6 Forwarding of PCIe to PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.6.1 PCIe Memory Write Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.6.2 PCIe Non-posted Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.7 Forwarding of PCI to PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.7.1 PCI Memory Write Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.7.2 PCI Non-posted Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.8 Forwarding of PCI-X to PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.9 Split Completion Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.10 PCI Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.11 PCI-X Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.12 PCIe Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.13 Message Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.13.1 INTx Interrupt Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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6.13.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.13.3 Locked Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.13.4 Slot Power Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.13.5 Vendor-defined and Device ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.14 Transaction Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7. PCI/X Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.3 PCI/X Arbitration Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8. Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

8.3 Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9. Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9.2 PCIe as Originating Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9.2.1 Received Poisoned TLPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

9.2.2 Received ECRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

9.2.3 PCI/X Uncorrectable Data Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

9.2.4 PCI/X Uncorrectable Address/Attribute Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

9.2.5 Received Master-Abort on PCI/X Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

9.2.6 Received Target-Abort On PCI/X Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.2.7 PCIe Unsupported Request Completion Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

9.2.8 PCIe Completer Abort Completion Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

9.2.9 Receiver of an Unexpected Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

9.3 PCI/X as Originating Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

9.3.1 Received PCI/X Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

9.3.2 Unsupported Request Completion Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

9.3.3 Completer Abort Completion Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

9.3.4 Split Completion Message with Completer Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

9.4 Timeout Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

9.4.1 PCIe Completion Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

9.4.2 PCI Delayed Transaction Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

9.5 Other Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

9.6 Error Handling Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

10. Reset, Clocking, and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

10.1 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

10.1.1 PCIe Link Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

10.1.2 PCI/X Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

10.2 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

10.2.1 PCIe Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

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10.2.2 PCI/X Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

10.3 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

11. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

11.1.2 Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

11.2 Power Management Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

11.3 Power States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

11.3.1 ASPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

11.3.2 L0 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

11.3.3 L0s State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

11.3.4 L1 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

11.3.5 L2/L3 Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

11.3.6 L3 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

11.3.7 LDn State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

11.3.8 Link State Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

11.3.9 Device Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

11.3.10 D0 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

11.3.11 D3

11.3.12 D3

11.3.13 D State Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

11.3.14 Power Management Event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

11.3.15 Power State Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Hot

State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Cold

12. Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

12.2 System Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

12.3 EEPROM Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

12.4 Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

13. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

13.2 TAP Controller Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8

13.3 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

13.4 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

13.5 JTAG Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

13.6 JTAG Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.6.1 Register Access from JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.6.2 Write Access to Registers from the JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.6.3 Read Access to Registers from JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

13.7 Dedicated Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

13.8 Accessing SerDes TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

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14. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

14.2 PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

14.3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

14.3.1 PCI Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

14.3.2 PCI Control and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

14.3.3 PCI Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

14.3.4 PCI Miscellaneous 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

14.3.5 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

14.3.6 PCI Secondary Status and I/O Limit and Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

14.3.7 PCI Memory Base and Limit Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

14.3.8 PCI PFM Base and Limit Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

14.3.9 PCI PFM Base Upper 32 Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

14.3.10 PCI PFM Limit Upper 32 Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

14.3.11 PCI I/O Address Upper 16 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

14.3.12 PCI Capability Pointer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

14.3.13 PCI Bridge Control and Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

14.3.14 Secondary Retry Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

14.3.15 PCI Miscellaneous Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

14.3.16 PCI Miscellaneous Clock Straps Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

14.3.17 Upstream Posted Write Threshold Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

14.3.18 Completion Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

14.3.19 Clock Out Enable Function and Debug Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

14.3.20 SERRDIS_OPQEN_DTC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

14.4 Opaque Addressing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

14.4.1 Opaque Memory Lower Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

14.4.2 Opaque Memory Upper Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

14.4.3 Opaque Memory Upper Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

14.5 Upstream Non-transparent Address Remapping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

14.5.1 NTMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

14.5.2 NTMA Primary Upper Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

14.5.3 NTMA Secondary Lower Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

14.5.4 NTMA Secondary Upper Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

14.5.5 NTMA Secondary Lower Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

14.5.6 NTMA Secondary Upper Limit Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

14.6 PCI Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

14.6.1 PCI-X Capability and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.6.2 PCI-X Bridge Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

14.6.3 PCI-X Upstream Split Transaction Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

14.6.4 PCI-X Downstream Split Transaction Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

14.6.5 PCI Power Management Capability Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

14.6.6 PCI Power Management Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

14.6.7 EEPROM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

14.6.8 Secondary Bus Device Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

14.6.9 Short-term Caching Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

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14.6.10 Retry Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

14.6.11 Prefetch Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

14.7 PCIe Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

14.7.1 PCIe Capabilities Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

14.7.2 PCIe Device Capabilities Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

14.7.3 PCIe Device Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

14.7.4 PCIe Link Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

14.7.5 PCIe Link Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

14.8 Downstream Non-transparent Address Remapping Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

14.8.1 Secondary Bus Non-prefetchable Address Remap Control Register . . . . . . . . . . . . . . . . . . . . . . . . . 214

14.8.2 Secondary Bus Non-prefetchable Upper Base Address Remap Register . . . . . . . . . . . . . . . . . . . . . . 215

14.8.3 Secondary Bus Prefetchable Address Remap Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

14.8.4 Secondary Bus Prefetchable Upper Base Address Remap Register . . . . . . . . . . . . . . . . . . . . . . . . . . 216

14.8.5 Primary Bus Non-prefetchable Upper Base Address Remap Register . . . . . . . . . . . . . . . . . . . . . . . . 216

14.8.6 Primary Bus Non-prefetchable Upper Limit Remap Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

14.9 Advanced Error Reporting Capability Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

14.9.1 PCIe Advanced Error Reporting Capability Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

14.9.2 PCIe Uncorrectable Error Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

14.9.3 PCIe Uncorrectable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

14.9.4 PCIe Uncorrectable Error Severity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

14.9.5 PCIe Correctable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

14.9.6 PCIe Correctable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

14.9.7 PCIe Advanced Error Capabilities and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

14.9.8 PCIe Header Log 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

14.9.9 PCIe Header Log 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

14.9.10 PCIe Header Log 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

14.9.11 PCIe Header Log 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

14.9.12 PCIe Secondary Uncorrectable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

14.9.13 PCIe Secondary Uncorrectable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

14.9.14 PCIe Secondary Uncorrectable Error Severity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

14.9.15 PCIe Secondary Error Capabilities and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

14.9.16 PCIe Secondary Header Log 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

14.9.17 PCIe Secondary Header Log 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

14.9.18 PCIe Secondary Header Log 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

14.9.19 PCIe Secondary Header Log 4 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

14.9.20 Replay Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

14.9.21 ACK/NACK Update Latency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

14.9.22 N_FTS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

14.10 PCIe and SerDes Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

14.10.1 Base Offset Address Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

14.10.2 PCIe Per-Lane Transmit and Receive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

14.10.3 PCIe Transmit and Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

14.10.4 PCIe Output Status and Transmit Override Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

14.10.5 PCIe Receive and Output Override Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

14.10.6 PCIe Debug and Pattern Generator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

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14.10.7 PCIe Pattern Matcher Control and Error Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

14.10.8 PCIe SS Phase and Error Counter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

14.10.9 PCIe Scope Control and Frequency Integrator Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

14.10.10 PCIe Clock Module Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

14.10.11 PCIe Control and Level Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

14.10.12 PCIe Control and Level Override Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

15. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

15.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

15.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

15.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

15.4 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

15.5 DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

15.6 AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

15.6.1 PCI/X Interface AC Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

15.6.2 PCIe Differential Transmitter Output Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

15.6.3 PCIe Differential Receiver Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

15.6.4 Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

15.6.5 Boundary Scan Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

15.6.6 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

15.7 AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

16. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

16.1 Mechanical Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

16.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

16.3 Moisture Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

17. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

17.1 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

17.2 Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

A. PCIe Programmable Transmit and Receive Equalization. . . . . . . . . . . . . . . . . . 271

A.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

A.2 Transmit Drive Level and Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

A.3 Receive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

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Figures

Figure 1: Tsi384 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 2: Tsi384 Device Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 3: Motherboard Application — PC, Server, SBC, Industrial PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 4: External Storage Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 5: Server Add-in Cards for Networking and Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 6: Upstream Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 7: Downstream Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 8: Memory-mapped I/O Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 9: 64-bit Prefetchable Memory Address Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 10: I/O Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 11: ISA Mode I/O Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 12: Memory Window Remapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 13: PCIe Configuration Address Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 14: PCI Type 0 Configuration Addre ss Form at. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 15: PCI Type 1 Configuration Addre ss Form at. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 16: PCI-X Type 0 Configuration Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 17: PCI-X Type 1 Configuration Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 18: PCI/X Arbiter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 19: PCI/X Arbitration Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 20: Interrupt Handling Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 21: PCIe Flowchart of Device Error Signaling and Logging Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 22: Transaction Error Forwarding with PCIe as Originating Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 23: Transaction Error Forwarding with PCI/X as Originating Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 24: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 25: PCIe Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 26: PCI/X Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 27: Master Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 28: Slave Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 29: PCIe Link Power Management States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 30: D State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 31: EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 32: 9-bit EEPROM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 33: 16-bit EEPROM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 34: 9-bit EEPROM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 35: 16-bit EEPROM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 36: EEPROM WREN Instruction Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 37: EEPROM RDSR Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Figure 38: Read/Write Access from JTAG — Serial Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 39: Observe from JTAG — Serial Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 40: PCIe SerDes Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 41: Transmitter Eye Voltage and Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 42: Minimum Receiver Eye Timing and Voltage Compliance Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

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Figure 43: Weighing Function for RMS Phase Jitter Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 44: Input Timing Measurement Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 45: Output Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 46: PCI/X TOV (max) Rising Edge AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 47: PCI/X TOV (max) Falling Edge AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 48: PCI/X TOV (min) AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Figure 49: Mechanical Diagram 256 pin 17x17mm BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 50: Drive Strength and Equalization Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

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13

Tables

Table 1: Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 2: PCIe Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 3: PCI/X Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 4: EEPROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 5: JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 6: Power-up Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 7: Power Supply Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 8: Initial Credit Advertisement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 9: PCI Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 10: PCI-X Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 11: PCIe Transaction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 12: Transaction Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 13: Error Forwarding Requirements (Step A to Step B) for Received PCIe Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 14: Bridge Requirements for Transactions Requiring a Completion (Immediate Response) . . . . . . . . . . . . . . . . . . . . 84

Table 15: Error Forwarding Requirements for Received PCI/X Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 16: Error Forwarding Requirements for PCI Delayed Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 17: Abnormal Conditions and Tsi384’s Response to Split Completion Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 18: ECRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 19: Poisoned TLP Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 20: Malformed TLP Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 21: Link and Flow Control Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 22: Uncorrectable Data/Address/Attribute Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 23: Received Master/Target Abort Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 25: Request Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 24: Completion Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 26: Reset Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 27: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 28: PCI/X Bus Mode and Speed Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 29: Master Mode and Clock Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 30: Master Mode External Clock Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 31: Slave Mode and Clock Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 32: Slave Mode Clock Insertion Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 33: Initialization Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 34: PCIe Link States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 35: Power Management State Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 36: EEPROM Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 37: PCI Type 1 Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 38: PCI-X Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 39: Power Management Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 40: PCIe Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Table 41: Advanced Error Reporting Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 42: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

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Tables14

Table 43: SerDes Per-lane and Clock Control and Status Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Table 44: TX_LVL Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Table 45: Absolute Maximum Ratings – PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 47: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8

Table 46: Absolute Maximum Ratings – PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Table 48: Power Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

Table 49: DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Table 50: PCI/X Clock (PCI_CLK) Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Table 51: AC Specifications for PCI/X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1

Table 52: PCIe Differential Transmitter Output Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Table 53: PCIe Differential Receiver Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Table 54: Reference Clock (PCIE_REFCLK_n/p) Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Table 55: Boundary Scan Test Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Table 56: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Table 57: Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Table 58: Junction to Ambient Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Table 59: Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

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About this Document

This section discusses the following topics:

• “Scope”

• “Document Conventions”

• “Revision History”

Scope

The Tsi384 PCIe-to-PCI Bridge User Manual discusses the features, capabilities, and configuration
requirements for the Tsi384.

Document Conventions

15

This document uses the following conventions.

Non-differential Signal Notation

Non-differential signals are either active-low or active-high. An active-low signal has an active state of
logic 0 (or the lower voltage level), and is denoted by a lowercase “n”. An active-high signal has an
active state of logic 1 (or the higher voltage level), and is not denoted by a special character. The
following table illustrates the non-differential signal naming convention.

State Single-line signal Multi-line signal

Active low NAMEn NAMEn[3]

Active high NAME NAME[3]

Differential Signal Notation

Differential signals consist of pairs of complement positive and negative signals that are measured at
the same time to determine a signal’s active or inactive state (they are denoted by “_p” and “_n”,
respectively). The following table illustrates the differential signal naming convention.

State Single-line signal Multi-line signal

Inactive NAME_p = 0

Active NAME_p = 1

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NAME_n = 1

NAME_n = 0

NAME_p[3] = 0

NAME_n[3] =1

NAME_p[3] is 1
NAME_n[3] is 0

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May 5, 2014

About this Document16

Tip

Object Size Notation

•A byte is an 8-bit object.

•A word is a 16-bit object.

•A doubleword (Dword) is a 32-bit object.

Numeric Notation

• Hexadecimal numbers are denoted by the prefix 0x (for example, 0x04).

• Binary numbers are denoted by the prefix 0b (for example, 0b010).

• Registers that have multiple iterations are denoted by {x..y} in their names; where x is first register
and address, and y is the last register and address. For example, REG{0..1} indicates there are two
versions of the register at different addresses: REG0 and REG1.

Symbols

This symbol indicates a basic design concept or information considered helpful.

This symbol indicates important configuration information or suggestions.

This symbol indicates procedures or operating levels that may result in misuse or damage to
the device.

Document Status Information

• Advance – Contains information that is subject to change, and is available once prototypes are
released to customers.

• Preliminary – Contains information about a product that is near production-ready , and is revised as
required.

• Formal – Contains information about a final, customer-ready product, and is available once the
product is released to production.

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About this Document 17

Revision History

May 5, 2014, Formal

• Changed the 00110 setting to 112 from 102 for UPST_PWR_THRES in the “Upstream Post ed

Write Threshold Register”

• Updated step 3 in “Initialization”

• Added footnote H to Table 51: AC Specifications for PCI/X Interface

August 2009, Formal

This version of the document does not include any technical changes.

May 2009, Formal

• Added additional information about the TEST_BCE signal (see Table 5)

• Added missing register offset, 0x010, to the register map (Table 42)

• Revised the description of the CSR_SEL_400 bit in the “PCI Miscellaneous Clock Straps

Register”

• Changed the minimum value of the T

parameter for PCI 66 MHz to 2 ns (see Table 51)

OV1

July 2008, Formal

• Removed reference to PCIE_REXT pin because it is not applicable to the Tsi384

• Changed the Pin Type definition of various signals (see “Signal Descriptions”)

• Added Design Recommendations for Tsi384’s signals (see “Signal Descriptions”). This
information previously resided in the Tsi384 Board Design Guidelines.

• Corrected the description of the JTAG_TDO signal. Previously it indicated that the signal should
be pulled low if unused. The correct description for this signal if unused is to leave it unconnected
(see “JTAG Interface Signals”).

• Updated the “PCIe and SerDes Control and Status Registers”

• Added a new section that discusses “PCIe Programmable Transmit and Receive Equalization”

February 2008, Formal

• Added a note that explains how the EEPROM Controller handles an EEPROM byte count value
that is programmed to a non-multiple of 6 (see “System Diagram”)

• Revised the description of the “Opaque Memory Lower Register”

• Added bits 18–20 to the “PCIe Link Capabilities Register”

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About this Document18

October 2007, Formal

• Revised the description of the PWRUP_EN_ARB signal (see “Power-up Signals”)

• Corrected the name of the PCI_PCIXCAP_PU signal that was used in several figures in “PCI/X

Clocking”. This signal was previously incorrectly named S_PCIXCAP_PU.

• Added power and current characteristics (see “Power Characteristics”)

July 2007, Preliminary

• Added error handling tables for PCIe and PCI/X (see “Error Handling Tables”)

• Updated the power supply sequencing information to indicate that the Tsi384 does not have any
specific sequencing constraints (see “Power Supply Sequencing”)

• Redefined two SerDes registers (see “PCIe Debug and Pattern Generator Control Register” and

“PCIe Pattern Matcher Control and Error Register”)

April 2007, Preliminary

• Updated the description of PCI/X bus arbitration (see “PCI/X Arbitration Scheme”)

• Added a cautionary note on how to use an EEPROM with the Tsi384 (see “System Diagram”)

• Updated the description of how JTAG can provide access to the Tsi384’s registers (see “JTAG

Register Access”)

• Added a new bit, PCI_MISC_CLK_STRAPS[CSR_SEL_400], to allow configuration of the PLL
clock (see “PCI Miscellaneous Clock Straps Register”)

• Added electrical and packaging information. This information used to reside in the
Tsi384 Hardware Manual, whic h is now an obsolete document.

December 2006, Preliminary

This version includes numerous minor changes.

October 2006, Advance

This version includes numerous minor changes.

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1. Functional Overview

Topics discussed include the following:

• “Overview”

• “Features”

• “Device Architecture”

• “Typical Applications”

1.1 Overview

The IDT T s i384 is a high-performance bus bridge that connects the PC I Expr ess (PCIe) protocol to the
PCI and PCI-X bus standards (see Figure 1).

The Tsi384’s PCIe Interface is a superior performance, configurable port that supports 1, 2, or 4 lanes.
This enables the bridge to offer exceptional throughput performance of up to 1 GBps per transmit and
receive direction. The device’s PCI/X Interface can operate up to 133 MHz in PCI-X mode, or up to
66 MHz in PCI mode. This interface offers designers extensive flexibility by supporting three types of
addressing modes: transparent, opaque, and non-transparent.

19

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Figure 1: Tsi384 Block Diagram

PCI/X

Arbiter

Error

Handling

Interrupt
Handling

Clocking/

Reset

EEPROM

Controller

Power
Mgmt

JTAG

PCI/X Interface

PCIe Interface (x4)

80E1000_BK001_01 (Tsi384)

Posted

Writer
Buffer

Posted
Queue

Mux Logic

Non-

Posted

Buffer

Non­Posted
Queue

DownstreamDownstream

UpstreamUpstream

Posted

Writer
Buffer

Posted
Queue

Mux Logic

Non-

Posted

Buffer

Non­Posted
Queue

Config

Registers

1. Functional Overview20

1.2 Features

The Tsi384’s key features are listed in the following sub-sections.

1.2.1 General Features

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May 5, 2014

• Forward bridge, PCIe to PCI/X

• Single store and forward for optimal latency performance

• Supports three modes of addressing:
— Transparent: For eff icient, flow-through configurations
— Opaque: For multi-processor configurations and enhanced private device suppo rt
— Non-transparent: For address remapping of the PCIe and the PCI/PCI-X domains

• Compliant to the following specifications:
— PCI Express Base Specification (Revision 1.1)
— PCI Express-to-PCI/PCI-X Bridge Specification (Revision 1.0)
— PCI-to-PCI Bridge Specification (Revision 1.2)

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1. Functional Overview 21

— PCI Local Bus Specification (Revision 3.0)
— PCI-X Addendum to PCI Local Bus Specification (Revision 2.0) (mode 1 only)
— PCI Bus Power Management Interface Specification (Revision 1.2)

• 3.3V PCI/X I/Os

• Support for four external PCI/X bus masters through an integrated arbiter

• Support for external PCI/X bus arbiter

• Support for Masquerade mode (can overwrite vendor and device ID from EEPROM)

• JTAG IEEE 1149.1, 1149.6

• Support for D0, D3 hot, D3 cold power management states

• Packaged in 17 x 17 mm, 256-pin PBGA

1.2.2 PCIe Features

• 1, 2, or 4 lanes

• 512-byte maximum payload

• Advanced error reporting capability

• Lane reversal and lane polarity inversion

• End-to-end CRC (ECRC) check and generation

• Up to four outstanding memory reads

• Four, 128-byte read completion buffers

• ASPM L0s link state power management

• Legacy interrupt signaling

• Hot plug support

1.2.3 PCI-X Features

• 32/64-bit addressing

• 32/64-bit data bus

• 50-, 66-, 100-, and 133-MHz operation

• Up to eight outstanding memory reads

• 4-KB read completion buffer

1.2.4 PCI Features

• 32/64-bit addressing

• 32/64-bit data bus

• 25-, 33-, 50-, and 66-MHz operation

• Up to eight outstanding read requests

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• 4-KB read completion buffer

Rx PHY

SERDES

Configuration Registers

Data Link Layer

2K Repl ay buff ers

PC Ie P ri ma ry In t er f ac e

PCI /X Interface (Secondary Interface)

Tar get int erface

4

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(

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T ransac ti on Layer

Tx P H Y

SERDES

Dat a Link Layer

Tr ansac ti on Layer

orderin g

Order ing

A ddres s dec odin g

PC I / X

Arbiter

JTA G

EEPROM

CLK/
Reset

U

p

s

t

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d

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• Short-term caching support

1.3 Device Architecture

A high-level, architectural diagram of the Tsi384 is displayed in Figure 2. For more information about
data flow through the device, see “Upstream Data Path” and “Downstream Data Path”.

Figure 2: Tsi384 Device Architecture

1. Functional Overview22

Packets received on the PCIe Interface are processed by the data link layer and transaction layer, if
applicable. If a packet is destined for the transaction layer, its address is decoded and forwarded to the
appropriate destination:

• Configuration register

• Downstream posted write buffer

• Downstream read request queue

• Downstream read completion buffer

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1. Functional Overview 23

PCI/X data that is destined for the PCIe fabric are subject to PCIe ordering rules. Data is pulled from
the appropriate queue:

• Configuration register

• Upstream posted write buffer

• Upstream read request queue

• Upstream read completion buffer
PCI/X transactions that are decoded for the PCIe address space are forwarded to the appropriate queue:

• Upstream read request queue

• Upstream posted write buffer
PCI-X read completion (Tsi384 is target), from a split transaction, are also decoded and sent to the

downstream read completion buffer.
Transactions destined for downstream devices on the PCI/X bus, are subject to PCI/X ordering rules.

Data is pulled form the appropriate queue:

• Downstream posted write buffer

• Downstream read request queue
PCI-X read completion (Tsi384 is master), from a split transaction, are also ordered and pulled from

the upstream read completion buffer.
PCIe is a serialized protocol at the physical layer, and a packetized protocol at the data link layer. Each

PCIe lane operates at 2.5 Gb symbol rate, or at 2.0 Gb data rate; the difference is a result of the 8/10b
coding process. The Tsi384 uses the following processes to ensure the accurate and timely delivery of
data through the data link layer:

• Credit-based flow control – Prevents data loss and congestion

• ACK/noACK protocol and End-to-End CRC (ECRC) – Ensures reliable data delivery if bit errors
occur

• Replay buffer – Replays packets that are not acknowledged by the receiver (NAK)

In contrast, PCI/X is a parallel data interface at the physical layer. PCI is a non-packetized protocol.
When a bus master starts a read or a write transaction, it indicates only the starting transaction address
to the target, and not the size of the read or write. PCI-X is a also a parallel bus at the physical layer , but
is more accommodating to packetized data flow. For example, the length of a read or write transaction
is defined during the attribute phase on the PCI-X bus.

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1. Functional Overview24

In the case of a PCI/X write, which is initiated on the PCI/X Interface and is destined for the root
complex, the data is written into an upstream posted write buffer in the Tsi384. The end of the write
transaction is signaled by the master on the PCI/X bus. Once the write is completed the data can be
forwarded to the PCIe Interface. If the posted write buffer is about to overflow, the Tsi384 indicates a
retry/disconnect on the PCI bus. In the case of a PCI-X transaction, the Tsi384 disconnect on an
allowable disconnect boundary (ADB). Once the posted write buffer empties, the Tsi384 can accept
additional write transactions. The Tsi384 will split write transactions as required to meet PCIe
constraints: to prevent a write crossing a 4-KB boundary; if byte enables are used throughout the
transaction; or if the quantity of data exceeds the maximum payload size (see MAX_SIZE in “PCIe

Device Capabilities Register”). The upstream posted write buffer is managed as a simple FIFO.

A read initiated on the PCI bus that is decoded for an upstream target is handled as a delayed
transaction by the Tsi384. The bridge latches the read transaction and attempts to reserve buffer space
in its upstream read completion buffer. If space is successfully reserved in the buffer, the Tsi384
initiates a read on the PCIe Interface. When the read data is returned from the root comple x, it is store d
in the upstream read completion buffer. PCI-initiated reads, however, do not define the amount of data
to read. Once the master on the PCI bus retries the read transaction, the transaction is checked to
determine if the read data is returned. If it has the read data, the Tsi384 responds as the target and
transfers the read data to the PCI bus. Note the upstream read completion buffer is not a simple FIFO,
as the order that masters on the PCI bus retry is not deterministic. If the complet io n buffer becomes
empty prior to the transaction completing, the Tsi384 disconnects from the PCI bus. When the read
transaction is completed, the Tsi384 discards any prefetched data that is not used and frees up the
buffer.

A read initiated on the PCI-X bus that is decoded for an upstream target is handled as a split transaction
by the Tsi384. The bridge latches the read transaction and attempts to reserve buffer space in the
upstream read completion buffer . If space was successfully reserved in the buf fer, the T si384 initiates a
read on the PCIe Interface for the specified amount of data. When the read data is returned from the
root complex, it is stored in the upstream read completion buffer. When the Tsi384 has received
sufficient read data, the Tsi384 transfers the data to the target on the PCI-X bus.

The 512-byte data blocks in the upstream read completion buffer may be destined to different devices
on the PCI-X bus, and therefore, in different streams. A round-robin algorithm determin es which
stream is sent first. If the upstream read completion buffer is empty before the transaction completes,
the Tsi384 disconnects from the PCI-X bus on an ADB. The Tsi384 splits PCI-X read transactions as
required to meet PCIe constraints: to prevent a read crossing a 4-KB boundary; or if the quantity of
data exceeds MAX_RD_SIZE in the “PCIe Device Control and Status Register”.

A write initiated on the PCIe Interface with the target on the downstream PCI/X bus is written into the
downstream posted write buffer. The Tsi384 acts as the master for the transaction and arbitr ate s for the
PCI/X bus and initiates the write transaction. The downstream posted write buffer is managed as a
FIFO. There will always be space available in the buffer to accept packet data because of the flow
control method used by the PCIe data link layer. If the downstream posted write buffer is about to
overflow , the upstream device will be informed of this by its lack of credits and will not send any more
write data to the Tsi384.

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1. Functional Overview 25

4

A read initiated on the PCIe Interface with the target on the downstream PCI/X bus is written into the
downstream read request queue. The downstream read request queue is managed with flow control
credits to prevent overflowing. The T si384 latches the read transaction and attempts to reserve space in
the downstream read completion buffer. If space is successfully reserved in the buffer, the Tsi384 acts
as the master for the transaction and initiates a read transaction on the PCI/X bus. The read request
queue is managed using a round-robin algorithm. In the case of PCI-X, the target may respond with a
split response, which causes the Tsi384 to become the target for the read completion.

Programmable address decoders instruct the Tsi384 which transactions on the PCI/X bus to forward
upstream, and which transactions on the PCIe link to forward downstream.

1.4 Typical Applications

This section illustrates some typical applications for the Tsi384.

Figure 3: Motherboard Application — PC, Server, SBC, Industrial PC

DRAM

PCIe
Endpoints

Processor

Block

x4 x4

Tsi384

PCI-X

Tsi384

Ts i38

Device

Tsi384

PCIe

Switch

PCIe
Endpoints

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Figure 4: External Storage Application

PCI-X 133 MHz

PCI-X 133 MHz

PCIe x4

Tsi384

GbE/FC

Controller

GbE/FC

Controller

PCI 66 MHz

PCI 66 MHz

PCIe x4

Tsi384

SCSI

Controller

SCSI

Controller

IOP

DRAM

1. Functional Overview26

PCI-X

to SATA

iSCSI

GbE

with

TOE

Integrated

CPU

x4x4

Tsi384

PCI-X

to SATA

Figure 5: Server Add-in Cards for Networking and Storage

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2. Signal Descriptions

Topics discussed include the following:

• “Overview”

• “PCIe Interface Signals”

• “PCI/X Interface Signals”

• “EEPROM Interface Signals”

• “JTAG Interface Signals”

• “Power-up Signals”

• “Power Supply Signals”

2.1 Overview

27

Signals are classified according to the types defined in the following table.

Table 1: Pin Types

Pin Type Definition

3.3 OD 3.3V CMOS open-drain output

3.3 3-state 3.3V CMOS tri-state output

3.3 Bidir 3.3V CMOS bi-directional

3.3 Bidir PU 3.3V CMOS bi-directional with 265K (+/- 45K) pull-up resistor

3.3 Bidir OD 3.3V CMOS bi-directional open-drain

3.3 In 3.3V CMOS input

3.3 In PU 3.3V CMOS input with 265K (+/- 45K) pull-up resistor

3.3 Out 3.3V CMOS output

PCI/X Bidir PCI/X bi-directional

PCI/X Bidir OD PCI/X bi-directional open-drain

PCI/X In PCI/X input

PCI/X Out PCI/X output

PCI/X OD PCI/X output open-drain

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Table 1: Pin Types (Continued)

Pin Type Definition

PCIE Diff Out PCIe differential output

PCIE Diff In PCIe differential input

2.2 PCIe Interface Signals

Table 2: PCIe Interface Signals

Name Pin Type Description Design Recommendation

2. Signal Descriptions28

PCIE_PERSTn 3.3 In Master reset in:

0 = Tsi384 in reset

1 = Tsi384 in normal mode

PCIE_TXD_n[3:0]
PCIE_TXD_p[3:0]

PCIE_RXD_n[3:0]
PCIE_RXD_p[3:0]

PCIE_REFCLK_n
PCIE_REFCLK_p

PCIE_LANE_VALIDn[3

:0]

PCIE Diff Out Transmit Data. These differential pair

signals send PCIe 8b/10b encoded
symbols and an embedded clock to the
link partner.

PCIE Diff In Receive Data. These differential pair

signals receive PCIe 8b/10b encoded
symbols and an embedded clock from
the link partner.

PCIE Diff In Reference Clock. 100-MHz differential

reference clock.

3.3 out PCIe Lane Valid:

0 = Lane valid

1 = Lane invalid

Direct connect to the PERST# signal.

DC blocking capacitors must be placed
in the link between the transmitter and
the receiver. Place a 0603 or 0402

0.075uF to 0.1uF ceramic capacitor on
each TXD_n, TXD_p signal.

DC blocking capacitors must be placed
in the link between the transmitter and
the receiver; however, the DC blocking
capacitors are normally placed near the
transmitter. When designing an add-in
card, capacitors are not required on this
link. When designing a system board,
the DC blocking capacitors should be
placed near the transmitter.

Refer to the Tsi384 Board Design
Guidelines.

When connecting to LEDs, connect the
cathode on PCIE_LANE_VALIDn and
the anode to 3.3V.

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2. Signal Descriptions 29

2.3 PCI/X Interface Signals

Table 3: PCI/X Interface Signals

Name Pin Type Description Design Recommendation

PCI_ACK64n PCI/X Bidir Acknowledge 64-bit Transaction. The

bus target asserts this signal to indicate
it wants to participate in a 64-bit
transaction.

PCI_AD[63:0] PCI/X Bidir Address/Data Bus. These multiplexed

signals provide a 32/64-bit address and
64-bit data bus.

PCI_CBEn[7:0] PCI/X Bidir Command/Byte Enables. These

multiplexed signals indicate the current
transaction type.

PCI_CLK PCI/X In PCI Input Clock. This signal provides

timing for the Tsi384, either from an
external clock or from one of the
PCI_CLKO[4:0] signals (see

“Clocking”).

PCI_CLKO[4:0] PCI/X Out PCI Output Clock. PCI_CLKO[3:0] are

for driving four devices, and
PCI_CLKO[4] can feed back to
PCI_CLK to compensate for PCB track
length (see “Clocking”).

PCI_DEVSELn PCI/X Bidir Device Select. A target device asserts

this signal when it decodes its address
on the bus. The master samples the
signal at the beginning of a transaction,
and the target rescinds it at the end of
the transaction.

Pull up (8.2K) to 3.3V.

Pull up (8.2K) to 3.3V on
PCI_AD[63:32].

Pull up (8.2K) to 3.3V on
PCI_CBE[7:4].

None.

Point-to-point connection to PCI/X
device. IDT recommends a 33 Ohm
series termination resistor.

Pull up (8.2K) to 3.3V.

a

a

a

a

PCI_FRAMEn PCI/X Bidir Frame. The current initiator drives this

signal to indicate the start and duration
of a transaction, and the bus target
samples it. The bus master rescinds the
signal at the end of the transaction.

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Pull up (8.2K) to 3.3V.

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May 5, 2014

Table 3: PCI/X Interface Signals (Continued)

Name Pin Type Description Design Recommendation

2. Signal Descriptions30

PCI_GNTn[3:0] PCI/X Bidir /

PCI/X Out

PCI_INTDn PCI/X In Interrupt D. Pull up (2.4K) to 3.3V.

PCI_INTCn PCI/X In Interrupt C. Pull up (2.4K) to 3.3V.

PCI_INTBn PCI/X In Interrupt B. Pull up (2.4K) to 3.3V.

PCI_INTAn PCI/X In Interrupt A. Pull up (2.4K) to 3.3V.

PCI_IRDYn PCI/X Bidir Initiator Ready. The bus master asserts

Bus Grant. The Tsi384 uses these
multifunction signals to grant access to
the PCI/X bus; however, they are used
differently depending on whether or not
the Tsi384 PCI/X arbiter is used. If the
arbiter is used, then PCI_GNTn[3:0] are
outputs used by the Tsi384 to grant
access to the bus (see “PCI/X

Arbitration”).

If an external arbiter is used,
PCI_GNTn[0] is an input that is driven
by the arbiter to grant the Tsi384 access
to the bus. The remaining pins,
PCI_GNTn[3:1], remain as outputs.

The input/output mode is controlled by
the PWRUP_EN_ARB pin (see

“Power-up Signals”).

this signal to indicate it is ready to
complete the current transaction.

PCI_GNTn[3:0] outputs connect directly
to the PCI device’s PCI_GNTn inputs.
Pull ups are not required on unused
outputs.

Pull up (8.2K) to 3.3V.

PCI_M66EN PCI/X In 66-MHz Enable. This signal enables the

PCI Interface for 66-MHz operation.

0 = 33-MHz operation

1 = 66-MHz operation

This signal is ignored in PCI-X mode.
PCI_M66EN must be stable and valid
around the rising edge of
PCIE_PERSTn (see “Reset”).

PCI_PAR PCI/X Bidir Parity. This signal carries even parity

across PCI_AD[31:0] and
PCI_CBEn[3:0]. The bus master
asserts this signal for the address and
write data phases. The bus target
asserts it for read data phases.

Tsi384 User Manual
May 5, 2014

Em

bedded designs

Pull down for 33 MHz and slower
operation. Pull up for greater than
33-MHz operation.

Bused designs using PCI/X slots for
add- in cards

Place a pull-up resistor (~5K to 10K) on
M66EN and route the signal from slot to
slot.

No pull-up or pull-down resistor is
required.

b

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