IDT Tsi381, Tsi382 LQFP, PEB383 (QFN) User Manual
®
Tsi381
™
Evaluation Board User Manual
60E2000_MA001_03
September 2009
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
©2009 Integrated Device Technology, Inc.
Printed in U.S.A.
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and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
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Contents
About this Document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Related Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1. Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.2 IDSEL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.3 Interrupt Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.4 Pull-up Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 PCIe Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.1 Power Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.4 System Power Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.5 PCI Vaux (PCI Auxiliary) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.1 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.2 System Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6 Other Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6.1 JTAG Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6.2 EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6.3 GPIO Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.7 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.8 Logic Analyzer Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
2. Configurable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.1 DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Shunt Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.1 J6 Shunt Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2.2 J21 Shunt Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Debug Headers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.1 J22 Tsi381 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.2 J23 Logic Analyzer PADs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.4 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4.1 J1, J2, J36, J37 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.4.2 J3 ATX Power Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Contents4
2.4.3 P1 x1 PCIe Finger Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Tsi381 Evaluation Board User Manual
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About this Document
This document describes how to test the key features of the Tsi381 using the Tsi381 evaluation board.
It can be used in conjunction with the Tsi381 Evaluation Board Schematics.
Related Information
• Tsi381 User Manual
• Tsi381 Evaluation Board Schematics
• Tsi381 Board Design Guidelines
• PCI Express Base Specification (Revision 1.1)
• PCI Express CEM Specification (Revision 1.1)
• PCI Express-to-PCI/PCI-X Bridge Specification (Revision 1.0)
Acronyms
5
Term Definition
PCIe PCI Express
SerDes Serial/De-serializer
Revision History
60E2000_MA001_03, Formal, September 2009
This document was rebranded as IDT. It does not include any technical changes.
60E2000_MA001_02, Formal, September 2007
Added a new section that discusses “PCI Vaux (PCI Auxiliary) Support”.
60E2000_MA001_01, Formal, August 2007
This is the first version of the Tsi382 PCIe-to-PCI Bridge User Manual.
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About this Document6
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1. Board Design
Topics discussed include the following:
• “Overview” on page 7
• “PCI Interface” on page 9
• “PCIe Interface” on page 10
• “Power Management” on page 10
• “Clock Management” on page 14
• “Other Interfaces” on page 15
• “Hardware Reset” on page 16
• “Logic Analyzer Connectivity” on page 17
7
1.1 Overview
The key features of the Tsi381 evaluation board include the following (see also Figure 1):
• Single x1 lane, 2.5 Gbps PCIe 1.1 compatible riser card (extended height form factor)
• Four PCI slots
• 32-bit PCI bus, 25–66 MHz operation
• PCI power support through system or external supply
• PCIe compliance/debugging test points
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Figure 1: Evaluation Board Block Diagram
EEPROM
Tsi381
3.3V PCI 32-bit Connector
Slot 0
PCI
Power
Management
PCI Express Card Edge X1
PCIe
LA Probe
JTAG
Header
ATX Connectors
EEPROM
1x SerDes SMA
Points
SerDes Path
Resistor Select
Clock
Management
3.3V PCI 32-bit Connector
Slot 1
3.3V PCI 32-bit Connector
Slot 2
3.3V PCI 32-bit Connector
Slot 3
GPIO
GPIO
1. Board Design8
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1. Board Design 9
1.2 PCI Interface
1.2.1 Overview
The PCI Interface is implemented on the board with four slots, in which one is an R/A mounted
connector on the top of the board. All PCI connectors are compliant with the PCI 3.0 specification.
Appropriate clearance is provided such that up to four PCI cards can be inserted for testing while the
board is in an open-chassis standard ATX case.
The PCI Interface supports four slots operating at 25, 33, 50, or 66 MHz.
1.2.2 IDSEL Signals
IDSEL signals are connected in the following order:
• Slot 0 – R/A connector top slot: 150 ohms to AD16 (Device 0)
• Slot 1 – 150 ohms to AD17 (Device 1)
• Slot 2 – 150 ohms to AD19 (Device 3)
• Slot 3 – 150 ohms AD18 (Device 2)
1.2.3 Interrupt Signals
The PCI interrupt signals are connected to the slots as shown in the following table.
Table 1: PCI Interrupt Routing
Tsi381 Slot 0 Slot 1 Slot 3 Slot 4
AABDC
BBCAD
CCDBA
DDACB
1.2.4 Pull-up Signals
The following pull-ups are added to the PCI bus, in which a value of 8.2Kohm is used.
Table 2: PCI Pull-up Signals
Signal Description
PCI_REQ#[0:3] Bus request
PCI_GNT#[0:3] Bus grant
PCI_FRAME# Control signal
PCI_IRDY#, PCI_TRDY# Control signal
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Table 2: PCI Pull-up Signals (Continued)
Signal Description
PCI_STOP# Control signal
PCI_SERR# System error
PCI_PERR# Parity error
PCI_DEVSEL# Device select line
PCI_INT#[A:D] Interrupt line
PCI_PME# PCI Power Management Event occurred
1.3 PCIe Interface
The Tsi381 evaluation board implements a single lane PCIe Interface. It is designed to connect to a
PCIe system with a standard x1 finger connector. The system must provide the REFCLK and PERSTN
signals. The PCIe Interface has the following design elements:
1. Board Design10
• Supports Hot insertion and removal
• Mid-bus logic analyzer pads for PCIe RXD/TXD signal probing
• AC coupling on the TXD lanes
• JTAG TDI - TDO loopback for chain continuity
1.4 Power Management
1.4.1 Power Regulation
The evaluation board’s power regulation is implemented as follows:
• Digital 3.3V power supply available from DC/DC regulator or ATX supply
• Digital 1.2V switching regulator
• PCIe supplies filtered using EMI ferrite networks
To support PCI cards, the following additional power resources are included:
• 12V to 5V DC/DC converter
• 12V to 3.3V DC/DC converter
• External power connectors – ATX 20-pin connector for supplying all power from an ATX power
supply
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1. Board Design 11
1.4.2 Power Requirements
The power requirements and implementation for the Tsi381 is as follows.
Table 3: Tsi381 Power Requirements
Supply Name Symbol Supplied Source
Device Core 1.2V_384 DC/DC switching regulator w/Enable pin
PCIe 1.2V Core 1.2V_A_384 Passive Filter
PCI 3.3V supply 3.3V_384 Power switch w optional Ferrite filter to reduce
EMI/noise from PCI environment
PCIe 3.3V supply 3.3V_A_384 Passive Filter
The target power draw of the Tsi381 is a maximum of 1W, all supplies combined. The supplies to the
Tsi381 are controlled during ramp up using enable pins on regulators and switches.
1.4.2.1 PCIe
The PCIe CEM Specification 1.1 defines power limits on PCIe slots according to the number of lanes
available on a card. Power rules regarding x1 PCIe slots are a maximum of 25W slot. Current limits are
included in Table 4.
Table 4: PCIe Connector Current Limits
Rail Current
3.3V 3A
12V 2.1A
The usage of the 12V supply provides access to the full 25W available from the system to the board.
The PCIe pinout design includes more 1 2V power pi ns as it allows more power -per -pin capability. The
evaluation board regulates all power from the 12V system rail; however, 3.3V from the system remains
unused.
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1.4.2.2 PCI
The PCISIG defines the power rules regarding PCI cards as a maximum of 25 Watts per card (All
power rails combined power draw). The individual current limits on voltage rails are included in
Table 5.
Table 5: PCI Connector Current Limits
It is not possible to provide the full power required to the PCI bus without violating the specification
while drawing power from only a x1 PCIe system. Up to 23W not including regulator efficiency losses
can be made available. The evaluation board provides the power requirements in one of two ways
depending on the application:
1. Board Design12
Rail Current
3.3V 7.6a
5V 5a
-12V 100ma
12V 500ma
• PCIe system power
• ATX System connector
The following conditions summarize the power available for a single PCI card without external supply.
An efficiency of 85% is taken into account for switching regulators. These limits can be exceeded in
cases where the system can provide more than the suggested limit, which is usually only implemented
in hot swap systems.
Table 6: PCI Connector Current Limit with No External Supply
Rail Supplying Topology Current (Maximum)
3.3V 12V to 3.3V regulator 6A
12V 12V directly 500mA
-12V N/A N/A
5V 12V to 5V regulator 4A
For additional slots, or in cases where the system cannot supply enough power, a separate ATX power
connector is used to power the card. The evaluation board senses the presence of this supply, and
disables the slave PCIe slot power. For the case of a separate external ATX supply, all four slots are
provided with the required power.
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