IDT Tsi350A User Manual

®

Tsi350A™ PCI-to-PCI Bridge

User Manual

80D5000_MA001_08

September 5, 2009

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: [phone] • [phone] • FAX: [phone]

©2009 Integrated Device Technology, Inc.

Printed in U.S.A.

Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

GENERAL DISCLAIMER

Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely
at your own risk. IDT MAKES NO REPRESENT ATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITABILITY
OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICU­LAR PURPOSE, OR NON-INFRINGEMENT. FURTHER, IDT MAKES NO REPRESENT ATIONS OR WARRANTIES AS TO THE TRUTH, ACCURACY OR COMPLETENESS
OF ANY STATEMENTS, INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR
THAT IS CONTAINED ON ANY IDT INTERNET SITE. IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, I NCIDENTAL, INDIRECT, PUNITIVE OR
SPECIAL DAMAGES, HOWEVER THEY MAY ARIS E, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code
examples also may be subject to United States export control laws and may be subject to the export or import laws of other countries and it is your responsibility to comply with
any applicable laws or regulations.

Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.

IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

CODE DISCLAIMER

LIFE SUPPORT POLICY

About this Document

This section discusses the following topics:

• “Scope” on page 3

• “Document Conventions” on page 3

• “Revision History” on page 4

Scope

The Tsi350A PCI-to-PCI Bridge User Manual discusses the features, capabilities, and configuration
requirements for the Tsi350A. It is intended for hardware and software engineers who are designing
system interconnect applications with the device.

Document Conventions

3

This document uses the following conventions.

Non-differential Signal Notation

Non-differential signals are either active-low or active-high. An active-low signal has an active state of
logic 0 (or the lower voltage level), and is denoted by a lowercase “b”. An active-high signal has an
active state of logic 1 (or the higher voltage level), and is not denoted by a special character. The
following table illustrates the non-differential signal naming convention.

State Single-line signal Multi-line signal

Active low NAME_b NAMEn[3]

Active high NAME NAME[3]

Object Size Notation

•A byte is an 8-bit object.

•A word is a 16-bit object.

•A doubleword (Dword) is a 32-bit object.

Numeric Notation

• Hexadecimal numbers are denoted by the prefix 0x (for example, 0x04).

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Tip

• Binary numbers are denoted by the prefix 0b (for example, 0b010).

• Registers that have multiple iterations ar e denoted by {x..y} in their names; where x is first register
and address, and y is the last register and address. For example, REG{0..1} indicates there are two
versions of the register at different addresses: REG0 and REG1.

Symbols

This symbol indicates a basic design concept or information considered helpful.

This symbol indicates important configuration information or suggestions.

This symbol indicates procedures or operating levels that may result in misuse or damage to
the device.

Document Status Information

• Advance – Contains information that is subject to change, and is available once prototypes are
released to customers.

• Preliminary – Contains information about a product that is near production-ready, and is revised as
required.

• Formal – Contains information about a final, customer-ready product, and is available once the
product is released to production.

Revision History

80D5000_MA001_08, Formal, September 2009

This document was rebranded as IDT. It does not include any technical changes.

80D5000_MA001_07, Formal, April 2008

This document supports the production version of the Tsi350A. The asynchronous mode functionality
was removed from this document. Information has been removed from “Secondary Clock Outputs” on

page 84 and pin 52 in “208-pin PQFP Pin List” on page 1 04 was changed from ASYNC_MODE to

VSS.

80D5000_MA001_06, Formal, January 2008

This document supported the production version of the Tsi350A. The Tsi350A is a performance
enhancement of the Tsi350 and there are no functional changes between the devices. All technical
information in this document applies to both the Tsi350 and the Tsi350A.

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About this Document 5

80D5000_MA001_05, Formal, August 2007

The changes to this document were minor and include register address clarifications in the register
chapter and a compliance list added to the overview chapter.

80D5000_MA001_04, Formal, March 2007

The following chapters were extensively edited:

• “Signals and Pinout” on page 93

• “Electrical Characteristics” on page 119

• “Package Information” on page 169

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Contents

About this Document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1. Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.1 Overview of the Tsi350A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.1.2 Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.2.1 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.2.2 JTAG Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.2.3 Hot Swap Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4 Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4.1 Posted Write Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.4.2 Delayed Transaction Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.4.3 Read Data Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7

2. PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.1 Transaction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.2 Transaction Phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2.1 Address Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.2.2 Data Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3 Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3.1 Posted Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3.2 Memory Write and Invalidate Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.3.3 Delayed Write Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.3.4 Write Transaction Address Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.3.5 Buffering Multiple Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.4 Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.4.1 Calculating the Prefetch Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.4.2 Prefetchable Read Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.4.3 Non-Prefetchable Read Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.4.4 Read Prefetch Address Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.4.5 Delayed Read Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.5 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.5.1 Type 0 Access to Tsi350A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.5.2 Type 1 to Type 0 Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.5.3 Type 1 to Type 1 Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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2.6 Transaction Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.6.1 Master Termination Initiated by Tsi350A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.6.2 Master Abort Received by Tsi350A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.6.3 Target Termination Received by Tsi350A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.6.4 Target Termination Initiated by Tsi350A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3. Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

3.1 Overview of Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2 Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.3 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.3.1 Base and Limit Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.3.2 ISA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.4 Memory Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.4.1 Memory-Mapped I/O Base and Limit Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.4.2 Prefetchable Memory Base and Limit Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.4.3 Prefetchable Memory 64-Bit Addressing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.5 VGA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.5.1 VGA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.5.2 VGA Snoop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4. Transaction Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

4.2 Transaction Governed by Ordering Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.3 General Ordering Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.3.1 Ordering Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5. Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

5.2 Address Parity Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.3 Data Parity Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3.1 Configuration Write Transactions to Tsi350A Configuration Space. . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3.2 Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3.3 Delayed Write Transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.3.4 Posted Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.4 System Error (SERR_b) Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6. Exclusive Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

6.1 Concurrent Locks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.2 Acquiring Exclusive Access Across the Tsi350A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.3 Ending Exclusive Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7. PCI Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.2 Primary PCI Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.3 Secondary PCI Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.3.1 Secondary Bus Arbitration Using the Internal Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.3.2 Secondary Bus Arbitration Using an External Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.4 Bus Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

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8. General Purpose I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.2 GPIO Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3 Secondary Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

8.4 Live Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

8.5 CompactPCI Hot-swap Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9. Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.2 Primary and Secondary Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.2.1 Synchronous Secondary Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.2.2 Asynchronous Secondary Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.3 Secondary Clock Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9.3.1 Running the Secondary Clock Faster than the Primary Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

10. PCI Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

11. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.1 Primary Interface Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.2 Secondary Interface Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

11.3 Chip Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

12. JTAG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.2 JTAG Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

12.3 Test Access Port (TAP) Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.3.1 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.3.2 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12.3.3 Boundary-Scan Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

12.4 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

13. Signals and Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

13.2 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13.2.1 Primary PCI Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

13.2.2 Secondary PCI Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

13.2.3 Secondary Bus Arbitration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

13.2.4 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

13.2.5 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.2.6 Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

13.2.7 JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.2.8 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.3.1 208-pin PQFP Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.3.2 256-pin PBGA Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

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14. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

14.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

14.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

14.3 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

14.4 Power Supply Sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

14.5 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

14.6 AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

15. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

15.1.1 Reserved Register Addresses and Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

15.2 PCI-to-PCI Bridge Standard Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 8

15.2.1 Vendor ID Register—Offset 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

15.2.2 Device ID Register—Offset 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

15.2.3 Primary Command Register—Offset 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

15.2.4 Primary Status Register—Offset 0x04. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

15.2.5 Revision ID Register—Offset 0x08. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

15.2.6 Programming Interface Register—Offset 0x08. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

15.2.7 Subclass Code Register—Offset 0x08. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

15.2.8 Base Class Code Register—Offset 0x08. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

15.2.9 Cache Line Size Register—Offset 0x0C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15.2.10 Primary Latency Timer Register—Offset 0x0C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15.2.11 Header Type Register—Offset 0x0C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15.2.12 Primary Bus Number Register—Offset 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

15.2.13 Secondary Bus Number Register—Offset 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

15.2.14 Subordinate Bus Number Register—Offset 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

15.2.15 Secondary Latency Timer Register—Offset 0x18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

15.2.16 I/O Base Address Register—Offset 0x1C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

15.2.17 I/O Limit Address Register—Offset 0x1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

15.2.18 Secondary Status Register—Offset 0x1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

15.2.19 Memory Base Address Register—Offset 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

15.2.20 Memory Limit Address Register—Offset 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

15.2.21 Prefetchable Memory Base Address Register—Offset 0x24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

15.2.22 Prefetchable Memory Limit Address Register—Offset 0x24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

15.2.23 Prefetchable Memory Base Address Upper 32 Bits Register—Offset 0x28. . . . . . . . . . . . . . . . . . . . 143

15.2.24 Prefetchable Memory Limit Address Upper 32 Bits Register—Offset 0x2C . . . . . . . . . . . . . . . . . . . 144

15.2.25 I/O Base Address Upper 16 Bits Register—Offset 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

15.2.26 I/O Limit Address Upper 16 Bits Register—Offset 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

15.2.27 ECP Pointer Register—Offset 0x34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

15.2.28 Interrupt Pin Register—Offset 0x3C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

15.2.29 Bridge Control Register—Offset 0x3C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

15.3 Device-Specific Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

15.3.1 Chip Control Register—Offset 0x40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

15.3.2 Diagnostic Control Register—Offset 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

15.3.3 Arbiter Control Register—Offset 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

15.3.4 Read Transaction Control Register— Offset 0x44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

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15.3.5 P_SERR_b Event Disable Register—Offset 0x64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

15.3.6 GPIO Output Data Register—Offset 0x64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15.3.7 GPIO Output Enable Control Register—Offset 0x64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

15.3.8 GPIO Input Data Register—Offset 0x64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

15.3.9 Secondary Clock Control Register—Offset 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

15.3.10 P_SERR_b Status Register—Offset 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

15.3.11 Capability ID Register—Offset 0xDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

15.3.12 Next Item Pointer Register—Offset 0xDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

15.3.13 Power Management Capabilities Register—Offset 0xDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

15.3.14 Power Management Control and Status Register—Offset 0xE0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

15.3.15 PPB Support Extensions Registers—Offset 0xE2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

15.3.16 Data Register—Offset 0xE3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

15.3.17 HS Capability ID Register— Offset 0xE4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

15.3.18 HS Next Item Pointer Register— Offset 0xE5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

15.3.19 HS Control Status Register— Offset 0xE6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

A. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

A.1 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

A.1.1 208-pin PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

A.1.2 256-pin PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

A.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

A.2.1 Junction-to-Ambient Thermal Characteristics (Theta ja) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

A.2.2 System-level Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

A.2.3 Example on Thermal Data Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

B. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

B.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

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Figures

Figure 1: Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2: System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3: Tsi350A Downstream Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4: Type 0 Configuration Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 5: Type 1 Configuration Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 6: Clock Mask Load and Shift Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 7: PCI Signal Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 8: 208-pin PQFP Package Diagram - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 9: 208-pin PQFP Package Diagram - Side View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 10: 208-pin PQFP Package Diagram - Side View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 11: 256-pin PBGA Package Diagram - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 12: 256-pin PBGA Package Diagram - Bottom View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 13: 256-pin PBGA Package Diagram - Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

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Tables

Table 1: Tsi350A PCI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 2: Write Transaction Address Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 3: Read Transaction Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 4: Read Prefetch Address Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 5: Device Number to IDSEL S_AD Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 6: Tsi350A Response to Delayed Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 7: Tsi350A Response to Posted Write Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 8: Tsi350A Response to Delayed Read Target Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 9: Summary of Transaction Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 10: Clock Mask Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 11: Tsi350A Hot-Swap Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 12: Tsi350A S_CLK_O clock outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 13: Power Management Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 14: JTAG Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 15: JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 16: Tsi350A Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 17: Tsi350A Signal Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 18: Primary PCI Bus Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 19: Secondary PCI Bus Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 20: Secondary PCI Bus Arbitration Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 21: Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 22: Tsi350A Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 23: Tsi350A Miscellaneous Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 24: JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 25: Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 26: Tsi350A 208 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 27: Tsi350A 256 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 28: Tsi350A 256 Pin List - Power, Ground, and Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 29: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 30: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 31: Power Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 32: Tsi350A DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 33: 33 MHz PCI Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 34: 66 MHz PCI Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 35: Tsi350A Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 36: Register Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 37: PQFP Symbol Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Table 38: Thermal Characteristics of the Tsi35 0A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 39: Simulated Junction to Ambient Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 40: Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

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1. Functional Overview

This chapter describes the main features and functions of the Tsi350A. The following topics are
discussed:

• “Overview of the Tsi350A” on page 17

• “Functional Description” on page 20

• “Architecture” on page 22

• “Data Path” on page 22

1.1 Overview of the Tsi350A

The IDT Tsi350A is a PCI-to-PCI bridge that is fully compliant with PCI Local Bus Specification,
Revision 2.3. The Ts i350A has sufficient clock and arbitration pins to support nine PCI bus master

devices directly on its secondary interface.

17

The Tsi350A allows the two PCI buses to operate concurrently. This means that a master and a target
on the same PCI bus can communicate while the other PCI bus is busy. This traffic isolation may
increase system performance in applications such as multimedia.

The Tsi350A makes it possible to extend a sy stem ’s load capability limit beyond that of a single PCI
bus by allowing motherboard designers to add more PCI devices or more PCI option card slots than a
single PCI bus can support.

The Tsi350A has two identical PCI Interfaces that each handle PCI transactions for its respective bus,
and, depending on the type of transaction, ca n act as either a bus master or a bus slave. These interfaces
transfer data and control information flowing to and from the blocks shown in Figure 1.

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Figure 1: Block Diagram

Secondary PCI Bus Interface

Primary PCI Bus Interface

Secondary

Bus Arbiter

Address
Decoder

Posted

Write

Buffer

Posted
Queue

Non­Posted
Buffer

Non­Posted
Queue

Mux

Logic

Posted

Write

Buffer

Posted
Queue

Non-

Posted

Buffer

Non­Posted
Queue

Mux

Logic

66 MHz / 32-bit

PCI Bus

66 MHz / 32-bit
PCI Bus

80D5000_BK001_02

JTAG

Hot

Swap

Clocking/

Reset

IEEE1149.1

Boundary Scan

1. Functional Overview > Overview of the Tsi350A18

Option card designers can use Tsi350A to implement multiple-device PCI option cards. Without a
PCI-to- PCI bridge, PCI loading rules would limit option cards to one device. The PCI Local Bus
Specification loading rules limit PCI option cards to a single connection per PCI signal in the option
card connector. The Tsi350A overcomes this restriction by providing, on the option card, an
independent PCI bus to which up to nine devices can be attached.

Figure 2 shows how the Tsi350A enables the design of a multi-component option card or expand

existing PCI buses.

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1. Functional Overview > Overview of the Tsi350A 19

PCI Bus

80D5000_TA001_02

PCI

Device

PCI

Device

PCI

Device

PCI

Device

PCI

Device

PCI

Device

Tsi350A

Figure 2: System Block Diagram

1.1.1 Features

• Industry-standard 32-bit, 66-MHz PCI bridge

•Fully PCI Local Bus Specification, Revision 2.3 compliant

• Supports up to nine PCI bus masters on the secondary interface

• Ten independent secondary clock outputs to the secondary slots

• Primary and secondary interfaces can be operated using asynchronous clocks

• Secondary clock can either be derived from the input primary clock or supplied by an external
clock source

• Secondary clocks can be masked through the GPIO interface during power up

• Supports four independent delayed transactions in each direction

• Supports up to nine secondary requests and grants

• External arbiter support on the secondary bus

• Supports CompactPCI Hot Swap functionality

• C I Power management with D3Hot support with option to disable clocks during D3Hot state

• Supports Bus Locking mechanism

• VGA/Palette memory and I/O decoding options

• Optional non-posted entry flush upon posted writes traveling the same direction

• Compatible with existing solutions from Intel, TI, PLX, and Peri com

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1.1.2 Compliance

• PCI-to-PCI Bridge Architecture Specification (Revision 1.1)

• PCI Local Bus Specification (Revision 2.3)

• PCI bus Power Management Interface Specification (Revision 1.1)

• Advanced Configuration Power Interface (ACPI)

• PICMG CompactPCI Hot-Swap Specification (Revision 2.0)

1.2 Functional Description

This chapter outlines functionality of various interfaces and major blocks.

1.2.1 PCI Interface

Tsi350A has two PCI interfaces, one on the primary side and another on the secondary side. These
interfaces transfer data/control information to and from BLU (Buffer Logic Unit).

1.2.1.1 Posted Write Buffer

1. Functional Overview > Functional Description20

This buffer is used as temporary storage for posted memory write data flowing from one interface to
the other. Each posted buffer has a capacity of 128 bytes. The amount of buffer locations allotted for a
transaction is dynamic. A single transaction can utilize from one memory location (4 bytes) to 32
memory locations (128 bytes) as needed.

1.2.1.2 Posted Write Queue

Posted Write Queue is used to store control information related to the posted write transaction flowing
from one interface to the other. Each Posted Write Queue is a 4-entry FIFO, providing four active
posted write transactions in each direction. Data related to each entry is stored in the Posted Write
Buffer. Posted Write Queue will accept entry from external master only when at least one entry is free
and at least one Q-word space is available in Posted Write Buffer.

1.2.1.3 Non-Posted Buffer

Non-Posted Buffer is used to hold data for read transactions. Each Non-Posted Buffer contains 128
bytes of buffer space. The amount of buffer locations allotted for a transaction is dynamic. A single
transaction can utilize from one memory location (4 bytes) to 32 memory locations (128 bytes) as
needed. Tsi350A will start giving data on originating bus once the first four locations of the buffer are
filled or the transaction is completed on the target bus.

1.2.1.4 Non-Posted Queue

Non-Posted Queue is used to store the control information related to the all non-posted transactions.
Each Non-Posted Queue is a 4-entry FIFO, providing 4-active non-posted transactions in each
direction. Data related to each entry is stored in the Non-Posted Buffer. The Non-Posted Queue will
accept a transaction from external master only when at least one entry is free.

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1. Functional Overview > Functional Description 21

1.2.1.5 Mux Logic

This module arbitrates the transactions from the Posted Queue and Non-Posted Queue.

1.2.1.6 Configuration Space

The configuration registers help the system software to configure behavior of the bridge. The bridge
has Type 01 configuration header support as per the specification. All of these registers function
exactly as specified in the PCI to PCI Bridge Architectur e Specification, Revision 1.2. The
configuration space can be accessed only from primary bus interface. Tsi350A implements device
specific configuration registers to enable software to program the bridge features.

1.2.1.7 Address Decoding Logic

Tsi350A operates in transparent mode. In transparent mode I/O, memory, pre-fetchable memory base
and limit, and optional Base Address Registers 0 and 1 define address ranges for the devices residing
on secondary bus. All other addresses are assumed to res ide on the primary bus. Inverse address
decoding determines when to forward a transaction up-stream.

1.2.1.8 Secondary Bus Arbiter

Tsi350A is designed with an internal arbiter that can be enabled through input strap S_CFN_b. The
arbiter provides bus arbitration for nine additional masters. The arbiter can be programmed to
enable/disable and prioritize each request independently through software.

Tsi350A implements 2-level arbitration scheme. The requesters are divided into 2 groups, a high
priority group and a low priority group. Each master can be assigned to either high or low priority
group through the configuration register.

1.2.2 JTAG Controller

Tsi350A provides a JTAG test port that is compliant with IEEE Standard 1149.1, IEEE Standard Test
Access Port and Boundary-Scan Architectur e, to facilitate card and board testing using boundary scan

techniques. This function consists of five-signal test port interface with signals TCK, TDI, TDO, TMS,
and TRST.

1.2.3 Hot Swap Interface

T si350A is designed with an interface for Hot Swap support. This allows the user to insert or extract the
bridge card without powering down the system. During insertion and extraction process, the bridge
indicates to system software about the Hot Swap event by driving HS_EN UM_b. It also provides a
visual indication to the user through the HS_LED signal.

Hot-Swap support is implemented in the 208-pin PQFP package only. The 256-pin PBGA
package does not support Hot Swap.

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1.3 Architecture

Tsi350A internal architecture consists of the following major functions:

• PCI interface control logic for the primary and secondary PCI interfaces

• Data path and data path control logic

• Configuration register and co nfiguration control logic

• Secondary bus arbiter

1.4 Data Path

The data path consists of a primary-to-secondary data path for transactions and data flowing in the
downstream direction and a secondary-to-primary data path for transactions and data flowing in the
upstream direction.

Both data paths have the following queues:

• Posted write queue

• Delayed transaction queue

1. Functional Overview > Architecture22

• Read data queue
To prevent deadlocks and to maintain da ta coherency, a set of ordering rules is imposed on the

forwarding of posted and delayed transactions across Tsi350A. The queue structure, along with the
order in which the transactions in the queues are initiated and completed, supports these ordering
requirements.

Figure 3 shows the Tsi350A data path for the downstream direction, and the following sections

describe the data path queues.

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1. Functional Overview > Data Path 23

Figure 3: Tsi350A Downstream Data Path

1.4.1 Posted Write Queue

The posted write queue contains the address and data of memory write transactions targeted for the
opposite interface. The posted write transaction can consist of an arbitrary number of data phases,
subject to the amount of space in the queue and disconnect boundaries. The posted write queue can
contain multiple posted write transactions. The number of posted write transactions that can be queued
at one time is dependent upon their burst size. The posted write queue consists of 128 bytes in each
direction.

1.4.2 Delayed Transaction Queue

For a delayed write request transaction, the delayed transaction queue contains the address, bus
command, 1 Dword of write data, byte enable bits, and parity. When the delayed write transaction is
completed on the target bus, the write completion status is added to the corresponding entry. For a
delayed read request tran sa ctio n, the de laye d tr ansac tion queue c ontains the address and bus c ommand

- and for non-prefetchable read transactions - the byte enable bits. When the delayed read transaction is

completed on the target bus, the read completion status corresponding to that transaction is added to the
delayed request entry. Read data is placed in the read data queue. The delayed transaction queue can
hold up to four transactions (any combination of read and write transactions).

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1.4.3 Read Data Queue

The read data queue contains read data transferred from the target during a delayed read completion.
Read data travels in the opposite direction of the transaction. The primary-to secondary read data queue
contains read data corresponding to a delayed read transaction residing in the secondary-to-primary
delayed transaction queue. The secondary-to-primary read data queue contains read data corresponding
to a delayed read transaction in the primary-to-secondary delayed transaction queue. The amount of
read data per transaction depends on the amount of space in the queue and disconnect boundaries. Read
data for up to four transactions, subject to the burst size of the read transactions and available queue
space, can be stored. The read data queue for Tsi350A consists of 128 bytes in each direction.

1. Functional Overview > Data Path24

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2. PCI Interface

This chapter discusses the following topics:

• “Transaction Types” on page 25

• “Transaction Phases” on page 27

• “Write Transactions” on page 28

• “Read Transactions” on page 32

• “Configuration Transactions” on page 37

• “Transaction Termination” on page 42

2.1 Transaction Types

This section summarizes the PCI transactions performed by Tsi350A.

25

Table 1 lists the command code and name of each PCI transaction. The Master and Target columns

indicate Tsi350A support for each transaction when Tsi350A initiates transactions as a master, on the
primary bus and on the secondary bus, and when Tsi350A responds to transactions as a target, on the
primary bus and on the secondary bus.

As indicated in Table 1, the following PCI commands are not supported by Tsi350A:

• Tsi350A never initiates a PCI transaction with a reserved command code and, as a target Tsi350A
ignores reserved command codes.

• Tsi350A never initiates an interrupt acknowledge transaction and, as a target, Tsi350A ignores
interrupt acknowledge transactions. Interrupt acknowledge transactions are expected to reside
entirely on the primary PCI bus closest to the host bridge.

• Tsi350A does not respond to special cycle transactions. Tsi350A cannot guarantee delivery of a
special cycle transaction to downstream buses because of the broadcast nature of the special cycle
command and the inability to control the transaction as a target. To generate special cycle
transactions on other PCI buses, either upstream or downstream, a Type 1 configuration command
must be used.

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• Tsi350A does not generate Type 0 configuration transactions on the primary interface, nor does it
respond to Type 0 configuration transactions on the secondary PCI interface. The PCI-to-PCI
Bridge Architecture Specification does not support configuration from the secondary bus.

Table 1: Tsi350A PCI Transactions

2. PCI Interface > Transaction Types26

Initiates as a Master Responds as a Target

Command Type of Transaction

0000 Interrupt Acknowledge No No No No
0001 Special Cycle Yes Yes No No
0010 I/O Read Yes Yes Yes Yes
0011 I/O Write Yes Yes Yes Yes
0100 Reserved No No No No
0101 Reserved No No No No
0110 Memory Read Yes Yes Yes Yes
0111 Memory Write Yes Yes Yes Yes
1000 Reserved No No No No
1001 Reserved No No No No
1010 Configuration read No Yes Yes No
1011 Configuration Write Type 1 Yes Yes Type 1
1100 Memory Read Multiple Yes Yes Yes Yes
1101 Dual Address Cycle Yes Yes Yes Yes

Primary Secondary Primary Secondary

1110 Memory Read Line Yes Ye s Yes Yes

1111 Memory Write and Invalidate Yes Yes Yes Yes

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2. PCI Interface > Transaction Phases 27

2.2 Transaction Phases

2.2.1 Address Phase

The standard PCI transaction consists of one or two address phases, followed by one or more data
phases. An address phase always lasts one PCI clock cycle. The first address phase is designated by an
asserting (falling) edge on the FRAME_b signal. The number of address phases depends on whether
the address is 32 bits or 64 bits.

2.2.1.1 Single Address Phase

A 32-bit address uses a single address phase. This address is driven on AD[31:0], and the bus
command is driven on C/BE_b[3:0]. Tsi350A supports the linear increment address mode only, which
is indicated when the lower two address bits are equal to 0. If either of the lower two address bits is
nonzero, T si350A automatically disconnects the transaction after the first data transfer.

2.2.1.2 Dual Address Phase

Dual address transactions are PCI transactions that contain the following two address phases specifying
a 64-bit address:

• The first address phase is denoted by the asserting edge of FRAME_b.

• The second address phase always follows on the next clock cycle.
The first address phase contains the dual address command code on the C/BE_b[3:0] lines, and the low

32 address bits on the AD[31:0] lines. The second address phase consists of the specific memory
transaction command code on the C/BE_b[3:0] lines and the high 32 address bits on the AD[31:0]lines.
In this way, 64-bit addressing can be supported on 32-bit PCI buses.

The PCI-to-PCI Bridge Architecture Specification supports the use of dual address transactions in the
prefetchable memory range only. Tsi350A supports dual address transactions in both the upstream and
the downstream direction. Tsi350A supports a programmable 64-bit address range in prefetchable
memory for downstream forwarding of dual address transactions. Dual address transactions falling
outside the prefetchable address range are forwarded upstream, but not downstream. Prefetching and
posting are performed in a manner consistent with the guidelines given in this specification for each
type of memory transaction in prefetchable memory space.

Any memory transactions addressing the first 4 GB space should use a single address phase; that is, the
high 32 bits of a dual address transaction should never be 0.

Tsi350A responds only to dual address transactions that use the following transaction command codes:

• Memory Write

• Memory Write and Invalidate

• Memory Read

• Memory Read Line

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• Memory Read Multiple

Use of other transaction codes may result in a master abort.

2.2.1.3 Device Select (DEVSEL_b) Generation

T si350A always performs positive address dec oding when accepting tran sactions on either the primary
or secondary buses. Tsi350A never subtractively decodes. Medium DEVSEL_b timing is used on both
interfaces.

2.2.2 Data Phase

The address phase or phases of a PCI transaction are followed by one or more data phases. A data
phase is completed when IRDY_b and either TRDY_b or STOP_b are asserted. A transfer of data
occurs only when both IRDY_b and TRDY_b are asserted during the same PCI clock cycle. The last
data phase of a transaction is indicated when FRAME_b is de-asserted and both TRDY_b and IRDY_b
are asserted, or when IRDY_b and STOP_b are asserted (se e “T rans action Termination” o n page 42 for
further discussion of transaction termination).

Depending on the command type, Tsi350A can support multiple data phase PCI transactions. For a
detailed description of how Tsi350A imposes disconnect boundaries, see “Write Transactions” on

page 28 for a description of write address boundaries and “Read Transactions” on page 32 for a

description of read address boundaries.

2. PCI Interface > Write Transactions28

2.3 Write Transactions

Write transactions are treated as either posted write or delayed write transactions.

2.3.1 Posted Write Transactions

Posted write forwarding is used for memory write and for memory write and invalidate transactions.
When Tsi350A determines that a memory write transaction is to be forwarded across the bridge,

T si350A asserts DEVSEL_b wit h medium timing and TRDY_b in the next cy cle, provided th at enough
buffer space is available in the posted data queue for the address and at least 8 Dwords of data. This
enables Tsi350A to accept write data without obtaining access to the target bus. Tsi350A can accept
one Dword of write data every PCI clock cycle; that is, no target wait states are inserted. This write
data is stored in internal posted write buffers and is subsequently delivered to the target.

Tsi350A continues to accept write data until one of the following events occurs:

• The initiator terminates the transaction by de-asserting FRAME_b and IRDY_b.

• An internal write address boundary is reached, such as a cache line boundary or an aligned 4 kB
boundary, depending on the transaction type.

• The posted write data buffer fills up.

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2. PCI Interface > Write Transactions 29

When one of the last two events occurs, Tsi350A retur ns a target disconnect to the requesting initiator
on this data phase to terminate the transaction. Once the posted write data moves to the head of the
posted data queue, Tsi350A asserts its request on the target bus. This can occur while Ts i350A is still
receiving data on the initiator bus. When the grant for the target bus is received and the target bus is
detected in the idle condition, Tsi350A asserts FRAME_b and drives the stored write address out on the
target bus. On the following cycle, Tsi350A drives the first Dword of write data and continues to
transfer write data until all write data corresponding to that transaction is delivered, or until a target
termination is received. As long as write data exists in the queue, Tsi350A can drive 1 Dword of write
data each PCI clock cycle.

Tsi350A ends the transaction on the target bus when one of the following conditions is met:

• All posted write data has been delivered to the target.

• The target returns a target disconnect or target retry (Tsi350A starts another transaction to deliver
the rest of the write date)

• The target returns a target abort (Tsi350A discards remaining write data).

• The master latency timer expires, and Tsi350A no longer has the target bus grant (Tsi350A starts
another transaction to deliver remaining write data).

2.3.2 Memory Write and Invalidate Transactions

Posted write forwarding is used for memory write and invalidate transactions. Memory write and
invalidate transactions guarantee transfer of entire cache lines. If the write buffer fills before an entire
cache line is transferred, Tsi350A disconnects the transaction and converts it to a memory write
transaction.

Tsi350A disconnects memory write and invalidate co m mand s at aligned cache line boundaries. The
cache line size value in Tsi350A cache line size register gives the number of Dwords in a cache line.
For Tsi350A to generate memory write and invalidate transactions, this cache line size value must be
written to a value that is a nonzero power of two and less than or equal to 16 (that is, 1, 2, 4, 8, or 16
Dwords).

If the cache line size does not meet the memory write and invalidate conditions, that is, the value is 0 or
is not a power of two or is greater than 16 Dwords, Tsi350A treats the memory write and invalidate
command as a memory write command. In this case, when Tsi350A forwards the memory write and
invalidate transaction to the target bus, it converts the command code to a memory write code and does
not observe cache line boundaries.

If the value in the cache line size register does meet the memory write and invalidate conditions, that is,
the value is a nonzero power of 2 less than or equal to 16 Dwords, T si350A returns a target disconnect
to the initiator either on a cache line boundary or when the posted write buffer fills. For a cache line
size of 16 Dwords, Tsi350A disconnects a memory write and invalidate transaction on every cache line
boundary. When the cache line size is 1, 2, 4, or 8 Dwords, Tsi350A accepts another cache line if at
least 8 Dwords of empty space remains in the posted write buffer. If less than 8 Dwords of empty space
remains, Tsi350A disconnects on that cache line boundary. When the memory write and invalidate
transaction is disconnected before a cache line boundary is reached, typically because the posted write
buffer fills, the transaction is converted to a memory write transaction.

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2.3.3 Delayed Write Transactions

Delayed write forwarding is used for I/O write transactions and for Type 1 configuration write
transactions.

A delayed write transaction guarantees that the actual target response is returned back to the initiator
without holding the initiating bus in wait states. A delayed write transaction is limited to a single
Dword data transfer.

When a write transaction is first detected on the initiator bus, and Tsi350A forwards it as a delayed
transaction, Tsi350A claims the access by asserting DEVSEL_b and returns a target retry to the
initiator. During the address phas e, Tsi350A samples the bus command, address, and address parity one
cycle later. After IR DY_b is assert ed, Tsi350A also samples the fir st da ta Dword, byte enable bits , and
data parity. This information is placed into the delayed transaction queue. The transaction is queued
only if no other existing delayed transactions have the same address and command, and if the delayed
transaction queue is not full. When the delayed write transaction moves to the head of the delayed
transaction queue and all ordering constraints with posted data are satisfied, Ts i350A initiates the
transaction on the target bus. Tsi350A transfers the write data to the target. If Tsi350A receives a target
retry in response to the write transaction on the target bus, it continues to repeat the write transaction
until the data transfer is completed, or until an error condition is encoun tered.

If Tsi350A is unable to deliver write data after 2
returns a target abort to the initiator. The delayed transaction is removed from the delayed transaction
queue. Tsi350A also asserts P_SERR_b if the primary SERR_b enable bit is set in the command
register.

2. PCI Interface > Write Transactions30

24

attempts, Tsi350A ceases further write attempts and

When the initiator repeats the same write transaction (same command, address, byte enable bits, and
data), and the completed delayed transaction is at the head of the queue, Tsi350A claims the access by
asserting DEVSEL_b and returns TRDY_b to the initiator to indicate that the write data was
transferred. If the initiator requests multiple Dwords, Tsi350A also asserts STOP_b in conjunction with
TRDY_b to signal a target disconnect. Note that only those bytes of write data with valid byte enable
bits are compared. If any of the byte enable bits are turned off (driven high), the corresponding byte of
write data is not compared.

If the initiator repeats the write transaction before the data has been transferred to the target, Tsi350A
returns a target retry to the initiator. Tsi350A continues to return a target retry to the initiator until write
data is delivered to the target, or until an error condition is encountered. When the write transaction is
repeated, Tsi350A does not make a new entry into the delayed transaction queue. For detailed
information on how the Tsi350A responds to target termination during delayed write transactions, see

“Delayed Write Target Termination Response” on page 44.

Tsi350A

implements a discard timer that starts counting when the delayed write completion is at the

head of the delayed transaction queue. The initial value of this timer can be set to one of two values,
selectable through both the primary and secondary master time-out bits in the bridge control register . If
the initiator does not repeat the delayed write transaction before the discard timer expires, Tsi350A
discards the delayed write transaction from the delayed transaction queu e and asserts P_SERR_b (if
enabled).

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