IDT Tsi340-RDK1 User Manual
IDT
Tsi340 Evaluation Board
User Manual
80E3000_MA002_02
September 19, 2009
6024 Silver Creek Valley Road San Jose, California 95138
Telephone: (408) 284-8200 • FAX: (408) 284-3572
Printed in U.S.A.
©2009 Integrated Device Technology, Inc.
Titlepage
Integrated Device Technology, Inc. ("IDT") reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or
performance. IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information
herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may
contain errata which can affect product performance to a minor or immaterial degree. Current characterized errata will be made available upon request. Items identified
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purposes only and should not be relied upon for developing applications. Any use of such code examples shall be at the user's sole risk.
Copyright © 2009 Integrated Device Technology, Inc.
All Rights Reserved.
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GENERAL DISCLAIMER
1. Tsi340 Evaluation Board User Manual
This document explains the design and layout of the Tsi340 Evaluation Board User Manual. The
following topics are discussed:
• “Overview” on page 3
• “Board Design” on page 5
• “Board Layout” on page 11
• “Build of Materials (BOM)” on page 18
Revision History
80E3000_MA002_02, Formal, September 2009
This document was rebranded as IDT. It does not include any technical changes.
80E3000_MA002_01, Formal, May 2007
3
This is the first version of this document.
Related Documents
Tsi340 Evaluation Board Schematics
1.1 Overview
This document is divided in two sections: board design and board layout. In board design, the
components on the board and board functionary are explained. In the board layout section the
component placement and the setting options are explained.
1.1.1 Evaluation Board Part Number
The Ts i340 evaluation board part number is Tsi340-RDK1 V1.0. The assembly number of the board is
E3000_AS001.
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1.1.2 Functional Description
This section describes the components on th e evaluation board.
1.1.2.1 Tsi340 PCI-to-PCI Bridge
• Primary PCI: 32bit, 66MHz
• Secondary PCI: 32bit, 66MHz
• Clocking Mode: Synchronized primary and secondary clocking
• Signal Standard: 3.3V LVTTL with 5V tolerance
• Supply Voltage: 3.3V
• Package: FQFP-128pin
1.1.2.2 Primary PCI Connector
• 32-bit universal PCI finger connector
• Support both 3.3 V and 5 V PCI slot
• Compliant with PPCI Specification (Revision 2.3)
• VIO pins are not supported
1.1.2.3 Secondary PCI Connector
• Four 3.3 V, 32 bit, PCI connector slots
• PCI clocking generated from Tsi340
• Compliant with PCI Specification (Revision 2.3)
1.1.2.4 Board Form Factor
• Form Factor: 4-layers Micro ATX Add-in Card with extended height
• Size: ~5.5” x 7.5”
1.1.2.5 Power Supply
• PCI Finger Edge Connector: +3.3 V, +5 V, +12 V, -12 V
• Maximum Power Consumption: 25 W
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2. Board Design
Tsi340
PCI-to-PCI Bridge
Secondary Interface
3.3V/5V 32Bit PCI
Finger Edge Connector
3.3V 32Bit PCI Thru-Hole Connector Slot B
66MHz
3.3V 32Bit PCI Right Angle Connector Slot A
3.3V 32Bit PCI Thru-Hole Connector Slot C
3.3V 32Bit PCI Thru-Hole Connector Slot D
66MHz
5.0V
3.3V
DIPSWITCH
SETTING
Primary Interface
ATX Power
Connector
The following sections explain the design of the evaluation board, its components, and their
functionality.
2.1 Overview
The Tsi340 PCI-to-PCI bridge evaluation board has the necessary functionality to evaluate all the
features of the Tsi340. The primary PCI side of the Tsi340 is wired to a PCI finger connector. The
secondary PCI side is wired to four, 32-bit, 3.3 V PCI connectors. Figure 1 shows the board block
diagram.
Many features can by exercised with shunt jumpers and switches.
Figure 1: Board Block Diagram
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P_CLK S_CLK_OUT0
S_CLK_OUT1
S_CLK_OUT2
S_CLK_OUT3
Tsi340
DIP
Switch
Secondary PCI
32bit 33/66MHz
Primary PCI
32bit 33/66MHz
PCI_M66EN
2.2 Clocking
Tsi340 is a synchronous device, where the secondary clock outputs are synchronous to the primary
clock input.
Figure 2 shows the PCI clocking connection.
Figure 2: Clock Signals
2.2.1 Domains
Primary and secondary clocking domains are described in the following sections.
2.2.1.1 Primary PCI Clock Domain
The primary clock is sourced from a PCI host. It must be synchronous with the primary PCI bus
(according to the PCI Specification (Revision 2.3))
The PCI host sets the clock frequency based on its M66EN signal level. However, the Tsi340
evaluation board has the option of forcing the PCI host's M66EN signal low with a DIP switch setting
on S1. Refer to “DIP Switch Package/ Individual Switch Position” on page 14 for more information.
2.2.1.2 Secondary PCI Clock Domain
T si340 has four secondary clock outputs, which provide PCI_CLKin for four on-board PCI connectors.
The secondary clock outputs are derived from the primary PCI clock input.
2.2.2 M66EN Signal
The M66EN signal from the primary side PCI finger connector is directly routed to four on-board PCI
connectors. A DIP switch is attached to M66EN that is used to force M66EN to ground so tha t the
33 MHz PCI clock can be set. Refer to “DIP Switch Package/ Individual Switch Position” on page 14
for more information.
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