IDT PCI Express 89HPES32NT24xG2 User Manual

®

IDT® 89HPES32NT24xG2

®

PCI Express

Switch

User Manual

January 2013

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: [phone] • [phone] • FAX: [phone]

©2013 Integrated Device Technology, Inc.

Printed in U.S.A.

Integrated Device Technology, Inc. reserves t he right to make changes to its produc ts or specifications at any time, without notice, in order to improve design or perf or mance
and to supply th e best possible product. IDT does not assume any responsibility for use of any circui try described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use . N o license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

GENERAL DISCLAIMER

Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely
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examples also ma y b e s ubj ec t t o Uni te d S ta tes ex po rt c on trol l aw s an d m ay b e s ubj ect t o the e xpo r t or im por t la ws of ot her co un tries and it i s your re sponsi bilit y to comply with
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Integrated Device Technology's products are not authorized for use as cr itical components in life support devi ces or systems unless a specific written agreement pertaining to
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1. Life support devices or systems are devices or systems which (a) are intend ed for su rgical implant into the body or (b) support or sustain life and whose failure to perform,
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CODE DISCLAIMER

LIFE SUPPORT POLICY

Notes

®

About This Manual

Overview

This user manual includes hardware and software information on the 89HPES32NT24xG2, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard. The part number PES32NT24xG2 which is used extensively throughout this manual in fact
covers two distinct switch devices: the PES32NT24AG2 and the PES32NT24BG2. The information in this
manual applies equally to both devices except where noted in occasional notes and footnotes in various
chapters.

Finding Additional Information

Information not included in this manual such as mechanicals, package pin-outs, and electrical character­istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)
as well as through your local IDT sales representative.

Content Summary

Chapter 1, “PES32NT24xG2 Device Overview,” provides an introduction to the performance capabili­ties of the 89HPES32NT24xG2 and a high level architectural overview of the device.

Chapter 2, “Clocking,” provides a description of the PES32NT24xG2 clocking architecture.

Chapter 3, “Reset and Initialization,” describes the PES32NT24xG2 reset operations and initialization

procedure.

Chapter 4, “Switch Core,” provides a description of the PES32NT24xG2 switch core.

Chapter 5, “Switch Partitions,” describes how the PES32NT24xG2 supports up to 16 active switch

partitions.

Chapter 6, “Failover,” provides a description of the flexible failover mechanism that allows the
construction of highly-available systems.

Chapter 7, “Link Operation,” describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.

Chapter 8, “SerDes,” describes basic functionality and controllability associated with the Serialiazer­Deserializer (SerDes) block in PES32NT24xG2 ports.

Chapter 9, “Power Management,” describes the power management capability structure located in the
configuration space of each PCI-to-PCI bridge in the PES32NT24xG2.

Chapter 10, “Transparent Operation,” describes the device-specific architectural features for the
transparent switch associated with each PES32NT24xG2 partition (i.e., the PCI-to-PCI bridge functions and
their interaction in the switch).

Chapter 11, “Ho t-Plu g and H ot-S wap, ” describes the behavior of the hot-plug and hot-swap features
in the PES32NT24xG2.

Chapter 12, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the
PES32NT24xG2.

Chapter 13, “General Purpose I/O,” describes how the 9 General Purpose I/O (GPIO) pins may be
individually configured as general purpose inputs, general purpose outputs, or alternate functions.

Chapter 14, “Non-Transparent Operation,” describes how a non-transparent bridge in the
PES32NT24xG2 allows two roots or PCI Express trees (i.e., hierarchies) to be interconnected with one or
more shared address windows between them.

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Notes

Chapter 15, “DMA Controller,” describes how the PES32NT24xG2 supports two direct memory
access controller (DMA) functions.

Chapter 16, “Switch Events,” describes mechanisms provided by the PES32NT24xG2 to facilitate
communication between roots associated with different partitions as well as for communication between
these roots and a management agent.

Chapter 17, “Multicast,” describes how the multicast capability enables a single TLP to be forwarded
to multiple destinations.

Chapter 18, “Temperature Sensor,” provides a description of the on-chip temperature sensor with
three programmable temperature thresholds and a temperature history capability.

Chapter 19, “Register Organization,” describes the organization of all the software visible registers in
the PES32NT24xG2 and provides the address space for those registers.

Chapter 20, “PCI to PCI Bridge and Proprietary Port Specific Registers,” lists the Type 1 configura­tion header registers in the PES32NT24xG2 and provides a description of each bit in those registers.

Chapter 21, “Proprietary Registers,” lists the proprietary registers in the PES32NT24xG2 and
provides a description of each bit in those registers.

Chapter 22, “NT Endpoint Registers,” lists the NT Endpoint registers in the PES32NT24xG2 and
provides a description of each bit in those registers.

Chapter 23, “DMA Registers,” lists the DMA registers in the PES32NT24xG2 and provides a descrip­tion of each bit in those registers.

Chapter 24, “Switch Control Registers,” lists the switch control and status registers in the
PES32NT24xG2 and provides a description of each bit in those registers.

Chapter 25, “JTA G Boundary Scan,” discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.

Chapter 26, “Usage Models,” describes possible configurations of the PES32NT24xG2 switch and
presents some important system usage models.

Signal Nomenclature

To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.

To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ s hould be i nter­preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.

To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on
the right. No leading zeros will be included.

Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.

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Notes

1 2 3 4

high-to-low

transition

low-to-high

transition

single clock cycle

Figure 1 Signal Transitions

Numeric Representations

To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.

The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.

The compressed notation ABC[y:x]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.

Data Units

The following data unit terminology is used in this document.

Term Words Bytes Bits

Byte 1/2 1 8
Word 1 2 16
Doubleword (DWord) 2 4 32
Quadword (QWord) 4 8 64

Table 1 Data Unit Terminology

In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double­words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the leas t significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.

The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.

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Notes

0 1 2 3

bit 0bit 31

Address of Bytes within Words: Big Endian

3 2 1 0

bit 0bit 31

Address of Bytes within Words: Little Endian

Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition

Register Terminology

Software in the context of this register terminology refers to modifications made by PCI Express root
configuration writes, writes to registers made through the slave SMBus interface, or serial EEPROM
register initialization. See Table 2.

Type Abbreviation Description

Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mechanisms

such as pin strapping or serial EEPROM. (System firmware hard­ware initialization is only allowed for system integrated devices.)
Bits are read-only after initialization and can only be reset (for
write-once by firmware) with reset.

Read Only and Clear RC Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.

Read Clear and Write RCW Software can read the register/bits with this attribute. Reading the

value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.

Reserved Reserved The value read from a reserved register/bit is undefined. Thus,

software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined
bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit posi­tions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit posi­tions and then written back.
In addition to reserved registers, some valid register fields have
encodings marked as reserved. Such register fields must never be
written with a value corresponding to an encoding marked as
reserved. Violating this rule produces undefined operation in the
device.

Read Only RO Software can only read registers/bits with this attribute. Contents

Table 2 Register Terminology (Part 1 of 2)

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are hardwired to a constant value or are status bits that may be
set and cleared by hardware. Writing to a RO location has no
effect.

IDT

Notes

Type Abbreviation Description

Read and Write RW Software can both read and write bits with this attribute.
Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.

However, writing a value of zero to a bit with this attribute has no
effect. A RW1C bit can only be set to a value of 1 by a hardware
event. To clear a RW1C bit (i.e., change its value to zero) a value
of one must be written to the location. An RW1C bit is never
cleared by hardware.

Read and Write when
Unlocked

Sticky Sticky Register/bits with this designation take on their initial value as a

Switch Sticky SWSticky Register/bits with this designation take on their default value as a

Modified Switch Sticky MSWSticky A MSWSticky register is a Switch Sticky register that in addition to

Table 2 Register Terminology (Part 2 of 2)

Software can read the register/bits with this attribute. Writing to
register/bits with this attribute will only cause the value to be modi­fied if the REGUNLOCK bit in the SWCTL register is set. When
the REGUNLOCK bit is cleared, writes are ignored and the regis­ter/bits are effectively read-only.

result of a switch fundamental reset or partition fundamental reset.
Other resets have no effect.

result of a switch fundamental reset. Other resets have no effect.

taking on its default value as a result of a switch fundamental
reset, it takes on its default value when the event(s) defined in the
register description occur, unless the register has been written-to
by software/firmware before the occurrence of the event.
If the value of an MSWSticky register has been written by soft­ware/firmware, it preserves the value across all events until written
again or until a switch fundamental reset is applied to the device.
After a switch fundamental reset, the MSWSticky register will
return to taking on the value as defined in the register description.

Use of Hypertext

In Chapter 19, Tables 19.2, 19.5, 19.6, 19.10, and 19.11 contain register names and page numbers
highlighted in blue under the Register Definition column. In pdf fil es, users can jump from thi s source table
directly to the registers by clicking on the register name in the source table. Each register name in the table
is linked directly to the appropriate register in Chapters 20 through 24. To return to the source table after
having jumped to the register section, click on the same register name (in blue) in the register section.

Reference Documents

PCI Express Base Specification Revision 2.1., March 4, 2009, PCI-SIG.

PCI Local Bus Specification Revision 3.0., February 3, 2004, PCI-SIG.

PCI-to-PCI Bridge Architecture Specification Revision 1.2., June 9, 2003, PCI-SIG.

Address Translation Services Specification, March 8, 2007, PCI-SIG.

PCI Bus Power Management Interface Specification, Revision 1.2., March 3, 2004, PCI-SIG

SMBus Specification, Version 2.0, August 3, 2000, SBS Implementers Forum.

Revision History

July 8, 2009: Initial publication of preliminary user manual.

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Notes

July 14, 2009: Includes changes in several chapters based on recent updates in the functional specifi­cation.

July 30, 2009: Includes changes in several chapters based on recent updates in the functional specifi­cation.

August 28, 2009: Added Chapter 27, Usage Models.

September 18, 2009: In Chapter 2, added Table 2.5. In Chapter 4, added new sections Packet Routing

Classes and Proprietary Weighted Round Robin (WRR) Arbitration, and revised Figure 4.8. Made
numerous revisions in Chapter 8. In Chapter 10, made changes to the Action Taken column in Table 10.14.
In Chapter 12, updated the I/O Expander tables. In Chapter 15, made changes to Table 15.7 and added text
to DMA Multicast section. In Chapter 25, made numerous changes in SerDes x Transmitter Lane Control 0
and 1 registers

October 6, 2009: In Chapter 3, added text to section Switch Fundamental Rest and moved this section
in front of Boot Configuration Vector section, and added text to Switch Modes section. In Chapter 5, added
text to sections Switch Partitioning and Non-Transparent Operations. In Chapter 15, modified sections Data
Transfer and Addressing, Source Address E xpired Error, and Destination Address Expired Er ror. In Chapter
16, added text to section Switch Signals. In Chapter 21, modified description for bit EIS in the PCIESSTS
register. In Chapter 24, modified description of RUN bit in the DMAC[1:0]CTL register.

October 14, 2009: In Chapter 22, added WRR Port Arbitration Counts registers, and in Chapter 20,
updated Figure 20.2 and Table 20.5 to show new registers. Corrected Table 26.2, Boundary Scan Chain.

November 4, 2009: In Chapter 2, added new section Support for Spread Spectrum Clocking (SCC) with
updated tables and modified Limitations column in Table 2.6, Clock Frequency Limitations. In Chapter 5,
added three new sections: Partition State Change Latency, Port Operating Mode Change Latency, and
Partition Reconfiguration Latency. In Chapter 8, deleted all references to Slew Rate. In Chapter 10, title for
Table 10.11 was changed to Unexpected Completions instead of Unsupported Requests, and a new bullet
was added at the top of section Address Routed TLPs. In Chapter 14, modified text in Overview section and
in section Unsupported Request (UR) Error. In Chapter 15, modified text in section Reception of a Request
TLP That is Unsupported. In Chapter 19, added reference to junction temperature in the Overview section.
In Chapter 20, added new section Configuration Register Side-Effects under Overview. In Chapter 24, DMA
Channel Error Mask register, de-featured bits 2 and 17. In Chapter 25, SMBus Control register, de-featured
bit 16 (MSMBIOM).

November 23, 2009: In Chapter 4, corrected port numbers for Stack 1 in Figure 4.1.

December 4, 2009: In Chapter 10, modified text in section Error Emulation Control in the PCI-to-PCI

Bridge Function and added new section Error Emulation Usage and Limitations. In Chapter 14, modified
text in section Error Emulation Control in the NT Function and added new section Error Emulation Usage
and Limitations.

January 6, 2010: In Chapter 17, corrected references to NT Multicast Control register and NT Multicast
Transmit Enable bit in the following sections: NT Multicast TLP Routing, and Usage Restrictions. In Chapter
20, corrected Figure 20.5. In Chapter 23, NTIERRORMSK0 register, changed bits 29 and 30 to reserved. In
Chapter 24, DMAIERRORMSK0 register, changed bits 29 and 30 to reserved. In Chapter 25, changed
default values for several bits in the TMPADJA and TSSLOPE registers.

March 4, 2010: Revised manual to include references to the PES32NT24BG2 device in Chapters 1, 2,
3, 12, and 26 as appropriate and changed manual name to PES32NT24xG2.

March 8, 2010: Removed references to OUTDBELLCLR and OUTSBELLDBELLCLR registers in
Chapter 14, Non-Transparent Switch Operation.

March 17, 2010: In Chapter 8, updated Tables 8.6, 8.7, 8.8, 8.11, and 8.12. In Chapter 13, deleted re fer­ence to multiple GPIOAFSEL registers; there is only one register. In Chapter 24, deleted “other” from ECRC
Error name for bit 31 in the DMAC[1:0]ERRSTS register.

May 10, 2010: In Chapter 21, PCI Bridge Registers, the ACSCAP register offset address was corrected
to 0x324. In Chapter 23, NT Endpoint Register, revised the Description for MODE field in BARSETUP0
register and LADDR field in BARLIMIT0 register.

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Notes

May 21, 2010: In Chapter 23, NT Endpoint Registers, revised Description for INDEX field in
LUTOFFSET register to read that if BAR4 is selected, the INDEX field must only be set to values 0 to 11
(instead of 12 to 23).

June 21, 2010: In Chapter 23, NT Endpoint Registers, revised Bit Field column in NTMTBLDATA
register.

August 27, 2010: In Chapter 4, revised text in sections Internal Errors and Reporting of Port AER Errors
as Internal Errors and updated Figures 4.7 and 4.8. In Chapter 5, revised text in Reset Mode Change
Behavior. In Chapter 7, revised text in Link Width Negotiation in the Presence of Bad Lanes section and
Crosslink section. In Chapter 11, corrected reference to DLLLASC in Hot Plug Events section. In Chapter
12, revised description for BYTECNT in Tables 12.19 and 12.21. In Chapter 14, added Note at end of
section NT Mapping Table. In Chapter 15, deleted section DMA Channel Errors and revised text in
Descriptor Prefetching, ECRC Errors, and Completion Timeout sections. In Chapter 16, revised text in
section Port AER Errors. In Chapter 17, changed reference from NTMTC to NTMCC in NT Multicast TLP
Routing section.

In Chapter 21, made the following changes: revised description for MAXLNKSPD bit in PCI Express Link
Capabilities register (also applies to same bit in same register in Chapters 23 and 24), revised description
for bits in PCI Express Slot Control register.

In Chapter 22, made the following changes: added text under section Physical Layer Control and Status
Registers, revised description for bits in PCI Express Slot C ontrol Initial Value register, deleted Port AER
Status register, revised Port AER Mask register, added bit 10 to bit 9 as Reserved and revised description
for ILSCC bit in Phy Link Configuration 0 register.

In Chapter 23, made the following changes: revised PCI Express Device Capabilities 2 and PCI Express
Device Control 2 registers, revised Description for REG and EREG bits in ECFGADDR register, added bits
31:16 row in AER Correctable Error Status register, added text in Description of NXTPTR in SNUMCAP
register, added text in Description of NXTPTR in PCIEVCECAP register, revised information for fields
PARBC and PATBLOFF in VCR0CAP register, revised information for fields LPAT and PARBSEL in
VCR0CTL register, revised Description for PATS in VCR0STS register, added text in Description of
NXTPTR in ACSECAPH register, added text in Description of NXTPTR in MCCAPH register, changed
default value for bits 30:29 from 0x1 to 0x3 in NTIERRORMSK0 register, changed bit 6 in the NTINTMSK
register to Reserved, revised description for bits SIZE and MODE in Bar 0 Setup register, revised informa­tion in LADDR field in BARLIMIT0 register, revised text under register title for BAR 1 Limit Address and
changed Default Value for Reserved and LADDR and Description for LADDR, revised text under register
title for BARLIMIT3 and changed Default Value for Reserved and LADDR and Description for LADDR,
revised Default Value and Description for LADDR field in BARLIMIT4 register, revised text under register
title for BARLIMIT5 and changed Default Value and Description for LADDR, revised description for INDEX
in LUTOFFSET register.

In Chapter 24, made the following changes: revised bits 4 to 21 in PCIEDCAP2 register , r evised bit s 4 to
15 in PCIEDCTL2 register, revised bits 21 and 22 and added bits 24 and 25 in AERUES register, revised bit
22 and added bits 24 and 25 in AERUEM register, revised bit 22 and added bits 24 and 25 in AERUESV
register, changed Default Value for CIE bit in AERCES register, changed Type and Default Value for
ECRCGC and ECRCCC bits in AERCTL register, changed bit 24 (HEC) to reserved in DMAIERRORMSK1
register, de-featured bits 0 and 6 through 9 in the DMAC[1:0]ERRSTS register, de-featured bits 0 and 6
through 7 and changed name of bit 31 to ECRCE in DMAC[1:0]ERRMSK register.

In Chapter 25, made the following changes: revised SESTS register, revised description for COUNT
field in FCAP[3:0]TIMER register, added bits 20 and 21 and revised default value and/or description for bits
22 to 25 and changed name/value/description of bit 29 in SMBUSSTS register, removed default value for
TEMP field in TMPSTS register.

September 27, 2010: In Chapter 22, changed bit 16 in the IERRORSTS0 register from ULD to
Reserved.

October 22, 2010: In Chapter 15, added footnote to T able 15.7. In Chapter 25, re-arranged bits 24:28 in
TMPCTL register.

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Notes

December 21, 2010: In Chapter 2, revised header in Table 2.6 to read “Initial Port Clock Mode.” In
Chapter 5, added new footnote #1 in section Port Operating Mode Change. In Chapter 15, deleted refer­ence to DATCT bit in Completion Timeout section. In Chapter 23, added text to SUBVID and SUBID regis­ters. In Chapter 24, changed bit 20 (DATCT bit) in the DMAC[1:0]ERRSTS and DMAC[1:0]ERRMSK
registers to Reserved and added text to SUBVID and SUBID registers. In Chapter 26, deleted PERSTN,
GLK1, and SMODE from Table 26.1.

March 11, 2011: In Chapter 26, revised Usage Considerations section to remove reference to
JTAG_TCK being driven to a known value.

March 25, 2011: In Chapter 22, added PHYLSTATE0 register with FLRET bit description.

May 20, 2011: In Chapter 1, added ZC silicon to Table 1.2.

June 21, 2011: In Chapter 5, section Reset Mode Change Behavior, changed fourth bullet to read “The

port remains in a Reset state for at least 250 µs.”

June 24, 2011: In Chapter 25, added bit BDISCARD to the Switch Control register.

July 15, 2011: In Chapter 1, revised section Switch Events and removed “and Signals” from the section

title. In Chapter 5, revised the following sections: Downstream Switch Port, Port Operating Mode Change
Latency, and System Notification of Partition Reconfiguration. In Chapter 8, revised section Programmable
De-emphasis Adjustment. In Chapter 16, removed “and Signals” from title and revised section Global
Signals and deleted Signals section. In Chapter 21, MCBLKALLH register, changed lower 32 to upper 32 in
description of MCBLKALL bit. In Chapters 22 and 23, deleted references to SSIGNAL field. In Chapter 25,
added section Internal Switch Timers with 4 new registers and deleted SSIGNAL register. Updated Figure

20.5 and Table 20.11, Switch Configuration and Status, in Chapter 20 to account for new registers.

July 27, 2011: In Chapter 22, added bits 7:0 (

RCVD_OVRD) in SERDESCFG register.

August 23, 2011: In Chapter 24, DMACxCFG register, changed 0x2 in DPREFETCH field to Reserved.

September 12, 2011: In Chapter 8, added additional reference in last paragraph of section Driver

Voltage Level and Amplitude Boost.

October 24, 2011: In Chapter 22, added Port Control Register. In Chapter 20, added reference to Port
Control register in Table 20.5.

November 7, 2011: In Chapter 2, section Local Port Clocked Mode, added recommendation to tie
unused port clock pins to ground.

December 4, 2011: In Chapter 25, revised Description for AFSEL0 field in the GPIOAFSEL register.

January 11, 2012: Removed Hardware Error Containment chapter. Deleted references to SWFRST bit.

February 8, 2012: In Chapter 12, added footnote for RERR and WERR bits in Table 12.20.

February 23, 2012: Added paragraph after Table 12.19 to explain use of DWord addresses.

March 14, 2012: In the Overview section of Chapter 2, changed “single” to ”two” differential global refer-

ence clock pairs.

May 1, 2012: In Chapter 2, Clocking, made text changes to state that unused port clock pins should be
connected to Vss on the board. In Chapter 12, SMBus Interfaces, added new section Setting Up I2C
Commands for Block Transactions.

June 27, 2012: In Chapter 12, changed BYTCNT=7 to BYTCNT=4 in Figure 12.14. In Chapter 24,
changed type and default values for bits 16 and 20 in Switch Control register.

January 30, 2013: In Figure 12.12, changed No-ack to Ack between DATALM and DATAUM.

PES32NT24xG2 User Manual 8 January 30, 2013

Notes

Table of Contents

®

About This Manual

Overview ........................................................................................................................................1

Content Summary ..........................................................................................................................1

Signal Nomenclature .....................................................................................................................2

Numeric Representations ..............................................................................................................3

Data Units ......................................................................................................................................3

Register Terminology .....................................................................................................................4

Use of Hypertext ............................................................................................................................5

Reference Documents ...................................................................................................................5

Revision History .............................................................................................................................5

PES32NT24xG2 Device Overview

Overview.........................................................................................................................................1-1

System Identification.......................................................................................................................1-1

Vendor ID................................................................................................................................1-1

Device ID................................................................................................................................1-1

Revision ID.............................................................................................................................1-1

JTAG ID..................................................................................................................................1-2

SSID/SSVID............................................................................................................................1-2

Device Serial Number Enhanced Capability...........................................................................1-2

Architectural Overview....................................................................................................................1-2

Port Operating Modes.....................................................................................................................1-3

Switch Partitioning..........................................................................................................................1-6

Non-Transparent Operation............................................................................................................1-8

DMA Operation.............................................................................................................................1-12

Dynamic Reconfiguration and Failover.........................................................................................1-15

Switch Events...............................................................................................................................1-16

Multicasting and Non-Transparent Multicasting............................................................................1-17

Clocking

Overview.........................................................................................................................................2-1

Port Clocking Modes.......................................................................................................................2-2

Global Clocked Mode.............................................................................................................2-3

Local Port Clocked Mode........................................................................................................2-4

Support for Spread Spectrum Clocking (SSC).......................................................................2-5

Port Clocking Mode Selection.................................................................................................2-6

System Clocking Configurations.....................................................................................................2-8

Reset and Initialization

Overview.........................................................................................................................................3-1

Switch Fundamental Reset.............................................................................................................3-2

Boot Configuration Vector...............................................................................................................3-4

Stack Configuration.........................................................................................................................3-5

Static Configuration of a Stack...............................................................................................3-9

Dynamic Reconfiguration of a Stack via EEPROM / SMBus..................................................3-9

Switch Modes.......................................................................................................................3-10

Partition Resets.............................................................................................................................3-11

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Notes

Partition Fundamental Reset................................................................................................3-12

Partition Hot Reset ...............................................................................................................3-12

Partition Upstream Secondary Bus Reset............................................................................3-13

Partition Downstream Secondary Bus Reset .......................................................................3-14

Port Mode Change Reset.............................................................................................................3-14

Switch Core

Overview.........................................................................................................................................4-1

Switch Core Architecture................................................................................................................4-1

Ingress Buffer.........................................................................................................................4-2

Egress Buffer..........................................................................................................................4-3

Crossbar Interconnect............................................................................................................4-4

Virtual Channel Support..................................................................................................................4-5

Packet Routing Classes..................................................................................................................4-5

Packet Ordering..............................................................................................................................4-6

Arbitration .......................................................................................................................................4-6

Port Arbitration........................................................................................................................4-6

Cut-Through Routing......................................................................................................................4-9

Request Metering .........................................................................................................................4-11

Operation..............................................................................................................................4-13

Completion Size Estimation..................................................................................................4-14

Internal Errors...............................................................................................................................4-16

Switch Core Time-Outs ........................................................................................................4-17

Memory SECDED ECC Protection.......................................................................................4-18

End-to-End Data Path Parity Protection...............................................................................4-18

Reporting of Port AER Errors as Internal Errors...................................................................4-19

Switch Partition and Port Configuration

Overview.........................................................................................................................................5-1

Switch Partitions.............................................................................................................................5-1

Partition Configuration............................................................................................................5-2

Partition State.........................................................................................................................5-3

Partition State Change ...........................................................................................................5-4

Switch Ports....................................................................................................................................5-5

Switch Port Mode ...................................................................................................................5-5

Port Operating Mode Change.......................................................................................................5-13

Common Operating Mode Change Behavior .......................................................................5-15

No Action Mode Change Behavior.......................................................................................5-21

Reset Mode Change Behavior .............................................................................................5-21

Partition Reconfiguration and Failover..........................................................................................5-21

Partition Reconfiguration Latency.........................................................................................5-23

System Notification of Partition Reconfiguration ..................................................................5-23

Failover

Overview.........................................................................................................................................6-1

Failover Initiation.............................................................................................................................6-1

Software Initiated Failover......................................................................................................6-2

Signal Initiated Failover..........................................................................................................6-2

Watchdog Timer Initiated Failover..........................................................................................6-2

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Link Operation

Overview.........................................................................................................................................7-1

Port Merging...................................................................................................................................7-1

Port Maximum Link Width...............................................................................................................7-1

Polarity Inversion............................................................................................................................7-2

Lane Reversal.................................................................................................................................7-2

Link Width Negotiation....................................................................................................................7-4

Link Width Negotiation in the Presence of Bad Lanes ...........................................................7-5

Dynamic Link Width Reconfiguration..............................................................................................7-5

Dynamic Link Width Reconfiguration in the PES32NT24xG2................................................7-6

Link Speed Negotiation...................................................................................................................7-6

Link Speed Negotiation in the PES32NT24xG2.....................................................................7-7

Software Management of Link Speed ....................................................................................7-8

Link Retraining................................................................................................................................7-9

Link States......................................................................................................................................7-9

Link Down Handling......................................................................................................................7-10

Slot Power Limit Support..............................................................................................................7-11

Upstream Port ......................................................................................................................7-11

Downstream Switch Port......................................................................................................7-12

Link Active State Power Management (ASPM)............................................................................7-12

L0s ASPM.............................................................................................................................7-12

L1 ASPM ..............................................................................................................................7-13

Link Status....................................................................................................................................7-16

De-emphasis Negotiation .............................................................................................................7-16

Crosslink.......................................................................................................................................7-17

Hot Reset Operation on a Crosslink.....................................................................................7-17

Link Disable Operation on a Crosslink .................................................................................7-18

Gen 1 Compatibility Mode ............................................................................................................7-18

SerDes

Overview.........................................................................................................................................8-1

SerDes Numbering and Port Association.......................................................................................8-1

SerDes Transmitter Controls..........................................................................................................8-3

Driver Voltage Level and Amplitude Boost.............................................................................8-3

De-emphasis ..........................................................................................................................8-4

PCI Express Low-Swing Mode...............................................................................................8-4

Receiver Equalization.....................................................................................................................8-4

Programming of SerDes Controls...................................................................................................8-4

Programmable Voltage Margining and De-Emphasis ............................................................8-5

SerDes Transmitter Control Registers....................................................................................8-6

Transmit Margining Using the PCI Express Link Control 2 Register....................................8-12

Low-Swing Transmitter Voltage Mode..........................................................................................8-12

Receiver Equalization Controls.....................................................................................................8-14

SerDes Power Management.........................................................................................................8-14

Power Management

Overview.........................................................................................................................................9-1

Power Management Event (PME) Messages.................................................................................9-4

PCI Express Power Management Fence Protocol .........................................................................9-4

Upstream Switch Port or Downstream Switch Port Mode......................................................9-4

NT Function Mode or NT with DMA Function Mode...............................................................9-5

Upstream Switch Port with NT and/or DMA Function Mode...................................................9-5

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Transparent Switch Operation

Overview.......................................................................................................................................10-1

Transaction Routing......................................................................................................................10-1

Virtual Channel Support................................................................................................................10-2

Maximum Payload Size................................................................................................................10-2

Upstream Port Device Number.....................................................................................................10-2

Bus Locking..................................................................................................................................10-2

Interrupts.......................................................................................................................................10-4

Downstream Port Interrupts..................................................................................................10-4

Upstream Port Interrupts......................................................................................................10-4

Legacy Interrupt Aggregation...............................................................................................10-5

Access Control Services...............................................................................................................10-6

ECRC Support............................................................................................................................10-10

Error Detection and Handling by the PCI-to-PCI Bridge Function..............................................10-11

Physical Layer Errors .........................................................................................................10-11

Data Link Layer Errors........................................................................................................10-12

Transaction Layer Errors....................................................................................................10-13

Routing Errors ....................................................................................................................10-23

Error Emulation Control in the PCI-to-PCI Bridge Function................................................10-24

Hot-Plug and Hot-Swap

Overview.......................................................................................................................................11-1

Hot-Plug Signals...........................................................................................................................11-3

Port Reset Outputs.......................................................................................................................11-5

Power Enable Controlled Reset Output................................................................................11-5

Power Good Controlled Reset Output..................................................................................11-6

Hot-Plug Events............................................................................................................................11-7

Legacy System Hot-Plug Support.................................................................................................11-7

Hot-Swap......................................................................................................................................11-8

SMBus Interfaces

Overview.......................................................................................................................................12-1

Master SMBus Interface...............................................................................................................12-1

Initialization and I

Serial EEPROM...................................................................................................................12-2

Initialization from Serial EEPROM........................................................................................12-3

Programming the Serial EEPROM.....................................................................................12-10

I/O Expanders.....................................................................................................................12-11

Slave SMBus Interface...............................................................................................................12-22

Initialization.........................................................................................................................12-22

SMBus Transactions ..........................................................................................................12-23

Setting Up I2C Commands for Block Transactions.....................................................................12-29

CSR Register Read or Write Operation..............................................................................12-29

SMBus Transactions ..........................................................................................................12-30

Examples of Setting Up the I2C CSR Byte Sequence for a CSR Register Read...............12-32

Examples of Setting Up the I2C CSR Byte Sequence for a CSR Register Write...............12-35

2

C Reset...................................................................................................12-1

General Purpose I/O

Overview.......................................................................................................................................13-1

GPIO Configuration ......................................................................................................................13-1

Input......................................................................................................................................13-1

Output...................................................................................................................................13-1

Alternate Function ................................................................................................................13-1

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Non-Transparent Switch Operation

Overview.......................................................................................................................................14-1

Base Address Registers (BARs)...................................................................................................14-1

BAR Limit..............................................................................................................................14-2

Mapping NT Configuration Space to BAR 0.........................................................................14-4

TLP Translation ............................................................................................................................14-4

Direct Address Translation...................................................................................................14-4

Lookup Table Address Translation.......................................................................................14-5

ID Translation ...............................................................................................................................14-9

NT Mapping Table................................................................................................................14-9

Request ID Translation.......................................................................................................14-11

Completion ID Translation..................................................................................................14-13

Requester ID Capture Register..........................................................................................14-14

TLP Attribute Processing............................................................................................................14-14

No Snoop Processing.........................................................................................................14-14

Address Type Processing...................................................................................................14-15

NT Multicast................................................................................................................................14-15

Inter-Domain Communications...................................................................................................14-15

Doorbell Registers..............................................................................................................14-16

Message Registers.............................................................................................................14-17

Punch-Through Configuration Requests ....................................................................................14-18

Re-programming the Bus Number of the NT Function...............................................................14-19

Interrupts.....................................................................................................................................14-20

Virtual Channel Support..............................................................................................................14-21

Maximum Payload Size..............................................................................................................14-22

Power Management...................................................................................................................14-22

Bus Locking................................................................................................................................14-22

ECRC Support............................................................................................................................14-22

Access Control Services (ACS)..................................................................................................14-23

Error Detection and Handling by the NT Function......................................................................14-25

Physical Layer Errors .........................................................................................................14-26

Data Link Layer Errors........................................................................................................14-26

Transaction Layer Errors....................................................................................................14-26

NTB Inter-Partition Error Propagation ................................................................................14-31

Error Emulation Control in the NT Function........................................................................14-39

Non Transparent Operation Restrictions....................................................................................14-40

DMA Controller

Overview.......................................................................................................................................15-1

Base Address Registers...............................................................................................................15-1

DMA Channel Functional Description...........................................................................................15-1

Data Transfer and Addressing..............................................................................................15-2

DMA Descriptors ..................................................................................................................15-6

DMA Descriptor Processing ...............................................................................................15-15

TLP Attribute and Traffic Class Control..............................................................................15-20

Channel Interrupts..............................................................................................................15-21

DMA Outstanding Requests...............................................................................................15-21

Descriptor Prefetching........................................................................................................15-22

DMA Request Rate Control................................................................................................15-22

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DMA Multicast ....................................................................................................................15-23

Interrupts.....................................................................................................................................15-24

Virtual Channel (VC) Support.....................................................................................................15-25

Access Control Services (ACS) Support ....................................................................................15-25

Power Management....................................................................................................................15-27

Bus Locking................................................................................................................................15-27

ECRC Support............................................................................................................................15-27

Error Handling.............................................................................................................................15-27

PCI Express Error Handling by the DMA Function.............................................................15-28

DMA Limitations and Usage Restrictions ...................................................................................15-36

Switch Events

Overview.......................................................................................................................................16-1

Switch Events...............................................................................................................................16-1

Link Up .................................................................................................................................16-2

Link Down.............................................................................................................................16-3

Fundamental Reset..............................................................................................................16-3

Hot Reset..............................................................................................................................16-3

Failover.................................................................................................................................16-3

Global Signals ......................................................................................................................16-4

Port AER Errors....................................................................................................................16-5

Multicast

Overview.......................................................................................................................................17-1

Transparent Multicast Operation ..................................................................................................17-1

Addressing and Routing.......................................................................................................17-1

Usage Restrictions ...............................................................................................................17-6

Non-Transparent Multicast Operation...........................................................................................17-6

NT Multicast Configuration...................................................................................................17-7

NT Multicast TLP Determination...........................................................................................17-8

NT Multicast TLP Routing.....................................................................................................17-8

NT Multicast Egress Processing...........................................................................................17-9

Usage Restrictions .............................................................................................................17-11

Temperature Sensor

Overview.......................................................................................................................................18-1

Register Organization

Overview.......................................................................................................................................19-1

Partial-Byte Access to Word and DWord Registers .............................................................19-3

Configuration Register Side-Effects .....................................................................................19-3

Address Maps...............................................................................................................................19-4

PCI-to-PCI Bridge Function Registers..................................................................................19-4

Proprietary Port-Specific Registers in the PCI-to-PCI Bridge Function..............................19-11

NT Function Registers........................................................................................................19-14

DMA Function Registers.....................................................................................................19-23

Switch Configuration and Status Registers........................................................................19-29

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PCI-to-PCI Bridge Registers

Type 1 Configuration Header Registers .......................................................................................20-1

PCI Express Capability Structure ...............................................................................................20-13

PCI Power Management Capability Structure............................................................................20-36

Message Signaled Interrupt Capability Structure .......................................................................20-38

Subsystem ID and Subsystem Vendor ID ..................................................................................20-39

Extended Configuration Space Access Registers......................................................................20-40

Advanced Error Reporting (AER) Extended Capability...............................................................20-41

Device Serial Number Extended Capability................................................................................20-51

PCI Express Virtual Channel Capability .....................................................................................20-52

ACS Extended Capability ...........................................................................................................20-55

Multicast Extended Capability.....................................................................................................20-60

Proprietary Port Specific Registers

Port Control Register....................................................................................................................21-1

Upstream PCI-to-PCI Bridge Interrupt and Signaling...................................................................21-1

Port AER Mask Register...............................................................................................................21-3

Port Slot Control ...........................................................................................................................21-5

Internal Error Control and Status Registers..................................................................................21-7

Physical Layer Control and Status Registers .............................................................................21-28

Request Metering .......................................................................................................................21-32

WRR Port Arbitration Counts......................................................................................................21-33

Non-Transparent Multicast Overlay............................................................................................21-38

AER Error Emulation ..................................................................................................................21-40

Global Address Space Access Registers...................................................................................21-43

NT Endpoint Registers

Type 0 Configuration Header Registers .......................................................................................22-1

PCI Express Capability Structure ...............................................................................................22-13

PCI Power Management Capability Structure............................................................................22-28

Message Signaled Interrupt Capability Structure .......................................................................22-29

Subsystem ID and Subsystem Vendor ID ..................................................................................22-31

Extended Configuration Space Access Registers......................................................................22-31

Advanced Error Reporting (AER) Extended Capability...............................................................22-33

Device Serial Number Extended Capability................................................................................22-43

PCI Express Virtual Channel Capability .....................................................................................22-44

ACS Extended Capability ...........................................................................................................22-48

Multicast Extended Capability.....................................................................................................22-50

NT Registers...............................................................................................................................22-53

NT Control & Status............................................................................................................22-53

NT Interrupt and Signaling..................................................................................................22-54

Internal Error Reporting Masks...........................................................................................22-56

Doorbell Registers..............................................................................................................22-64

Message Registers.............................................................................................................22-65

BAR Configuration..............................................................................................................22-67

Mapping Table....................................................................................................................22-85

Lookup Table..............................................................................................................................22-88

AER Error Emulation ..................................................................................................................22-89

Punch-Through Configuration Registers ....................................................................................22-92

NT Multicast................................................................................................................................22-94

Global Address Space Access Registers...................................................................................22-95

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DMA Function Registers

Type 0 Configuration Header Registers .......................................................................................23-1

PCI Express Capability Structure .................................................................................................23-9

PCI Power Management Capability Structure............................................................................23-22

Message Signaled Interrupt Capability Structure .......................................................................23-24

Extended Configuration Space Access Registers......................................................................23-25

Advanced Error Reporting (AER) Extended Capability...............................................................23-26

ACS Extended Capability ...........................................................................................................23-37

DMA Registers............................................................................................................................23-39

BAR Configuration..............................................................................................................23-39

DMA AER Error Emulation.................................................................................................23-39

Internal Error Reporting Masks...........................................................................................23-42

DMA Multicast Control........................................................................................................23-49

DMA Channel Registers.....................................................................................................23-50

Global Address Space Access Registers...................................................................................23-59

Switch Configuration and Status Registers

Switch Control and Status Registers............................................................................................24-1

Internal Switch Timers..................................................................................................................24-5

Switch Partition and Port Registers..............................................................................................24-7

Failover Capability Registers......................................................................................................24-13

Protection....................................................................................................................................24-15

Switch Event Registers...............................................................................................................24-16

Global Doorbells and Message Registers ..................................................................................24-25

SerDes Control and Status Registers.........................................................................................24-26

General Purpose I/O Registers...................................................................................................24-33

Hot-Plug and SMBus Interface Registers...................................................................................24-35

Temperature Sensor Registers...................................................................................................24-45

JTAG Boundary Scan

Introduction...................................................................................................................................25-1

Test Access Point.........................................................................................................................25-1

Signal Definitions..........................................................................................................................25-1

Boundary Scan Chain...................................................................................................................25-3

Test Data Register (DR)...............................................................................................................25-6

Boundary Scan Registers.....................................................................................................25-7

Instruction Register (IR)................................................................................................................25-8

EXTEST................................................................................................................................25-9

SAMPLE/PRELOAD.............................................................................................................25-9

BYPASS...............................................................................................................................25-9

CLAMP...............................................................................................................................25-10

IDCODE..............................................................................................................................25-10

VALIDATE..........................................................................................................................25-10

EXTEST_TRAIN.................................................................................................................25-10

EXTEST_PULSE................................................................................................................25-11

RESERVED........................................................................................................................25-11

Usage Considerations........................................................................................................25-11

Usage Models

Introduction...................................................................................................................................26-1

Boot-time Stack Reconfiguration..................................................................................................26-1

Port Clocking Configuration..........................................................................................................26-2

Boot-time Switch Partitioning........................................................................................................26-3

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Switch Partitioning via serial EEPROM................................................................................26-4

Switch Partitioning via PCI Express Configuration Requests...............................................26-5

Dynamic Port and Partition Reconfiguration.................................................................................26-8

I/O Load Balancing: Downstream Port Migration .................................................................26-8

Non-Transparent Bridge (NTB) Usage Models...........................................................................26-11

PES32NT24xG2 as a Multiprocessor System Interconnect...............................................26-11

NT Crosslink & NT Punch-Through....................................................................................26-15

DMA Usage Models....................................................................................................................26-17

High-Performance Multiprocessor System.........................................................................26-17

Immediate Descriptor Usage..............................................................................................26-20

Failover.......................................................................................................................................26-20

Active / Passive Failover Configuration..............................................................................26-20

Active / Active Failover Configuration.................................................................................26-23

Failover with Two Crosslinked PES32NT24xG2 Switches.................................................26-27

NT Multicasting...........................................................................................................................26-30

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Notes

List of Tables

®

Table 1.1 PES32NT24xG2 Device IDs................................................................................................1-1

Table 1.2 PES32NT24xG2 Revision ID...............................................................................................1-2

Table 1.3 Operating Modes Supported by Each Port..........................................................................1-6

Table 2.1 Ports That Must Operate with the Same Port Clocking Mode.............................................2-3

Table 2.2 PxCLK Usage When a Port Operates in Local Port Clocked Mode ....................................2-4

Table 2.3 GCLK and PxCLK frequencies when PxCLK has SSC.......................................................2-6

Table 2.4 Port Clocking Mode Requirements......................................................................................2-6

Table 2.5 Initial Port Clocking Mode and Slot Clock Configuration State............................................2-7

Table 2.6 Clock Frequency Limitations when Modifying a Port’s Clock Mode ....................................2-7

Table 2.7 Valid PES32NT24xG2 System Clocking Configurations.....................................................2-8

Table 3.1 PES32NT24xG2 Reset Precedence....................................................................................3-1

Table 3.2 Boot Configuration Vector Signals.......................................................................................3-5

Table 3.3 Ports in Each Stack.............................................................................................................3-6

Table 3.4 Possible Configurations for Stack 0.....................................................................................3-6

Table 3.5 Possible Configurations for Stack 1.....................................................................................3-6

Table 3.6 Possible Configurations for Stack 2.....................................................................................3-7

Table 3.7 Possible Configurations for Stack 3.....................................................................................3-8

Table 3.8 Normal Switch Modes........................................................................................................3-10

Table 3.9 Switch Mode Dependent Register Initialization.................................................................3-11

Table 4.1 IFB Buffer Sizes...................................................................................................................4-3

Table 4.2 EFB Buffer Sizes.................................................................................................................4-4

Table 4.3 Replay Buffer Storage Limit.................................................................................................4-4

Table 4.4 Packet Ordering Rules in the PES32NT24xG2...................................................................4-6

Table 4.5 Conditions for Cut-Through Transfers...............................................................................4-10

Table 4.6 Request Metering Decrement Value..................................................................................4-14

Table 5.1 Port Functions for Each Port Operating Mode.....................................................................5-7

Table 5.2 Port Operating Mode Changes Supported by the Switch..................................................5-14

Table 7.1 Crosslink Port Groups........................................................................................................7-17

Table 7.2 Gen 1 Compatibility Mode: bits cleared in training sets .....................................................7-18

Table 8.1 SerDes / Port Association for Ports in Stack 0....................................................................8-2

Table 8.2 SerDes / Port Association for Ports in Stack 1....................................................................8-2

Table 8.3 SerDes / Port Association for Ports in Stack 2....................................................................8-2

Table 8.4 SerDes / Port Association for Ports in Stack 3....................................................................8-3

Table 8.5 SerDes Transmit Level Controls in the S[x]TXLCTL0 and S[x]TXLCTL1 Registers............8-6

Table 8.6 SerDes Transmit Driver Settings in Gen 1 Mode with -3.5 dB de-emphasis.......................8-7

Table 8.7 SerDes Transmit Driver Settings in Gen 2 Mode with -3.5 dB de-emphasis.......................8-8

Table 8.8 SerDes Transmit Driver Settings in Gen 2 Mode with -6.0 dB de-emphasis.......................8-9

Table 8.9 PCI Express Transmit Margining Levels Supported by the PES32NT24xG2....................8-12

Table 8.10 SerDes Transmit Drive Swing in Low Swing Mode at Gen 1 speed..................................8-13

Table 8.11 SerDes Transmit Drive Swing in Low Swing Mode at Gen 2 Speed.................................8-13

Table 9.1 PES32NT24xG2 Power Management State Transition Diagram........................................9-2

Table 10.1 Switch Routing Methods....................................................................................................10-1

Table 10.2 PCI-to-PCI Bridge Function Interrupts...............................................................................10-4

Table 10.3 Downstream to Upstream Port Interrupt Routing Based on Device Number.....................10-6

Table 10.4 Prioritization of ACS Checks for Request TLPs.................................................................10-9

Table 10.5 Prioritization of ACS Checks for Completion TLPs..........................................................10-10

Table 10.6 TLP Types Affected by ACS Checks ...............................................................................10-10

Table 10.7 Physical Layer Errors.......................................................................................................10-12

Table 10.8 Data Link Layer Errors.....................................................................................................10-12

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Notes

Table 10.9 Transaction Layer Errors Associated with the PCI-to-PCI Bridge Function.....................10-14

Table 10.10 Conditions Handled as Unsupported Requests (UR) by the PCI-to-PCI Bridge

Function...........................................................................................................................10-15

Table 10.11 Conditions Handled as Unexpected Completions (UC) by the PCI-to-PCI Bridge

Function...........................................................................................................................10-16

Table 10.12 Ingress TLP Formation Checks associated with the PCI-to-PCI Bridge Function...........10-17

Table 10.13 Egress Malformed TLP Error Checks..............................................................................10-18

Table 10.14 ACS Violations for Ports Operating in Downstream Switch Port Mode...........................10-19

Table 10.15 Prioritization of Transaction Layer Errors........................................................................10-20

Table 11.1 Port Hot Plug Signals........................................................................................................11-3

Table 11.2 Negated Value of Unused Hot-Plug Output Signals..........................................................11-4

Table 12.1 Serial EEPROM SMBus Address......................................................................................12-2

Table 12.2 PES32NT24xG2 Compatible Serial EEPROMs................................................................12-3

Table 12.3 Serial EEPROM Initialization Errors................................................................................12-10

Table 12.4 I/O Expander Functionality Allocation..............................................................................12-11

Table 12.5 Pin Mapping for I/O Expanders 0 through 11..................................................................12-15

Table 12.6 I/O Expander 0 through 11 Port Mapping........................................................................12-16

Table 12.7 Pin Mapping I/O Expander 12.........................................................................................12-16

Table 12.8 Pin Mapping of I/O Expander 13.....................................................................................12-17

Table 12.9 Pin Mapping I/O Expander 14.........................................................................................12-17

Table 12.10 Pin Mapping I/O Expander 15 .........................................................................................12-18

Table 12.11 Pin Mapping I/O Expander 16 .........................................................................................12-18

Table 12.12 Pin Mapping of I/O Expander 17 .....................................................................................12-19

Table 12.13 Pin Mapping of I/O Expander 18 .....................................................................................12-20

Table 12.14 Pin Mapping of I/O Expander 19 .....................................................................................12-20

Table 12.15 Pin Mapping of I/O Expander 20 .....................................................................................12-21

Table 12.16 Pin Mapping of I/O Expander 21 .....................................................................................12-22

Table 12.17 Slave SMBus Address.....................................................................................................12-23

Table 12.18 Slave SMBus Command Code Fields.............................................................................12-23

Table 12.19 CSR Register Read or Write Operation Byte Sequence.................................................12-24

Table 12.20 CSR Register Read or Write CMD Field Description.......................................................12-25

Table 12.21 Serial EEPROM Read or Write Operation Byte Sequence .............................................12-26

Table 12.22 Serial EEPROM Read or Write CMD Field Description ...................................................12-27

Table 12.23 CSR Register Read or Write Operation Byte Sequence.................................................12-30

Table 12.24 Slave SMBus Command Code Fields.............................................................................12-31

Table 12.25 CSR Register Read or Write CMD Field Description.......................................................12-31

Table 12.26 Constants Used in Examples ..........................................................................................12-32

Table 12.27 I2C Command Byte Array Indices...................................................................................12-33

Table 12.28 I2C Command Byte Array Indices...................................................................................12-34

Table 12.29 I2C Command Byte Array Indices...................................................................................12-35

Table 12.30 I2C Command Byte Array Indices...................................................................................12-36

Table 12.31 I2C Command Byte Array Indices...................................................................................12-37

Table 12.32 I2C Command Byte Array Indice.....................................................................................12-38

Table 13.1 GPIO Pin Configuration.....................................................................................................13-1

Table 13.2 GPIO Alternate Function Pin Assignment.........................................................................13-2

Table 13.3 GPIO Alternate Function Pins...........................................................................................13-2

Table 14.1 NT Endpoint BARs............................................................................................................14-2

Table 14.2 12-Entry Lookup Table Parameters...................................................................................14-7

Table 14.3 24-Entry Lookup Table Parameters...................................................................................14-8

Table 14.4 NT Mapping Table Field Description.................................................................................14-9

Table 14.1 NT Endpoint Interrupts....................................................................................................14-21

Table 14.2 ACS Checks Performed by the NT Function in a Port Operating in Multi-function Mode14-24

Table 14.3 TLP Types Affected by ACS Checks...............................................................................14-24

Table 14.4 Transaction Layer Errors Associated with the NT Function............................................14-27

Table 14.5 Conditions Handled as Unsupported Requests (UR) by the NT Function.......................14-29

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Notes

Table 14.6 Conditions Handled as Unexpected Completion (UC) by the NT Function.....................14-30

Table 14.7 Error Logging at Each Function for UR Example # 1......................................................14-34

Table 14.8 Error Logging at Each Function for UR Example # 2......................................................14-35

Table 14.9 Error Logging at Each Function for Poisoned TLP Example...........................................14-36

Table 14.10 Error Logging at Each Function for Poisoned TLP Example...........................................14-38

Table 15.1 DMA Channel Addressing Parameters..............................................................................15-4

Table 15.2 Linear Addressing DMA Example......................................................................................15-5

Table 15.3 Constant Addressing DMA Example.................................................................................15-6

Table 15.4 Stride Control DMA Descriptor Fields................................................................................15-8

Table 15.5 Data Transfer DMA Descriptor Fields..............................................................................15-10

Table 15.6 Immediate Data Transfer DMA Descriptor Fields............................................................15-13

Table 15.7 DMA Chaining Disabling..................................................................................................15-17

Table 15.8 DMA Channel Control (DMACxCTL) Register Action Summary.....................................15-19

Table 15.9 Downstream Switch Port Interrupts.................................................................................15-25

Table 15.10 ACS Checks Performed by the DMA Function................................................................15-26

Table 15.11 TLP Types Affected by ACS Checks...............................................................................15-26

Table 15.12 PCI Express Errors Detected by the DMA Function’s Transaction Layer........................15-30

Table 15.13 Prioritization of Transaction Layer Errors........................................................................15-35

Table 19.1 Global Address Space Layout...........................................................................................19-1

Table 19.2 PCI-to-PCI Bridge Function Configuration Space Registers.............................................19-6

Table 19.3 Default Linkage of Capability Structures for a PCI-to-PCI Bridge Function in the

Upstream Switch Port Mode............................................................................................19-10

Table 19.4 Default Linkage of Capability Structures for a PCI-to-PCI Bridge Function in a

Downstream or Unattached Port.....................................................................................19-10

Table 19.5 Proprietary Port Specific Registers..................................................................................19-13

Table 19.6 NT Function Registers.....................................................................................................19-17

Table 19.7 Default Linkage of Capability Structures for the NT Function When Operating as

Function 0 of the Port......................................................................................................19-22

Table 19.8 Default Linkage of Capability Structures for the NT Function When Operating as

Function 1 of the Port......................................................................................................19-23

Table 19.9 Default Linkage of Capability Structures for the DMA Function......................................19-24

Table 19.10 DMA Function Registers..................................................................................................19-26

Table 19.11 Switch Configuration and Status .....................................................................................19-31

Table 25.1 JTAG Pin Descriptions......................................................................................................25-2

Table 25.2 Boundary Scan Chain........................................................................................................25-3

Table 25.3 Instructions Supported by the JTAG Boundary Scan........................................................25-9

Table 25.4 System Controller Device Identification Register............................................................25-10

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Notes

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Notes

List of Figures

®

Figure 1.1 PES32NT24xG2 Block Diagram ........................................................................................1-3

Figure 1.2 Logical Representation of a Port with PCI-to-PCI bridge, NT, and DMA Functions ..........1-5

Figure 1.3 Transparent PCI Express Switch .......................................................................................1-6

Figure 1.4 Partitionable PCI Express Switch ......................................................................................1-7

Figure 1.5 Non-Transparent Bridge ....................................................................................................1-8

Figure 1.6 Generalized Multi-Port Non-Transparent Interconnect ......................................................1-9

Figure 1.7 Architectural Approaches for Integrating Non-Transparency into a PCI Express Switch .1-10

Figure 1.8 Non-Transparent Switch with Non-Transparency Between Partitions .............................1-11

Figure 1.9 Non-Transparent Switch with Non-Transparent Ports .....................................................1-11

Figure 1.10 Non-Transparent Switch with Non-Transparent Ports .....................................................1-12

Figure 1.11 Non-Transparent Switch with Non-Transparent Ports .....................................................1-12

Figure 1.12 Switch Partition with DMA function ..................................................................................1-13

Figure 1.13 Two Switch Partitions Interconnected by an NTB, with DMA in One Partition .................1-14

Figure 1.14 Two Switch Partitions Interconnected by an NTB, with DMA in Both Partitions ..............1-15

Figure 1.15 Non-Transparent Switch Failover Usage .........................................................................1-16

Figure 1.16 Example of Switch Event Mechanism ..............................................................................1-17

Figure 1.17 Example of Transparent Multicast ...................................................................................1-18

Figure 1.18 Example of Non Transparent Multicast ............................................................................1-18

Figure 2.1 Logical Representation of PES32NT24AG2 Clocking Architecture ...................................2-2

Figure 2.2 Logical Representation of PES32NT24BG2 Clocking Architecture ...................................2-2

Figure 2.3 Clocking Connection for a Port in Global Clocked Mode, with a Common Clocked

Configuration ......................................................................................................................2-3

Figure 2.4 Clocking Connection for a Port in Global Clocked Mode, Non-Common Clocked

Configuration ......................................................................................................................2-4

Figure 2.5 Clocking Connection for a Port in Local Port Clocked Mode, in a Common Clocked

Configuration ......................................................................................................................2-5

Figure 2.6 Clocking Connection for a Port in Local Port Clocked Mode, in a Non-Common

Clocked Configuration ........................................................................................................2-5

Figure 3.1 Switch Fundamental Reset with Serial EEPROM Initialization ..........................................3-3

Figure 3.2 Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State .....................3-4

Figure 4.1 High Level Diagram of Switch Core ...................................................................................4-2

Figure 4.2 Architectural Model of Arbitration .......................................................................................4-7

Figure 4.3 PCI Express Switch Static Rate Mismatch .......................................................................4-12

Figure 4.4 PCI Express Switch Static Rate Mismatch .......................................................................4-13

Figure 4.5 Request Metering Counter Decrement Operation ............................................................4-14

Figure 4.6 Non-Posted Read Request Completion Size Estimate Computation ...............................4-15

Figure 4.7 Internal Error Logic in Each PES32NT24xG2 Port ..........................................................4-17

Figure 4.8 Reporting of Port AER Errors as Internal Errors ..............................................................4-21

Figure 5.1 Allowable Partition State Transitions .................................................................................5-4

Figure 5.2 Logical Representation of a Port with PCI-to-PCI bridge, NT, and DMA Functions ..........5-6

Figure 6.1 Failover Policy vs. Failover Reconfiguration ......................................................................6-1

Figure 7.1 Lane Reversal for Highest Achievable Link Width of x2 ....................................................7-2

Figure 7.2 Lane Reversal for Highest Achievable Link Width of x4 ....................................................7-3

Figure 7.3 Lane Reversal for Highest Achievable Link Width of x8 ....................................................7-4

Figure 7.4 PES32NT24xG2 ASPM Link State Transitions ................................................................7-10

Figure 8.1 Relationship Between Coarse and Fine De-emphasis Controls ......................................8-10

Figure 8.2 Effect of Fine de-emphasis Control at Gen 2 with -6.0 dB Nominal de-emphasis ...........8-11

Figure 9.1 PES32NT24xG2 Power Management State Transition Diagram .......................................9-2

Figure 10.1 Logical Representation of INTx Aggregation ...................................................................10-5

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Notes

Figure 10.2 ACS Source Validation Example .....................................................................................10-7

Figure 10.3 ACS Peer-to-Peer Request Re-direct at a Downstream Switch Port ...............................10-8

Figure 10.4 ACS Upstream Forwarding Example ...............................................................................10-8

Figure 10.5 ACS Peer-to-Peer Request Re-direct by an Upstream PCI-to-PCI Bridge Function .......10-9

Figure 10.6 Error Checking and Logging on a Received TLP ...........................................................10-21

Figure 11.1 Hot-Plug on Switch Downstream Slots Application ..........................................................11-1

Figure 11.2 Hot-Plug with Switch on Add-In Card Application ............................................................11-2

Figure 11.3 Hot-Plug with Carrier Card Application ............................................................................11-2

Figure 11.4 Power Enable Controlled Reset Output Mode Operation ................................................11-6

Figure 11.5 Power Good Controlled Reset Output Mode Operation ...................................................11-6

Figure 12.1 Split SMBus Interface Configuration ................................................................................12-1

Figure 12.2 Single Double-word Initialization Sequence Format ........................................................12-4

Figure 12.3 Sequential Double-word Initialization Sequence Format .................................................12-5

Figure 12.4 Jump Configuration Block ................................................................................................12-5

Figure 12.5 Execution of a Jump Configuration Block ........................................................................12-6

Figure 12.6 Example of Multiple Configuration Images in Serial EEPROM ........................................12-7

Figure 12.7 Wait Configuration Block ..................................................................................................12-8

Figure 12.8 Configuration Done Sequence Format ............................................................................12-9

Figure 12.9 Slave SMBus Command Code Format .......................................................................... 12-23

Figure 12.10 CSR Register Read or Write CMD Field Format ...........................................................12-25

Figure 12.11 Serial EEPROM Read or Write CMD Field Format ........................................................12-26

Figure 12.12 CSR Register Read Using SMBus Block Write/Read Transactions with PEC

Disabled .........................................................................................................................12-27

Figure 12.13 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC

Disabled .........................................................................................................................12-28

Figure 12.14 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled .........12-28

Figure 12.15 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled .....12-28

Figure 12.16 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ......12-28

Figure 12.17 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ..12-29

Figure 14.1 BAR Limit Operation ........................................................................................................14-3

Figure 14.2 Direct Address Translation ...............................................................................................14-4

Figure 14.3 Lookup Table Translation ................................................................................................14-5

Figure 14.4 Lookup Table Entry Format .............................................................................................14-6

Figure 14.5 NT Mapping Table ...........................................................................................................14-9

Figure 14.6 NT Table Partitioning .....................................................................................................14-11

Figure 14.7 Request TLP Requester ID Translation .........................................................................14-12

Figure 14.8 Request TLP Requester ID Translation .........................................................................14-13

Figure 14.9 Logical Representation of Doorbell Operation ...............................................................14-17

Figure 14.10 Logical Representation of Message Register Operation ...............................................14-18

Figure 14.11 Example of a Rootless PCI Express Hierarchy with Bus Number Reprogramming ......14-20

Figure 14.12 Example of ACS Peer-to-Peer Request Re-direct Applied by the NT Function .............14-25

Figure 14.13 Basic Non-Transparent PES32NT24xG2 Configuration ................................................14-31

Figure 14.14 Unsupported Request Example # 1 ...............................................................................14-33

Figure 14.15 Unsupported Request Example # 2 ...............................................................................14-34

Figure 14.16 Poisoned TLP Error Propagation Example ....................................................................14-36

Figure 14.17 Example of Combined Transaction Layer Error Handling ..............................................14-38

Figure 15.1 DMA Data Transfer ..........................................................................................................15-2

Figure 15.2 Linear Addressing ............................................................................................................15-3

Figure 15.3 Linear Addressing Operations .........................................................................................15-3

Figure 15.4 DMA Channel Addressing ................................................................................................15-4

Figure 15.5 Constant Addressing Example .........................................................................................15-6

Figure 15.6 DMA Descriptor List .........................................................................................................15-6

Figure 15.7 General DMA Descriptor Format .....................................................................................1 5-7

Figure 15.8 Stride Control DMA Descriptor Format ............................................................................15-8

Figure 15.9 Data Transfer DMA Descriptor Format ..........................................................................15-10

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Notes

Figure 15.10 Immediate Data Transfer DMA Descriptor Format ........................................................15-13

Figure 15.11 DMA Chaining Example .................................................................................................15-17

Figure 15.12 Path Taken by a TLP Emitted by the DMA When it is Multicasted ................................15-24

Figure 15.13 Path Taken by a TLP Emitted by the DMA When it is NT Multicasted .......................... 15-24

Figure 15.14 Example of ACS Peer-to-Peer Request Redirect Applied by the DMA Function ...........15-27

Figure 15.15 DMA Function’s Error Checking and Logging on a Received TLP ................................15-36

Figure 16.1 Switch Event Detection and Signaling Mechanism ..........................................................16-2

Figure 16.2 Global Signaling Mechanism ...........................................................................................16-4

Figure 17.1 Multicast Group Address Ranges ....................................................................................17-3

Figure 17.2 Multicast Group Address Region Determination ..............................................................17-4

Figure 17.3 Transparent and Non-Transparent Multicast ...................................................................17-7

Figure 19.1 PCI-to-PCI Bridge Configuration Space Organization .....................................................19-5

Figure 19.2 Proprietary Port Specific Register Organization ............................................................19-12

Figure 19.3 NT Function Configuration Space Organization ............................................................19-16

Figure 19.4 DMA Function Configuration Space Organization .........................................................19-25

Figure 19.5 Switch Configuration and Status Space Organization ...................................................19-30

Figure 25.1 Diagram of the JTAG Logic ..............................................................................................25-1

Figure 25.2 State Diagram of the TAP Controller ...............................................................................25-2

Figure 25.3 Diagram of Observe-only Input Cell .................................................................................25-7

Figure 25.4 Diagram of Output Cell ....................................................................................................25-7

Figure 25.5 Diagram of Bidirectional Cell ............................................................................................25-8

Figure 25.6 Device ID Register Format .............................................................................................25-10

Figure 26.1 PES24NT24AG2 with One x8 port and Sixteen x1 Ports ................................................26-1

Figure 26.2 PES24NT6AG2 with Ports Operating in Different Clock Modes ......................................26-3

Figure 26.3 PES16NT8BG2 with Two Partitions Configured via Serial EEPROM ..............................26-4

Figure 26.4 PES16NT8BG2 with Two Partitions Configured via a Switch Manager Root Complex ...26-6

Figure 26.5 I/O Load Balancing Example: Initial Switch Configuration ...............................................26-8

Figure 26.6 I/O Load Balancing Example: Switch Configuration after Port Migration .......................26-11

Figure 26.7 Multiprocessor System Interconnection Using the PES32NT24xG2 .............................26-12

Figure 26.8 System Configuration immediately after Switch Fundamental Reset ............................26-15

Figure 26.9 System Configuration after Serial EEPROM Initialization ..............................................26-16

Figure 26.10 System Configuration Immediately after Switch Fundamental Reset ............................26-18

Figure 26.11 Target System Configuration ......................................................................................... 26-19

Figure 26.12 Active/Passive System Configuration Before Failover Event .........................................26-21

Figure 26.13 Active/Passive System Configuration after Failover Event ............................................26-23

Figure 26.14 Active/Active System Configuration Before Failover Event ...........................................26-24

Figure 26.15 Active/Active System Configuration Before Failover Event ...........................................26-26

Figure 26.16 High Availability System Configuration with Redundant PCI Express Switches ............26-27

Figure 26.17 System Configuration after RC2 Modifies Port 8 in Switch #2

to Downstream Switch Port Mode in Partition 0 .............................................................26-29

Figure 26.18 System Configuration after RC2 Modifies Port 8 in Switch #1

to Upstream Switch Port Mode in Partition 0 .................................................................26-30

Figure 26.19 PES32NT24xG2 with Port 0 Configured in NT Function with DMA Mode

and Ports 4, 8, and 16 in NT Function Mode .................................................................26-31

Figure 26.20 PES32NT24xG2 with Port 0 Configured in NT Function with DMA Mode

and Ports 4, 8, and 16 in NT Function Mode .................................................................26-32

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Notes

PES32NT24xG2 User Manual xviii January 30, 2013

Notes

Register List

®

ACSCAP - ACS Capability (0x324)...................................................................................................... 22-48

ACSCAP - ACS Capability (0x324)...................................................................................................... 23-37

ACSCAP - ACS Capability Register (0x324)........................................................................................ 20-56

ACSCTL - ACS Control (0x326)........................................................................................................... 22-49

ACSCTL - ACS Control (0x326)........................................................................................................... 23-38

ACSCTL - ACS Control Register (0x326).............................................................................................20-58

ACSECAPH - ACS Extended Capability Header (0x320).................................................................... 20-55

ACSECAPH - ACS Extended Capability Header (0x320).................................................................... 22-48

ACSECAPH - ACS Extended Capability Header (0x320).................................................................... 23-37

ACSECV - ACS Egress Control Vector (0x328)................................................................................... 20-59

AERCAP - AER Capabilities (0x100)................................................................................................... 20-41

AERCAP - AER Capabilities (0x100)................................................................................................... 22-33

AERCAP - AER Capabilities (0x100)................................................................................................... 23-26

AERCEM - AER Correctable Error Mask (0x114)................................................................................ 20-48

AERCEM - AER Correctable Error Mask (0x114)................................................................................ 22-40

AERCEM - AER Correctable Error Mask (0x114)................................................................................ 23-34

AERCES - AER Correctable Error Status (0x110)............................................................................... 20-47

AERCES - AER Correctable Error Status (0x110)............................................................................... 22-39

AERCES - AER Correctable Error Status (0x110)............................................................................... 23-32

AERCTL - AER Capabilities and Control (0x118)................................................................................ 20-50

AERCTL - AER Control (0x118)........................................................................................................... 22-42

AERCTL - AER Control (0x118)........................................................................................................... 23-35

AERHL1DW - AER Header Log 1st Doubleword (0x11C)................................................................... 20-50

AERHL1DW - AER Header Log 1st Doubleword (0x11C)................................................................... 22-43

AERHL1DW - AER Header Log 1st Doubleword (0x11C)................................................................... 23-36

AERHL2DW - AER Header Log 2nd Doubleword (0x120)................................................................... 20-50

AERHL2DW - AER Header Log 2nd Doubleword (0x120)................................................................... 22-43

AERHL2DW - AER Header Log 2nd Doubleword (0x120)................................................................... 23-36

AERHL3DW - AER Header Log 3rd Doubleword (0x124).................................................................... 20-51

AERHL3DW - AER Header Log 3rd Doubleword (0x124).................................................................... 22-43

AERHL3DW - AER Header Log 3rd Doubleword (0x124).................................................................... 23-36

AERHL4DW - AER Header Log 4th Doubleword (0x128).................................................................... 20-51

AERHL4DW - AER Header Log 4th Doubleword (0x128).................................................................... 22-43

AERHL4DW - AER Header Log 4th Doubleword (0x128).................................................................... 23-37

AERUEM - AER Uncorrectable Error Mask (0x108)............................................................................ 20-43

AERUEM - AER Uncorrectable Error Mask (0x108)............................................................................ 22-34

AERUEM - AER Uncorrectable Error Mask (0x108)............................................................................ 23-28

AERUES - AER Uncorrectable Error Status (0x104)........................................................................... 20-41

AERUES - AER Uncorrectable Error Status (0x104)........................................................................... 22-33

AERUES - AER Uncorrectable Error Status (0x104)........................................................................... 23-27

AERUESV - AER Uncorrectable Error Severity (0x10C)...................................................................... 20-45

AERUESV - AER Uncorrectable Error Severity (0x10C)...................................................................... 22-37

AERUESV - AER Uncorrectable Error Severity (0x10C)...................................................................... 23-31

BAR0 - Base Address Register 0 (0x010).............................................................................................. 20-5

BAR0 - Base Address Register 0 (0x010).............................................................................................. 22-5

BAR0 - Base Address Register 0 (0x010).............................................................................................. 23-5

BAR1 - Base Address Register (0x014)................................................................................................. 20-6

BAR1 - Base Address Register 1 (0x014).............................................................................................. 22-6

BAR1 - Base Address Register 1 (0x014).............................................................................................. 23-6

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IDT Register List

Notes

BAR2 - Base Address Register 2 (0x018)...............................................................................................22-7

BAR2 - Base Address Register 2 (0x018)...............................................................................................23-6

BAR3 - Base Address Register 3 (0x01C)..............................................................................................22-8

BAR3 - Base Address Register 3 (0x01C)..............................................................................................23-6

BAR4 - Base Address Register 4 (0x020)...............................................................................................22-9

BAR4 - Base Address Register 4 (0x020)...............................................................................................23-6

BAR5 - Base Address Register 5 (0x024).............................................................................................22-10

BAR5 - Base Address Register 5 (0x024)...............................................................................................23-7

BARLIMIT0 - BAR 0 Limit Address (0x474)..........................................................................................22-69

BARLIMIT1 - BAR 1 Limit Address (0x484)..........................................................................................22-72

BARLIMIT2 - BAR 2 Limit Address (0x494)..........................................................................................22-75

BARLIMIT3 - BAR 3 Limit Address (0x4A4)..........................................................................................22-78

BARLIMIT4 - BAR 4 Limit Address (0x4B4)..........................................................................................22-81

BARLIMIT5 - BAR 5 Limit Address (0x4C4)..........................................................................................22-84

BARLTBASE0 - BAR 0 Lower Translated Base Address (0x478)........................................................22-69

BARLTBASE1 - BAR 1 Lower Translated Base Address (0x488)........................................................22-73

BARLTBASE2 - BAR 2 Lower Translated Base Address (0x498)........................................................22-75

BARLTBASE3 - BAR 3 Lower Translated Base Address (0x4A8)........................................................22-78

BARLTBASE4 - BAR 4 Lower Translated Base Address (0x4B8)........................................................22-81

BARLTBASE5 - BAR 5 Lower Translated Base Address (0x4C8)........................................................22-85

BARSETUP0 - BAR 0 Setup (0x400)....................................................................................................23-39

BARSETUP0 - BAR 0 Setup (0x470)....................................................................................................22-67

BARSETUP1 - BAR 1 Setup (0x480)....................................................................................................22-70

BARSETUP2 - BAR 2 Setup (0x490)....................................................................................................22-73

BARSETUP3 - BAR 3 Setup (0x4A0) ...................................................................................................22-76

BARSETUP4 - BAR 4 Setup (0x4B0) ...................................................................................................22-79

BARSETUP5 - BAR 5 Setup (0x4C0)...................................................................................................22-82

BARUTBASE0 - BAR 0 Upper Translated Base Address (0x47C).......................................................22-70

BARUTBASE1 - BAR 1 Upper Translated Base Address (0x48C).......................................................22-73

BARUTBASE2 - BAR 2 Upper Translated Base Address (0x49C).......................................................22-76

BARUTBASE3 - BAR 3 Upper Translated Base Address (0x4AC).......................................................22-79

BARUTBASE4 - BAR 4 Upper Translated Base Address (0x4BC).......................................................22-82

BARUTBASE5 - BAR 5 Upper Translated Base Address (0x4CC) ......................................................22-85

BCTL - Bridge Control Register (0x03E)...............................................................................................20-12

BCVSTS - Boot Configuration Vector Status (0x0004)...........................................................................24-2

BIST - Built-in Self Test Register (0x00F)...............................................................................................20-5

BIST - Built-in Self Test Register (0x00F)...............................................................................................22-5

BIST - Built-in Self Test Register (0x00F)...............................................................................................23-5

CAPPTR - Capabilities Pointer (0x034) ................................................................................................22-11

CAPPTR - Capabilities Pointer (0x034) ..................................................................................................23-8

CAPPTR - Capabilities Pointer Register (0x034)..................................................................................20-10

CCISPTR - CardBus CIS Pointer (0x028).............................................................................................22-11

CCISPTR - CardBus CIS Pointer (0x028)...............................................................................................23-7

CCODE - Class Code (0x009) ................................................................................................................22-4

CCODE - Class Code (0x009) ................................................................................................................23-4

CCODE - Class Code Register (0x009)..................................................................................................20-4

CLS - Cache Line Size (0x00C)..............................................................................................................22-4

CLS - Cache Line Size (0x00C)..............................................................................................................23-4

CLS - Cache Line Size Register (0x00C)................................................................................................20-5

DID - Device Identification (0x002)..........................................................................................................22-1

DID - Device Identification (0x002)..........................................................................................................23-1

DID - Device Identification Register (0x002)...........................................................................................20-1

DMAC[1:0]CFG - DMA Channel Configuration (0x504/604).................................................................23-50

DMAC[1:0]CTL - DMA Channel Control (0x500/600)............................................................................23-50

DMAC[1:0]DPTRH - DMA Channel Descriptor Pointer High (0x52C/62C)...........................................23-58

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