Integrated Device Technology Inc IDT7MPV6255S66M, IDT7MPV6255S15M, IDT7MPV6253S66M, IDT7MPV6256S66M, IDT7MPV6256S15M Datasheet
Integrated Device Technology, Inc.
256KB AND 512KB SECONDARY
CACHE MODULES FOR THE
PowerPC
IDT7MPV6253
IDT7MPV6255/56
FEATURES
• For CHRP based PowerPC systems.
• Asynchronous and pipelined burst SRAM options in the
same module pinout
• Low-cost, low-profile card edge module with 178 leads
• Uses Burndy Computerbus connector, part number
ELF182KSC-3Z50
• Operates with external PowerPC CPU speeds up to
66MHz
• Separate 5V (±5%) and 3.3V (+10/-5%) power supplies
• Multiple GND pins and decoupling capacitors for maximum noise immunity
• Presence Detect output pins allow the system to determine the particular cache configuration.
DESCRIPTION
The IDT7MPV6253/55/56 modules belong to a family of
secondary caches intended for use with PowerPC CPUbased systems. The IDT7MPV6253 uses IDT’s 71V256 32K
FUNCTIONAL BLOCK DIAGRAM
x 8 asynchronous static RAMs and the IDT7MPV6255/56 use
IDT’s 71V432 32K x 32 pipelined synchronous burst static
RAMs in plastic surface mount packages mounted on a
multilayer epoxy laminate (FR-4) board. In addition, each of
the modules uses the IDT 71216 16K x 15 Cache-Tag static
RAM and IDT FCT logic. Extremely high speeds are achieved
using IDT’s high-reliability, low cost CMOS technology.
The low profile card edge package allows 178 signal leads
to be placed on a package 5.06" long, a maximum of 0.250"
thick and a maximum of 1.08" tall. The module space savings
versus discrete components allows the OEM to design additional functions onto the system or to shrink the size of the
motherboard for reduced cost.
All inputs and outputs are LVTTL-compatible, and operate
from separate 5V (±5%) and 3.3V (+10/-5%) power supplies.
Multiple GND pins and on-board decoupling capacitors ensure maximum protection from noise.
IDT7MPV6253 – 256KB ASYNCHRONOUS VERSION
A14 - A26
STANDBY STANDBY
The IDT logo is a registered trademark of Integrated Device Technology, Inc. PowerPC is a trademark of IBM. Computerbus is trademark of Burndy.
13 13
ALE
ADDRA0
ADDRA1
SRAM OE1
WE#0
WE#1
WE#2
WE#3
A14 - A26
TWE#
TOE#
STANDBY
TCLR#
TVALID
DIRTYIN
CLK
Latch
2
ADDRA0
ADDRA1
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
13
8K x 12
Tag Field
8K x 2
Status
8
8
8
8
12
TMATCH
DIRTYOUT
DH0 - DH7
DH8 - DH15
DH16 - DH23
DH24 - DH31
2 - A13
A
SRAM OE0
WE#4
WE#5
WE#6
WE#7
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
32K x 8
Asynchronous
SRAM
8
8
8
8
COMMERCIAL TEMPERATURE RANGE JUNE 1996
1996 Integrated Device Technology, Inc. DSC-3608/2
1
PD0
PD1
PD2
PD3
DL0 - DL7
DL8 - DL15
DL16 - DL23
DL24 - DL31
drw 01
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
IDT7MPV6255 – 256KB PIPELINED BURST VERSION
SRAM OE#0
SRAM ADS#0
CNT EN#0
STANDBY
BURST MODE
A14 - A28
15
A14 - A26
TWE#
TOE#
STANDBY
TCLR#
TVALID
DIRTYIN
CLK
WE#0
WE#1
WE#2
WE#3
CLK1
CLK0
WE#4
WE#5
WE#6
WE#7
13
2
32K x 32
Pipelined
Burst
SRAM
32K x 32
Pipelined
Burst
SRAM
8K x 12
Tag Field
8K x 2
Status
32
DH0-31
32
DL0-31
12
PD0
PD1
PD2
PD3
A2 - A13
TMATCH
DIRTYOUT
RECOMMENDED DC
OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC3 Supply Voltage 3.14 3.3 3.6 V
VCC5 Supply Voltage 4.75 5.0 5.25 V
GND Supply Voltage 0 0 0.0 V
VIH Input High Voltage 2.2 — VCC + 0.3 V
IL Input Low Voltage –0.5
V
NOTE: tbl 01
1. VIL = –1.0V for pulse width less than 5ns, once per cycle.
(1)
— 0.8 V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Power Plane Ambient Temperature GND VCC
VCC3 0°C to +70°C 0V 3.3V +10/-5%
CC5 0°C to +70°C 0V 5.0V ± 5%
V
tbl 02
drw 02
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Value Unit
TERM Terminal Voltage with Respect –0.5 to +4.6 V
V
for VCC3 to GND
TA Operating Temperature 0 to +70 °C
TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –55 to +125 °C
OUT DC Output Current 50 mA
I
NOTE: tbl 03
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
SRAM ACCESS TIMES
Module Speed Asych Burst
66MHz 15ns 8.5ns 10ns
NOTE: tbl 04
1. Burst SRAMs are measured by Clock to Data Out (tCD).
(1)
Tag
2
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
IDT7MPV6256 – 512KB PIPELINED BURST VERSION
SRAM OE#0
SRAM ADS#0
BURST MODE
A13 - A28
CNT EN#0
STANDBY
16
A13 - A26
TWE#
TOE#
STANDBY
TCLR#
TVALID
DIRTYIN
CLK
WE#0
WE#1
WE#2
WE#3
CLK1
WE#4
WE#5
WE#6
WE#7
CLK0
14
2
32K x 32
Pipelined
Burst
SRAM
32K x 32
Pipelined
Burst
SRAM
16K x 12
Tag Field
16K x 2
Status
32
DH0-31
32
DL0-31
SRAM OE#1
SRAM ADS#1
CNT EN#1
STANDBY
BURST MODE
12
WE#0
WE#1
WE#2
WE#3
CLK1
WE#4
WE#5
WE#6
WE#7
CLK0
A
1 - A12
TMATCH
DIRTYOUT
32K x 32
Pipelined
Burst
SRAM
32K x 32
Pipelined
Burst
SRAM
32
DH0-31
32
DL0-31
PD0
PD1
PD2
PD3
CAPACITANCE (IDT7MPV6253 )
(1)
(TA = +25°C, f = 1.0 MHz)
Symbol Parameter
C
IN1 Input Capacitance VIN = 0V 15 pF
(Address)
IN2 Input Capacitance VIN = 0V 25 pF
C
(ADDR0-1)
C
IN3 Input Capacitance VIN = 0V 45 pF
(OE#)
IN4 Input Capacitance VIN = 0V 8 pF
C
(WE#, TWE#)
C
I/O I/O Capacitance VOUT = 0V 10 pF
NOTES: tbl 05
1. These parameters are guaranteed by design but not tested.
(1)
Condition Max. Unit
CAPACITANCE (IDT7MPV6255/56 )
(1)
(TA = +25°C, f = 1.0 MHz)
Symbol Parameter
C
IN1 Input Capacitance VIN = 0V 20 pF
(Address)
IN2 Input Capacitance VIN = 0V — pF
C
(ADDR0-1)
C
IN3 Input Capacitance VIN = 0V 15 pF
(OE#)
IN4 Input Capacitance VIN = 0V 8 pF
C
(WE#, TWE#)
C
I/O I/O Capacitance VOUT = 0V 10/20 pF
NOTES: tbl 06
1. These parameters are guaranteed by design but not tested.
3
(1)
Condition Max. Unit
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