Integrated Device Technology Inc IDT79RV304133PF, IDT79RV304133J, IDT79RV304125J, IDT79RV304120PF, IDT79RV304120J Datasheet

COMMERCIAL TEMPERATURE RANGE MARCH 1996

©1996 Integrated Device Technology, Inc. DSC-2905/5

IDT79R3041

™

INTEGRATED RISController™ FOR
LOW-COST SYSTEMS

IDT79R3041

IDT79RV3041

FEATURES:

• Instruction set compatible with IDT79R3000A
and RISController Family MIPS RISC CPUs

• High level of integration minimizes system cost
— RISC CPU
— Multiply/divide unit
— Instruction Cache
— Data Cache
— Programmable bus interface
— Programmable port width support

• On-chip instruction and data caches
— 2KB of Instruction Cache
— 512B of Data Cache

• Flexible bus interface allows simple, low-cost designs
— Superset pin-compatible with RISController
— Adds programmable port width interface

(8-, 16-, and 32-bit memory sub-regions)

— Adds programmable bus interface timing support

(Extended address hold, Bus turn around time,
Read/write masks)

• Double-frequency clock input

• 16.67MHz, 20MHz, 25MHz and 33MHz operation

• 20MIPS at 25MHz

• Low cost 84-pin PLCC packaging

• On-chip 4-deep write buffer eliminates memory write stalls

• On-chip 4-word read buffer supports burst or simple block
reads

• On-chip DMA arbiter

• On-chip 24-bit timer

• Boot from 8-bit, 16-bit, or 32-bit wide PROMs

• Pin- and software-compatible family includes R3041, R3051,
R3052™, and R3081

™

• Complete software support
— Optimizing compilers
— Real-time operating systems
— Monitors/debuggers
— Floating Point emulation software
— Page Description Languages

Figure 1. R3041 Block Diagram

Clock

Generator

Unit

Master Pipeline Control

System Control

Coprocessor

Integer

CPU Core

Exception/Control

Registers

Bus Interface

Registers

General Registers

(32 x 32)

ALU

Shifter

Mult/Div Unit

Address Adder

PC Control

Virtual Address

Data

Cache

512B

Instruction

Cache

2kB

Physical Address Bus

BIU

Control

DMA

Arbiter

4-deep

Read

Buffer

4-deep

Write

Buffer

ClkIn

Int(5:3), SInt(2:0)

32

32

SBrCond(3:2)

Data Bus

Address/

Data

DMA

Ctrl

Rd/Wr

Ctrl

SysClk

PortSize
Register

Counter

Registers

TC

R3051 Superset

Bus Interface Unit

Data

Unpack

Unit

Data

Pack

Unit

Timing/ Interface

Control

2905 drw 01

1

Integrated Device Technology, Inc.

RISController, R3041, R3051, R3052, R3081, ORION, IDT/sim, and IDT/kit are trademarks, and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

2

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE

Device Instruction Data Floating Bus

Name Cache Cache Point Options

R3051 4kB 2kB Software Emulation Mux’ed A/D
R3052 8kB 2kB Software Emulation Mux’ed A/D

R3071 16kB 4kB On-chip Hardware 1/2 frequency bus option
R3081 or 8kB or 8kB

R3041 2kB 512B Software Emulation 8-, 16-, and 32-bit port width support

Programmable timing support

2905 tbl 01

INTRODUCTION

The IDT RISController family is a series of high-perfor­mance 32-bit microprocessors featuring a high-level of inte­gration, and targeted to high-performance but cost sensitive
embedded processing applications. The RISController family
is designed to bring the high-performance inherent in the
MIPS RISC architecture into low-cost, simplified, power sen­sitive applications.

Thus, functional units have been integrated onto the CPU
core in order to reduce the total system cost, rather than to
increase the inherent performance of the integer engine.
Nevertheless, the RISController family is able to offer 35MIPS
of integer performance at 40MHz without requiring external
SRAM or caches.

Further, the RISController family brings dramatic power
reduction to these embedded applications, allowing the use of
low-cost packaging. Thus, the RISController family allows
customer applications to bring maximum performance at
minimum cost.

The R3041 extends the range of price/performance achiev-

Table 1. Pin-Compatible RISController Family

Figure 2. RISController Family 5-Stage Pipeline

CPU Core

The CPU core is a full 32-bit RISC integer execution
engine, capable of sustaining close to a single cycle execution
rate. The CPU core contains a five stage pipeline, and 32
orthogonal 32-bit registers. The RISController family imple­ments the MIPS-I Instruction Set Architecture (ISA). In fact,
the execution engine of the R3041 is the same as the
execution engine of the R3000A. Thus, the R3041 is binary
compatible with those CPU engines, as well as compatible
with other members of the RISController family.

able with the RISController family, by dramatically lowering
the cost of using the MIPS architecture. The R3041 is de­signed to achieve minimal system and components cost, yet
maintain the high-performance inherent in the MIPS architec­ture. The R3041 also maintains pin and software compatibility
with the RISController and R3081.

The RISController family offers a variety of price/perfor­mance features in a pin-compatible, software compatible
family. Table 1 provides an overview of the current members
of the RISController family. Note that the R3051, R3052, and
R3081 are also available in pin-compatible versions that
include a full-function memory management unit, including
64-entry TLB. The R3051/2 and R3081 are described in
separate manuals and data sheets.

Figure 1 shows a block level representation of the func­tional units within the R3041. The R3041 can be viewed as the
embodiment of a discrete solution built around the R3000A.
By integrating this functionality on a single chip, dramatic cost
and power reductions are achieved.

An overview of these blocks is presented here, followed
with detailed information on each block.

IF

Current

CPU

Cycle

I#1 ALURD MEM WB

IFI#2 ALURD MEM WB

IFI#3 ALURD MEM WB

IFI#4 ALURD MEM WB

IFI#5 ALURD MEM WB

2905 drw 02

The execution engine of the RISController family uses a
five-stage pipeline to achieve close to single cycle execution.
A new instruction can be started in every clock cycle; the
execution engine actually processes five instructions concur­rently (in various pipeline stages). The five parts of the pipeline
are the Instruction Fetch, Read register, ALU execution,
Memory, and Write Back stages. Figure 2 shows the
concurrency achieved by the RISController family pipeline.

3

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE

System Control Co-Processor

The R3041 also integrates on-chip a System Control Co­processor, CP0. CP0 manages the exception handling capa­bility of the R3041, the virtual to physical address mapping of
the R3041, and the programmable bus interface capabilities
of the R3041. These topics are discussed in subsequent
sections.

The R3041 does not include the optional TLB found in other
members of the RISController family, but instead performs the
same virtual to physical address mapping of the base version
of the RISController family. These devices still support
distinct kernel and user mode operation, but do not require
page management software or an on-chip TLB, leading to a
simpler software model and a lower-cost processor.

The memory mapping used by these devices is illustrated
in Figure 3. Note that the reserved address spaces shown are
for compatibility with future family members; in the current
family members, references to these addresses are trans­lated in the same fashion as their respective segments, with
no traps or exceptions taken.

When using the base versions of the architecture, the
system designer can implement a distinction between the
user tasks and the kernel tasks, without having to execute
page management software. This distinction can take the
form of physical memory protection, accomplished by ad-

dress decoding, or in other system specific forms. In systems
which do not wish to implement memory protection, and wish
to have the kernel and user tasks operate out of a single
unified memory space, upper address lines can be ignored by
the address decoder, and thus all references will be seen in
the lower gigabyte of the physical address space.

The R3041 adds additional resources into the on-chip CP0.
These resources are detailed in the R3041 User's Manual.
They allow kernel software to directly control activity of the
processor internal resources and bus interface, and include:

• Cache Configuration Register: This register controls the

data cache block size and miss refill algorithm.

• Bus Control Register: This register controls the behavior

of the various bus interface signals.

• Count and Compare Registers: Together, these two

registers implement a programmable 24-bit timer, which
can be used for DRAM refresh or as a general purpose
timer.

• Port Size Control Register: This register allows the kernel

to indicate the port width of reads and writes to various sub­regions of the physical address space. Thus, the R3041 can
interface directly with 8-, 16-, and 32-bit memory ports,
including a mix of sizes, for both instruction and data
references, without requiring additional external logic.

Figure 3. Virtual to Physical Mapping of Base Architecture Versions

VIRTUAL

PHYSICAL

2905 drw 03

Kernel Cached

(kseg2)

Kernel Uncached

(kseg1)

Kernel Cached

(kseg0)

Kernel/User

Cached
(kuseg)

Kernel Cached

Tasks

1023 MB

Kernel/User

Cached

Tasks

2047 MB

Inaccessible

512 MB

Kernel Boot

and I/O
512 MB

0xfff00000

0xc0000000

0xa0000000

0x00000000

0xffffffff

0x80000000
0x7fffffff
0x7ff00000
0x7fefffff

0x9fffffff

0xbfffffff

0xffefffff

User Reserved

1MB

Kernel Reserved

1MB

0xfff00000

0xc0000000

0xbff00000

0x00000000

0xffffffff

0x40000000
0x3fffffff

0x20000000
0x1fffffff

0xbfefffff

0xbfffffff

0xffefffff

Kernel Reserved

1MB

User Reserved

1MB

4

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE

Clock Generation Unit

The R3041 is driven from a single 2x frequency input clock,
capable of operating in a range of 40%-60% duty cycle. On­chip, the clock generator unit is responsible for managing the
interaction of the CPU core, caches, and bus interface. The
clock generator unit replaces the external delay line required
in R3000A based applications.

Instruction Cache

The R3041 integrates 2kB of on-chip Instruction Cache,
organized with a line size of 16 bytes (four 32-bit entries) a nd
is direct mapped. This relatively large cache substantially
contributes to the performance inherent in the R3041, and
allows systems based on the R3041 to achieve high-perfor­mance even from low-cost memory systems. The cache is
implemented as a direct mapped cache, and is capable of
caching instructions from anywhere within the 4GB physical
address space. The cache is implemented using physical
addresses and physical tags (rather than virtual addresses or
tags), and thus does not require flushing on context switch.

Data Cache

The R3041 incorporates an on-chip data cache of 512B,
organized as a line size of 4 bytes (one word) and is direct
mapped. This relatively large data cache contributes substan­tially to the performance inherent in the RISController family.
As with the instruction cache, the data cache is implemented
as a direct mapped physical address cache. The cache is
capable of mapping any word within the 4GB physical address
space.

The data cache is implemented as a write through cache,
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4­deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance.

Bus Interface Unit

The RISController family uses its large internal caches to
provide the majority of the bandwidth requirements of the
execution engine, and thus can utilize a simple bus interface
connected to slow memory devices.

The RISController family bus interface utilizes a 32-bit
address and data bus multiplexed onto a single set of pins.
The bus interface unit also provides an ALE (Address Latch
Enable) output signal to de-multiplex the A/D bus, and simple
handshake signals to process CPU read and write requests.
In addition to the read and write interface, the R3041 incorpo­rates a DMA arbiter, to allow an external master to control the

external bus.

The R3041 augments the basic RISController bus interface
capability by adding the ability to directly interface with varying
memory port widths, for instructions or data. For example, the
R3041 can be used in a system with an 8-bit boot PROM, 16­bit font/program cartridges, and 32-bit main memory, trans­parently to software, and without requiring external data
packing, rotation, and unpacking.

In addition, the R3041 incorporates the ability to change
some of the interface timing of the bus. These features can be
used to eliminate external data buffers and take advantage of
lower speed and lower cost interface components.

One of the bus interface options is the Extended Address
Hold mode which adds 1/2 clock of extra address hold time
from ALE falling. This allows easier interfacing to FPGAs and
ASICs.

The R3041 incorporates a 4-deep write buffer to decouple
the speed of the execution engine from the speed of the
memory system. The write buffers capture and FIFO proces­sor address and data information in store operations, and
present it to the bus interface as write transactions at the rate
the memory system can accommodate. During main memory
writes, the R3041 can break a large datum (e.g. 32-bit word)
into a series of smaller transactions (e.g. bytes), according to
the width of the memory port being written. This operation is
transparent to the software which initiated the store, insuring
that the same software can run in true 32-bit memory systems.

The RISController family read interface performs both
single word reads and quad word reads. Single word reads
work with a simple handshake, and quad word reads can
either utilize the simple handshake (in lower performance,
simple systems) or utilize a tighter timing mode when the
memory system can burst data at the processor clock rate.
Thus, the system designer can choose to use page or static
column mode DRAMs (and possibly use interleaving, if de­sired, in high-performance systems), or even to use simpler
SRAM techniques to reduce complexity.

In order to accommodate slower quad word reads, the
RISController family incorporates a 4-deep read buffer FIFO,
so that the external interface can queue up data within the
processor before releasing it to perform a burst fill of the
internal caches.

In addition, the R3041 can perform on-chip data packing
when performing large datum reads (e.g., quad words) from
narrower memory systems (e.g., 16-bits). Once again, this
operation is transparent to the actual software, simplifying
migration of software to higher performance (true 32-bit)
systems, and simplifying field upgrades to wider memory.
Since this capability works for either instruction or data reads,
using 8-, 16-, or 32-bit boot PROMs is easily supported by the

5

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE

R3041.

SYSTEM USAGE

The IDT RISController family is specifically designed to
easily connect to low-cost memory systems. Typical low-cost
memory systems use inexpensive EPROMs, DRAMs, and
application specific peripherals.

Figure 4 shows some of the flexibility inherent in the R3041.
In this example system, which is typical of a laser printer, a 32­bit PROM interface is used due to the size of the PDL
interpreter. An embedded system can optionally use an 8-bit

Figure 4. Typical R3041-Based Application

boot PROM instead. A 16-bit font/program cartridge interface
is provided for add-in cards. A 16-bit DRAM interface is used
for a low-cost page frame buffer. In this system example, a
field or manufacturing upgrade to a 32-bit page frame buffer
is supported by the boot software and DRAM controller.
Embedded systems may optionally substitute SRAMs for the
DRAMs. Finally various 8/16/32-bit I/O ports such as RS-232/
422, SCSI, and LAN as well as the laser printer engine
interface are supported. Such a system features a very low
entry price, with a range of field upgrade options including the
ability to upgrade to a more powerful member of the
RISController family.

ClkIn

IDT R3041

RISController

Address/

Data

Control

EPROM and

I/O Controller

DRAM

Controller

16-bit

DRAM

16-bit

Add-on

DRAM

32-bit

EPROM

16-bit

Font

Cartridge

I/O

R3051

Local Bus

2905 drw 04

6

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE

DEVELOPMENT SUPPORT

The IDT RISController family is supported by a rich set of
development tools, ranging from system simulation tools
through PROM monitor and debug support, applications soft­ware and utility libraries, logic analysis tools, and sub-system
modules.

Figure 5 is an overview of the system development process
typically used when developing R3041 applications. The
RISController family is supported in all phases of project
development. These tools allow timely, parallel development
of hardware and software for RISController family based
applications, and include tools such as:

• Optimizing compilers from MIPS Technology, the acknowl-

edged leader in optimizing compiler technology.

• Cross development tools, available in a variety of develop­ment environments.

• The high-performance IDT floating point emulation library
software.

• The IDT Evaluation Board, which includes RAM, EPROM,
I/O, and the IDT PROM Monitor.

• IDT Laser Printer System boards, which directly drive a low­cost print engine, and runs Adobe PostScript™ Page De­scription Language

• Adobe PostScript Page Description Language running on
the IDT RISController family.

• The IDT/sim™ PROM Monitor, which implements a full
PROM monitor (diagnostics, remote debug support, peek/

Figure 5. R3041 Development Environment

Cache3041

Benchmarks

Evaluation Board

Laser Printer System

DBG Debugger

PIXIE Profiler

MIPS Compiler Suite

Stand-Alone Libraries

Floating Point Library

Cross Development Tools

Adobe PostScript PDL

MicroSoft TrueImage PDL

PeerlessPage BIOS

IDT/kit

Hardware Models

General CAD Tools

RISC Sub-systems

'341 Evaluation Board

Laser Printer System

Logic Analysis

Diagnostics

IDT/sim PROM Monitor

Remote Debug

Real-Time OS

Software

Hardware

System

Integration

and Verfification

System

Development

Phase

System

Architecture

Evaluation

2905 drw 05

7

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE

poke, etc.).

• IDT/kit™ (Kernel Integration Toolkit), providing library sup­port and a frame work for the system run time environment.

PERFORMANCE OVERVIEW

The RISController family achieves a very high-level of

performance. This performance is based on:

• An efficient execution engine: The CPU performs ALU
operations and store operations in a single cycle, and has
an effective load time of 1.3 cycles, and branch execution
rate of 1.5 cycles (based on the ability of the compilers to
avoid software interlocks). Thus, the R3041 achieves 20
MIPS performance at 25MHz when operating out of cache.

• Large on-chip caches: The RISController family contains
caches which are substantially larger than those on the
majority of embedded microprocessors. These large caches
minimize the number of bus transactions required, and
allow the RISController family to achieve actual sustained
performance very close to its peak execution rate, even with
low-cost memory systems.

• Autonomous multiply and divide operations: The
RISController family features an on-chip integer multiplier/
divide unit which is separate from the other ALU. This allows
the R3041 to perform multiply or divide operations in parallel
with other integer operations, using a single multiply or
divide instruction rather than using “step” operations.

• Integrated write buffer: The R3041 features a four deep
write buffer, which captures store target addresses and data
at the processor execution rate and retires it to main
memory at the slower main memory access rate. Use of on­chip write buffers eliminates the need for the processor to
stall when performing store operations.

• Burst read support: The R3041 enables the system
designer to utilize page mode, static column, or nibble mode
RAMs when performing read operations to minimize the
main memory read penalty and increase the effective cache
hit rates.

The performance differences among the various
RISController family members depends on the application
software and the design of the memory system. Different
family members feature different cache sizes, and the R3081
features a hardware floating point accelerator. Since all these
devices can be used in a pin and software compatible fashion,
the system designer has maximum freedom in trading be­tween performance and cost. The memory simulation tools
(e.g. Cache3041) allows the system designers to analyze and
understand the performance differences among these de-

vices in their application.

SELECTABLE FEATURES

The RISController family uses two methods to allow the

system designer to configure bus interface operation options.

The first set of options are established via the Reset
Configuration Mode inputs, sampled during the device reset.
After reset, the Reset Mode inputs become regular input or
output signals.

The second set of configuration options are contained in
the System Control Co-Processor registers. These Co-pro­cessor registers configuration options are typically initialized
with the boot PROM and can also be changed dynamically by
the kernel software.

Selectable features include:

• Big Endian vs. Little Endian operation: The part can be

configured to operate with either byte ordering convention,
and in fact may also be dynamically switched between the
two conventions. This facilitates the porting of applications
from other processor architectures, and also permits inter­communication between various types of processors and
databases.

• Data Cache Refill of one or four words: The memory

system must be capable of performing 4 word transfers to
satisfy instruction cache misses and 1 word transfers to
satisfy uncached references. The data cache refill size
option allows the system designers to choose between one
and four word refill on data cache misses, depending on the
performance each option brings to their application.

• Bus Turn Around speed: The R3041 allows the kernel to

increase the amount of time between bus transactions
when changes in direction of the A/D bus occur (e.g., at the
end of reads followed by writes). This allows transceivers
and buffers to be eliminated from the system.

• Extended Address Hold Time: The R3041 allows the

system designer to increase the amount of hold time avail­able for address latching, thus allowing slower speed (low
cost) address latches, FPGAs and ASICs to be used.

• Programmable control signals: The R3041 allows the

system designer to optimally configure various memory
control signals to be active on reads only, writes only, or on
both reads and writes. This allows the simplification of
external logic, thus reducing system cost.

8

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE

• Programmable memory Port Widths: The R3041 allows

the kernel to partition the physical memory space into
various sub-regions, and to individually indicate the port
width of these sub-regions. Thus, the bus interface unit can
perform data packing and unpacking when communicating
with narrow memory sub-regions. For example, these fea­tures, can be used to allow the R3041 to interface with
narrow 8-bit boot PROMs, or to implement 16-bit only
memory systems.

THERMAL CONSIDERATIONS

The RISController family utilizes special packaging tech­niques to improve the thermal properties of high-speed pro­cessors. Thus, all versions of the RISController family are
packaged in cavity down packaging.

The lowest cost members of the family use a standard
cavity down, injection molded PLCC package (the “J” pack­age). This package is used for all speeds of the R3041 family.

Higher speed and higher performance members of the
RISController family utilize more advanced packaging tech­niques to dissipate power while remaining both low-cost and
pin- and socket- compatible with the PLCC package. Thus,
these members of the RISController family are available in the
MQUAD package (the “MJ” package), which is an all alumi­num package with the die attached to a normal copper lead­frame mounted to the aluminum casing. The MQUAD pack­age is pin and form compatible with the PLCC package. Thus,
designers can choose to utilize this package without changing
their PCB.

The members of the RISController family are guaranteed in
a case temperature range of 0°C to +85°C. The type of
package, speed (power) of the device, and airflow conditions,
affect the equivalent ambient conditions which meet this
specification.

The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(ØCA) of the given package. The following equation relates
ambient and case temperature:

TA = TC - P * ØCA
where P is the maximum power consumption at hot tempera­ture, calculated by using the maximum Icc specification for the
device.

Typical values for ØCA at various airflows are shown in

Table 2 for the PLCC package.

NOTES ON SYSTEM DESIGN

The R3041 has been designed to simplify the task of high­speed system design. Thus, set-up and hold-time require­ments have been kept to a minimum, allowing a wide variety
of system interface strategies.

To minimize these AC parameters, the R3041 employs
feedback from its SysClk output to the internal bus interface
unit. This allows the R3041 to reference input signals to the
reference clock seen by the external system. The SysClk
output is designed to provide relatively large AC drive to
minimize skew due to slow rise or fall times. A typical part will
have less than 2ns rise or fall (10% to 90% signal times) when
driving the test load.

Therefore, the system designer should use care when
designing for direct SysClk use. Total loading (due to devices
connected on the signal net and the routing of the net itself)
should be minimized to ensure the SysClk output has a
smooth and rapid transition. Long rise and/or fall times may
cause a degradation in the speed capability of an individual
device.

Similarly, the R3041 employs feedback on its ALE output to
ensure adequate address hold time to ALE. The system
designer should be careful when designing the ALE net to
minimize total loading and to minimize skew between ALE and
the A/D bus, which will ensure adequate address access latch
time.

IDT's field and factory applications groups can provide the
system designer with assistance for these and other design
issues.

Airflow (ft/min)

ØCA 0 200 400 600 800 1000

"J" Package 29 26 21 18 16 15

TQFP 55 40 35 33 31 30

2905 tbl 02

Table 2. Thermal Resistance (ØCA) at Various Airflows

9

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

IDT R3041/RV3041

84-Pin PLCC/

Top View

(Cavity Down)

V

SS

V

CC

A/D(14)
A/D(13)
A/D(12)
A/D(11)
A/D(10)
A/D(9)
V

CC

V

SS

A/D(8)
A/D(7)
A/D(6)
A/D(5)
A/D(4)
A/D(3)
V

SS

V

CC

A/D(2)
A/D(1)
A/D(0)

Burst/WrNear

Addr(3)

Addr(2)

Diag

Last

ALE

Rd

Wr

DataEn

V

CC

V

SS

SysClk

BusGnt

Reset

BusError

Ack

RdCEn

BusReq

MemStrobe

V

SS

V

CC

ClkIn

TriState

BE16(1)

BE16(0)

Addr(1)
Addr(0)

Int(5)

V

SS

V

CC

Int(4)

Int(3)

SInt(2)

SInt(1)

SInt(0)

TC

V

SS

V

CC

A/D(15)

A/D(16)

A/D(17)

A/D(18)

A/D(19)

A/D(20)

A/D(21)

A/D(22)

A/D(23)

A/D(24)

A/D(25)

A/D(26)

V

CC

V

SS

A/D(27)

A/D(28)

A/D(29)

A/D(30)

A/D(31)

184

12

75

33

54

SBrCond(3)/

IOStrobe

SBrCond(2)/

ExtDataEn

13
14

234567891011 83 82 81 80 79 78 77 76

15
16
17
18
19
20
21
22
23

24
25
26
27
28
29
30
31
32

34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

V

CC

V

SS

V

CC

V

SS

2905 drw 06

10

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

2905 drw 06

SBrCond(2)/

ExtDataEn

SBrCond(3)/

IOStrobe

1121314 2345678910111516171819202122232425

V

SS

V

CC

ClkIn

TriState

BE16(1)

BE16(0)

Addr(1)
Addr(0)

Int(5)

V

SS

V

CC

Int(4)

Int(3)

SInt(2)

SInt(1)

SInt(0)

TC

V

SS

V

CC

V

SS

V

CC

A/D(14)
A/D(13)
A/D(12)
A/D(11)
A/D(10)

A/D(9)

V

CC

V

SS

A/D(8)
A/D(7)
A/D(6)
A/D(5)
A/D(4)
A/D(3)

V

SS

V

CC

A/D(2)
A/D(1)
A/D(0)

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

545253 55565758596051 616263 64 65 66 67 68 69 70 71 72 73 74 75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

NC
NC

NC
NC

NC
NC

NC
NC

A/D(15)

A/D(16)

A/D(17)

A/D(18)

A/D(19)

A/D(20)

A/D(21)

A/D(22)

A/D(23)

A/D(24)

A/D(25)

A/D(26)

A/D(27)

A/D(28)

A/D(29)

A/D(30)

A/D(31)

V

CC

V

SS

V

CC

V

SS

NC

NC

NC

NC

Burst/WrNear

Addr(3)

Addr(2)

Diag

Last

ALE

RdWrDataEn

V

CCVSS

SysClk

BusGnt

Reset

BusError

Ack

RdCEn

BusReq

MemStrobe

V

CCVSS

NC

NC

NC

NC

IDT R3041/RV3041

100-Pin

TQFP

(Cavity Up)

Top View

11

IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION

PIN NAME I/O DESCRIPTION

A/D(31:0) I/O Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction

in one phase, and which is used to transmit data between the CPU and external memory resources during
the rest of the transfer.

Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:

Address(31:4): The high-order address for the transfer is presented on A/D(31:4).

BE(3:0):

These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are presented on A/D(3:0).

BE(3

) indicates that

A/D(31:24) will be used, and

BE(0)

corresponds to A/D(7:0). These
strobes are only valid for accesses to 32-bit wide memory ports. Note
that

BE(3:0)

can be held in-active during reads by setting the appropriate
bit of CP0; thus when latched, these signals can be directly used as Write
Enable strobes.

During the second phase, these signals are the data bus for the transaction.

Data(31:0): During write cycles, the bus contains the data to be stored and is driven

from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in
either a single data transaction or in a burst of four words, and places it
into the on-chip read buffer.

The byte lanes used during the transfer are a function of the datum size,
the memory port width, and the system byte-ordering.

Addr(3:0) O Low Address (3:0) A 4-bit bus which indicates which word/halfword/byte is currently expected by the

processor. For 32-bit port widths, only Addr(3:2) is valid during the transfer; for 16-bit port widths, only
Addr(3:1) are valid; for 8-bit port widths, all of Addr(3:0) are valid. These address lines always contain
the address of the current datum to be transferred. In writes and single datum reads, the addresses initially
output the specific target address, and will increment if the size of the datum is wider than the target
memory port. For quad word reads, these outputs function as a counter starting at '0000', and
incrementing according to the width of the memory port.

I

(1)

During

Reset

, the Addr(3:0) pins act as Reset Configuration Mode bit inputs for the

BootProm16

,

BootProm8

, ReservedHigh, and

ExtAddrHold

options.

The R3041 Addr(1:0) output pins are designated as the unconnected Rsvd(1:0) pins in the R3051 and
R3081.

Diag O Diagnostic Pin. This output indicates whether the current bus read transaction is due to an on-

chip cache miss and whether the read is an instruction or data. It is time multiplexed as described below:

Cached/

Uncached

: During the phase in which the A/D bus presents address information, this

pin is an active high output which indicates whether or not the current
read is a result of a cache miss. The value of this pin at this time other
than in read cycles is undefined.

I/

D:

A high at this time indicates an instruction reference, and a low indicates
a data reference. The value of this pin at this time other than in read
cycles is undefined.

The R3041 Diag output pin is designated as the Diag(1) output pin in the R3051 and R3081.

ALE O Address Latch Enable: Used to indicate that the A/D bus contains valid address information for

the bus transaction. This signal is used by external logic to capture the address for the transfer, typically
by using transparent latches.

DataEn

O Data Enable: This signal indicates that the A/D bus is no longer being driven by the processor

during read cycles, and thus the external memory system may enable the drivers of the memory
system onto this bus without having a bus conflict occur. During write cycles, or when no bus trans­action is occurring, this signal is negated, thus disabling the external memory drivers.

2905 tbl 03

NOTE:

1. Reset Configuration Mode bit input when

Reset

is asserted, normal signal

function when

Reset

is de-asserted.