IDT IDT79RC4640 User Manual
查询IDT79R4640供应商
Low-Cost Embedded
64-bit RISController
w/ DSP Capability
Features
Features
FeaturesFeatures
◆
High-performance embedded 64-bit microprocessor
– 64-bit integer operations
– 64-bit registers
– Based on the MIPS RISC Architecture
– 100MHz, 133MHz, 150MHz, 180MHz, 200MHz and 267MHz
operating frequencies
– 32-bit bus interface brings 64-bit power to 32-bit system cost
◆
High-performance DSP capability
– 133.5 Million Integer Mul-Accumulate
operations/sec @267MHz
– 89 MFlops floating-point operations @267MHz
◆
High-performance microprocessor
– 133.5 M Mul-Add/second @267MHz
– 89 MFlops @267MHz
– >640,000 dhrystone (2.1)/sec capability @267MHz (352
dhrystone MIPS)
◆
High level of integration
– 64-bit, 267 MHz integer CPU
– 8KB instruction cache; 8KB data cache
– Integer multiply unit with 133.5M Mul-Add/sec
◆
Upwardly software compatible with IDT RISController
Family
◆
Easily upgradable to 64-bit system
IDT79RC4640
◆
Low-power operation
– Active power management powers-down inactive units
– Standby mode
◆
Large, efficient on-chip caches
– Separate 8KB Instruction and 8KB Data caches
– Over 3200MB/sec bandwidth from internal caches
– 2-set associative
– Write-back and write-through support
– Cache locking, to facilitate deterministic response
– High performance write protocols, for graphics and data
communications
◆
Bus compatible with RC4000 family
– System interfaces to 125MHz, provides bandwidth up to 500
MB/sec
– Direct interface to 32-bit wide systems
– Synchronized to external reference clock for multi- master
operation
– Socket compatible with IDT RC 64474 and RC64574
◆
Improved real-time support
– Fast interrupt decode
– Optional cache locking
Note: “R” refers to 5V parts; “RV” refers to 3.3V parts; “RC”
refers to both
™
Block Diagram
Block Diagram
Block Diagram Block Diagram
267 MHz 64-bit CPU
64-bit Register File
64-bit Adder
Load Align er
Store Aligner
Logic Unit
High-Performance
Integer Multiply
Instruction C a che
Set A
(Lockable)
Instruction C a che
Set B
The IDT logo is a registered trademark and RC4600, RC4650, RC3081,RC3052,RC3051,RC3041 RISController, and RISCore are trademarks of Integ r ated Device Technology, Inc.
Pipeline Control
Instruction Bus
System Control Coprocessor
Address Translation/
Cache Attribute Control
Exception Management
Functions
Control Bus
32-bit
Synchronized
System Inter fac e
Data Bus
89 MFlops Single-Precision FPA
FP Register File
Pack/Unpack
FP Add/Sub/Cvt/
Set A
(Lockable)
Set B
Div/Sqrt
FP Multiply
Pipeline Control
Data Cache
Data Cache
2001 Integrated Device Technology, Inc .
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DSC 3486/2
IDT79RC4640™
Description
Description
DescriptionDescription
The IDT79RC4640 is a low-cost member of the Integrated Device
Technology, Inc. RC4000 family, targeted to a variety of performancehungry embedded applications. The RC4640 continues the RC4000
tradition of high-performance through high-speed pipelines, high-bandwidth caches and bus interface, 64-bit architecture, and careful attention
to efficient control. The cost of this performance is reduced by removing
functional units frequently not required for many embedded applications.
The RC4640 supports a wide variety of embedded processor-based
applications, such as internetworking equipment (routers, switches),
office automation equipment (printers, scanners), and consumer multimedia game systems. Also, being upwardly software-compatible with
the RC32300 family as well as bus- and upwardly software-compatible
with the IDT RC4000 family, the RC4640 will serve in many of the same
applications. And, the RC4640 supports applications that require integer
digital signal processing (DSP) functions.
The RC64475 and RC64575 processors offer a direct migration path
for designs based on IDT’s RC4650 processors, through full pin and
socket compatibility.
The RC4640 brings 64-bit performance levels to lower cost systems.
High performance is preserved by retaining large on-chip two-way setassociative caches, a streamlined high-speed pipeline, high bandwidth,
64-bit execution, and facilities such as early restart for data cache
misses.
These techniques allow the system designer over 3.2 GB/sec aggregate internal bandwidth, 500 MB/sec bus bandwidth, almost 352 Dhrystone MIPS, 89MFlops, and 133.5 M Mul-Add/sec. An array of tools
facilitates rapid development of RC4640-based systems, allowing a
wide variety of customers access to the processor’s high-performance
capabilities while maintaining short time-to-market goals.
Hardware Overview
Hardware Overview
Hardware OverviewHardware Overview
Some key elements of the RC4640 are briefly described below. More
detailed information is available in the IDT79RC4640/IDT79RC4650
RISC Processor Hardware User’s Manual.
Pipeline
Pipeline
PipelinePipeline
The RC4640 uses a 5-stage pipeline that is similar to the
IDT79RC3000 and the IDT79RC4700 processors. The simplicity of this
pipeline allows the RC4640 to cost less than super-scalar processors
and require less power than super-pipelined processors. So, unlike
superscalar processors, applications that have large data dependencies, or require frequent load/stores, can still achieve peak performance.
Integer Execution Engine
Integer Execution Engine
Integer Execution EngineInteger Execution Engine
The RC4640 implements the MIPS-III Instruction Set Architecture
and is fully upward compatible with applications that run on earlier
generation parts. The RC4640 is software-compatible with the RC4650,
and includes the instruction set found in the RC4700 microprocessor,
targeted at higher performance while maintaining binary compatibility
with RC32300 processors.
The extensions result in better code density, greater multiprocessing support, improved performance for commonly used code
sequences in operating system kernels, and faster execution of floatingpoint intensive applications. All resource dependencies are made transparent to the programmer, insuring transportability among implementations of the MIPS instruction set architecture. In addition, MIPS-III
specifies new instructions defined to take advantage of the 64-bit architecture of the processor.
Finally, the RC4640 also implements additional instructions, which
are considered extensions to the MIPS-III architecture. These instructions improve the multiply and multiply-add throughput of the CPU,
making it well suited to a wide variety of imaging and DSP appli cations.
These extensions, which use opcodes allocated by MIPS Technologies
for this purpose, are supported by a wide variety of development tools.
The MIPS integer unit implements a load/store architecture with
single cycle ALU operations (logical, shift, add, sub) and autonomous
multiply/divide unit. The 64-bit register resources include: 32 generalpurpose orthogonal integer registers, the HI/LO result registers for the
integer multiply/divide unit, and the program counter. In addition, the onchip floating-point co-processor adds 32 floating-point registers, and a
floating-point control/status register.
Register File
Register File
Register File Register File
The RC4640 has 32 general-purpose 64-bit registers. These registers are used for scalar integer operations and address calculation. The
register file consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
Arithmetic L ogic Unit
Arithmetic L ogic Unit
Arithmetic L ogic UnitArithmetic L ogic Unit
The RC4640 ALU consists of the integer adder and logic unit. The
adder performs address calculations in addition to arithmetic operations;
the logic unit performs all of the logic and shift operations. Each unit is
highly optimized and can perform an operation in a single pipeline cycle.
Integer Multiply/Divide
Integer Multiply/Divide
Integer Multiply/DivideInteger Multiply/Divide
The RC4640 uses a dedicated integer multiply/divide unit, optimized
for high-speed multiply and multiply-accumulate operation. Table 1
shows the performance, expressed in terms of pipeline clocks, achieved
by the RC4640 integer multiply unit.
Opcode
MULT/U, MAD/U 16 bit 3 2 0
MUL 16 bit 3 2 1
DMULT, DMULTU any 6 5 0
DIV, DIVU any 36 36 0
DDIV, DDIVU any 68 68 0
Table 1 RC4640 Integer Multiply Operation
Operand
Size
32 bit 4 3 0
32 bit 4 3 2
Latency Repeat Stall
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The MIPS-III architecture defines that the results of a multiply or
divide operation are placed in the HI and LO registers. The values can
then be transferred to the general purpose register file using the MFHI/
MFLO instructions.
The RC4640 adds a new multiply instruction, “MUL”, which can
specify that the multiply results bypass the “Lo” register and are placed
immediately in the primary register file. By avoiding the explicit “Movefrom-Lo” instruction required when using “Lo”, throughput of multiplyintensive operations is increased.
An additional enhancement offered by the RC4640 is an atomic
“multiply-add” operation, MAD, used to perform multiply-accumulate
operations. This instruction multiplies two numbers and adds the product
to the current contents of the HI and LO registers. This operation is used
in numerous DSP algorithms, and allows the RC4640 to cost reduce
systems requiring a mix of DSP and control functions.
Finally, aggressive implementation techniques feature low latency for
these operations along with pipelining to allow new operations to be
issued before a previous one has fully completed. Table 1 also shows
the repeat rate (peak issue rate), latency, and number of processor stalls
required for the various operations. The RC4640 performs automatic
operand size detection to determine the size of the operand, and implements hardware interlocks to prevent overrun, allowing this high-performance to be achieved with simple programming.
As in the IDT79RC4700, the RC4640 maintains fully precise floatingpoint exceptions while allowing both overlapped and pipelined operations. Precise exceptions are extremely important in mission-critical
environments, such as ADA, and highly desirable for debugging in any
environment.
The floating-point unit’s operation set includes floating-point add,
subtract, multiply, divide, square root, conversion between fixed-point
and floating-point format, conversion among floating-point formats, and
floating-point compare. These operations comply with IEEE Standard
754. Double precision operations are not directly supported; attempts to
execute double-precision floating point operations, or refer directly to
double-precision registers, result in the RC4640 signalling a “trap” to the
CPU, enabling emulation of the requested function. Table 2 gives the
latencies of some of the floating-point instructions in internal processor
cycles.
Operation
ADD 4
SUB 4
MUL 8
DIV 32
Instruction
Latency
Floating-Point Coprocessor
Floating-Point Coprocessor
Floating-Point CoprocessorFloating-Point Coprocessor
The RC4640 incorporates an entire single-precision floating-point
coprocessor on chip, including a floating-point register file and execution
units. The floating-point coprocessor forms a “seamless” interface with
the integer unit, decoding and executing instructions in parallel with the
integer unit.
The floating-point unit of the RC4640 directly implements singleprecision floating-point operations, which enables the RC4640 to
perform functions such as graphics rendering without requiring extensive die area or power consumption. The single-precision unit of the
RC4640 is directly compatible with the single-precision operation of the
RC4700, and features the same latencies and repeat rates.
The RC4640 does not directly implement the double-precision operations found in the RC4700. However, to maintain software compatibility,
the RC4640 will signal a trap when a double-precision operation is initiated, allowing the requested function to be emulated in software. Alternatively, the system architect could use a software library emulation of
double-precision functions, selected at compile time, to eliminate the
overhead associated with trap and emulation.
Floating-Point Units
Floating-Point Units
Floating-Point UnitsFloating-Point Units
The RC4640’s floating-point execution units perform single precision
arithmetic, as specified in IEEE Standard 754. The execution unit is
broken into a separate multiply unit and a combined add/convert/divide/
square root unit. Overlap of multiply and add/subtract is supported. The
multiplier is partially pipelined, allowing a new multiplication instruction
to begin every 6 cycles.
SQRT 31
CMP 3
FIX 4
FLOAT 6
ABS 1
MOV 1
NEG 1
LWC1 2
SWC1 1
Table 2 Floating-Point Operation
Floating-Point General Register File
Floating-Point General Register File
Floating-Point General Register FileFloating-Point General Register File
The floating-point register file is made up of thirty-two 32-bit registers. These registers are used as source or target registers for the
single-precision operations.
References to these registers as 64-bit registers (as supported in the
RC4700) will cause a trap to be signalled to the integer unit.
The floating-point control register space contains two registers; one
for determining configuration and revision information for the coprocessor and one for control and status information. These are primarily
involved with diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
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IDT79RC4640™
System Control Coprocessor (CP0)
System Control Coprocessor (CP0)
System Control Coprocessor (CP0)System Control Coprocessor (CP0)
The system control coprocessor in the MIPS architecture is responsible for the virtual to physical address translation and cache protocols,
the exception control system, and the diagnostics capability of the
processor. In the MIPS architecture, the system control coprocessor
(and thus the kernel software) is implementation dependent.
In the RC4640, significant changes in CP0 relative to the RC4600
have been implemented. These changes are designed to simplify
memory management, facilitate debug, and speed real-time processing.
System Control Coprocessor Registers
System Control Coprocessor Registers
System Control Coprocessor RegistersSystem Control Coprocessor Registers
The RC4640 incorporates all system control co-processor (CP0)
registers on-chip. These registers provide the path through which the
virtual memory system’s address translation is controlled, exceptions
are handled, and operating modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In addition, the RC4640
includes registers to implement a real-time cycle counting facility, which
aids in cache diagnostic testing, assists in data error detection, and facilitates software debug. Alternatively, this timer can be used as the
operating system reference timer, and can signal a periodic interrupt.
Table 3 shows the CP0 registers of the RC4640.
Number Name Function
0 IBase Instruction address space base
1 IBound Instruction address space bound
2 DBase Data address space base
3 DBound Data address space bound
4-7, 10, 20-25,
29, 31
8 BadVAddr Virtual address on address exceptions
9 Count Counts every other cycle
11 Compare Generate interrupt when Count = Compare
12 Status Miscellaneous control/status
13 Cause Exception/Interrupt information
14 EPC Exception PC
15 PRId Processor ID
16 Config Cache and system attributes
17 CAlg Cache attributes for the 8 512MB regions of the
18 IWatch Instruction breakpoint virtual address
19 DWatch Data breakpoint virtual address
26 ECC Used in cache diagnostics
27 CacheErr Cache diagnostic information
28 TagLo Cache index information
30 ErrorEPC CacheError exception PC
- Not used
virtual address space
Table 3 RC4640 CPO Registers
Operation Modes
Operation Modes
Operation ModesOperation Modes
The RC4640 supports two modes of operation: user mode and
kernel mode. Kernel mode operation is typically used for exception
handling and operating system kernel functions, including CP0 management and access to IO devices. In kernel mode, software has access to
the entire address space and all of the co-processor 0 registers, and
can select whether to enable co-processor 1 accesses. The processor
enters kernel mode at reset, and whenever an exception is recognized.
User mode is typically used for applications programs. User mode
accesses are limited to a subset of the virtual address space, and can
be inhibited from accessing CP0 functions.
0xFFFFFFFF
Kernel virtual address space
(kseg2)
Unmapped, 1.0 GB
0xC0000000
0xBFFFFFFF
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
0xA0000000
0x9FFFFFFF
Cached kernel physical address space
(kseg0)
Unmapped, 0.5GB
0x80000000
0x7FFFFFF
User virtual address space
(useg)
Mapped, 2.0GB
0x00000000
Figure 1 Mode Virtual Addressing (32-bit mode)
Virtual-to-Physical Address Mapping
Virtual-to-Physical Address Mapping
Virtual-to-Physical Address MappingVirtual-to-Physical Address Mapping
The 4GB virtual address space of the RC4640 is shown in Figure 1.
The 4 GB address space is divided into addresses accessible in either
kernel or user mode (kuseg), and addresses only accessible in kernel
mode (kseg2:0).
The RC4640 supports the use of multiple user tasks sharing
common virtual addresses, but mapped to separate physical addresses.
This facility is implemented via the “base-bounds” registers contained in
CP0.
When a user virtual address is asserted (load, store, or instruction
fetch), the RC4640 compares the virtual address with the contents of
the appropriate “bounds” register (instruction or data). If the virtual
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IDT79RC4640™
address is “in bounds”, the value of the corresponding “base” register is
added to the virtual address to form the physical address for that reference. If the address is not within bounds, an exception is signalled.
This facility enables multiple user processes in a single physical
memory without the use of a TLB. This type of operation is further
supported by a number of development tools for the RC4640, including
real-time operating systems and “position independent code”.
Kernel mode addresses do not use the base-bounds registers, but
rather undergo a fixed virtual-to-physical address translation.
Debug Support
Debug Support
Debug SupportDebug Support
To facilitate software debug, the RC4640 adds a pair of “watch” registers to CP0. When enabled, these registers will cause the CP U to take
an exception when a “watched” address is appropriately accessed.
Interrupt Vector
Interrupt Vector
Interrupt VectorInterrupt Vector
The RC4640 also adds the capability to speed interrupt exception
decoding. Unlike the RC4700, which utilizes a single common exception
vector for all exception types (including interrupts), the RC4640 allows
kernel software to enable a separate interrupt exception vector. When
enabled, this vector location speeds interrupt processing by allowing
software to avoid decoding interrupts from general purpose exceptions.
Cache Memory
Cache Memory
Cache MemoryCache Memory
To keep the RC4640’s high-performance pipeline full and operating
efficiently, the RC4640 incorporates on-chip instruction and data caches
that can each be accessed in a single processor cycle. Each cache has
its own 64-bit data path and can be accessed in parallel. The cache
subsystem provides the integer and floating-point units with an aggregate bandwidth of over 3200 MB per second at a pipeline clock
frequency of 267MHz. The cache subsystem is similar in construction to
that found in the RC4700, although some changes have been implemented. Table 4 is an overview of the caches found on the RC4640.
Instru ct ion Cache
Instru ct ion Cache
Instru ct ion CacheInstru ct ion Cache
The RC4640 incorporates a two-way set associative on-chip instruction cache. This virtually indexed, physically tagged cache is 8KB in size
and is parity protected.
Because the cache is virtually indexed, the virtual-to-physical
address translation occurs in parallel with the cache access, thus further
increasing performance by allowing these two operations to occur simultaneously. The tag holds a 20-bit physical address and valid bit, and is
parity protected.
The instruction cache is 64-bits wide, and can be refilled or accessed
in a single processor cycle. Instruction fetches require only 32 bits per
cycle, for a peak instruction bandwidth of 1068MB/sec at 267MHz.
Sequential accesses take advantage of the 64-bit fetch to reduce power
dissipation, and cache miss refill, can write 64 bits-per-cycle to minimize
the cache miss penalty. The line size is eight instructions (32 bytes) to
maximize performance.
In addition, the contents of one set of the instruction cache (set “A”)
can be “locked” by setting a bit in a CP0 register. Locking the set
prevents its contents from being overwritten by a subsequent cache
miss; refill occurs then only into “set B”.
This operation effectively “locks” time critical code into one 4kB set,
while allowing the other set to service other instruction streams in a
normal fashion. Thus, the benefits of cached performance are achieved,
while deterministic real-time response is preserved.
Data Cache
Data Cache
Data CacheData Cache
For fast, single cycle data access, the RC4640 includes an 8KB onchip data cache that is two-way set associative with a fixed 32-byte
(eight words) line size. Table 4 lists the RC4640 cache attributes.
Characteristics Instruction Data
Size 8KB 8KB
Organization 2-way set associative 2-way set associative
Line size 32B 32B
Index vAddr
Tag pAddr
Write policy n.a. writeback /writethru
Line transfer order read sub-block order read sub-block order
Miss restart after transfer of entire line first word
Parity per-word per-byte
Cache locking set A set A
Table 4 RC4640 Cache Attributes
11..0
31..12
write sequential write sequential
vAddr
pAddr
11..0
31..12
The data cache is protected with byte parity and its tag is protected
with a single parity bit. It is virtually indexed and physically tagged to
allow simultaneous address translation and data cache access
The normal write policy is writeback, which means that a store to a
cache line does not immediately cause memory to be updated. This
increases system performance by reducing bus traffic and eliminating
the bottleneck of waiting for each store operation to finish before issuing
a subsequent memory operation. Software can however select writethrough for certain address ranges, using the CAlg register in CP0.
Cache protocols supported for the data cache are:
◆
Uncached.
Addresses in a memory area indicated as uncached will not be
read from the cache. Stores to such addresses will be written
directly to main memory, without changing cache contents.
◆
Writeback.
Loads and instruction fetches will first search the cache, reading
main memory only if the desired data is not cache resident. On
data store operations, the cache is first searched to see if the
target address is cache resident. If it is resident, the cache con-
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IDT79RC4640™
tents will be updated, and the cache line marked for later writeback. If the cache lookup misses, the target line is first brought
into the cache before the cache is updated.
◆
Write-through with write allocate.
Loads and instruction fetches will first search the cache, reading
main memory only if the desired data is not cache resident. On
data store operations, the cache is first searched to see if the
target address is cache resident. If it is resident, the cache contents will be updated and main memory will also be written; the
state of the “writeback” bit of the cache line will be unchanged. If
the cache lookup misses, the target line is first brought into the
cache before the cache is updated.
◆
Write-through without write-allocate.
Loads and instruction fetches will first search the cache, reading
main memory only if the desired data is not cache resident. On
data store operations, the cache is first searched to see if the
target address is cache resident. If it is resident, the cache contents will be updated, and the cache line marked for later writeback. If the cache lookup misses, then only main memory is
written.
Associated with the Data Cache is the store buffer. When the
RC4640 executes a Store instruction, this single-entry buffer gets written
with the store data while the tag comparison is performed. If the tag
matches, then the data is written into the Data Cache in the next cycle
that the Data Cache is not accessed (the next non-load cycle). The store
buffer allows the RC4640 to execute a store every processor cycle and
to perform back-to-back stores without penalty.
Write Buffer
Write Buffer
Write BufferWrite Buffer
Writes to external memory, whether cache miss writebacks or stores
to uncached or write-through addresses, use the on-chip write buffer.
The write buffer holds up to four address and data pairs. The entire
buffer is used for a data cache writeback and allows the processor to
proceed in parallel with memory update.
System Interface
System Interface
System InterfaceSystem Interface
The RC4640 supports a 32-bit system interface that is syntactically
compatible with the RC4700 system interface.
The interface consists of a 32-bit Address/Data bus with eight check
bits and a 9-bit command bus protected with parity . In addition, ther e are
eight handshake signals and six interrupt inputs. The interface has a
simple timing specification and is capable of transferring data between
the processor and memory at a peak rate of 500MB/sec at 125MHz on
the bus.
Figure 2 on page7 shows a typical system using the RC4640. In this
example two banks of DRAMs are used to supply and accept data with a
DDxxDD data pattern.
The RC4640 clocking interface allows the CPU to be easily mated
with external reference clocks. The CPU input clock is the bus reference
clock, and can be between 50 and 125MHz (somewhat dependent on
maximum pipeline speed for the CPU).
An on-chip phase-locked-loop generates the pipeline clock from the
system interface clock by multiplying it up an amount selected at system
reset. Supported multipliers are values 2 through 8 inclusive, allowing
systems to implement pipeline clocks at significantly higher frequency
than the system interface clock.
System Address/Data Bus
System Address/Data Bus
System Address/Data BusSystem Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to transfer
addresses and data between the RC4640 and the rest of the system. It
is protected with an 8-bit parity check bus, SysADC. When initialized for
32-bit operation, SysAD can be viewed as a 32-bit multiplexed bus, with
4 parity check bits.
The system interface is configurable to allow easier interfacing to
memory and I/O systems of varying frequencies. The bus frequency and
reference timing of the RC4640 are taken from the input clock. The rate
at which the CPU transmits data to the system interface is programmable via boot time mode control bits. The rate at which the processor
receives data is fully controlled by the external device. Therefore, either
a low cost interface requiring no read or write buffering or a faster, high
performance interface can be designed to communicate with the
RC4640. Again, the system designer has the flexibility to make these
price/performance trade-offs.
System Command Bus
System Command Bus
System Command BusSystem Command Bus
The RC4640 interface has a 9-bit System Command (SysCmd) bus.
The command bus indicates whether the SysAD bus carries an address
or data. If the SysAD carries an address, then the SysCmd bus also
indicates what type of transaction is to take place (for example, a read
or write). If the SysAD carries data, then the SysCmd bus also gives
information about the data (for example, this is the last data word transmitted, or the cache state of this data line is clean exclusive). The
SysCmd bus is bidirectional to support both processor requests and
external requests to the RC4640. Processor requests are initiated by
the RC4640 and responded to by an external device. External requests
are issued by an external device and require the RC4640 to respond.
The RC4640 supports single datum (one to eight byte) and 8-word
block transfers on the SysAD bus. In the case of a single-datum
transfer, the low-order 3 address bits gives the byte address of the
transfer, and the SysCmd bus indicates the number of bytes being
transferred.
Handshak e S ignals
Handshak e S ignals
Handshak e S ignalsHandshak e S ignals
There are six handshake signals on the system interface. Two of
these, RdRdy* and WrRdy* are used by an external device to indicate to
the RC4640 whether it can accept a new read or write transaction. The
RC4640 samples these signals before deasserting the address on read
and write requests.
The following is a list of the supported external requests:
◆
Read Response
◆
Null
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IDT79RC4640™
Boot-Time Options
Boot-Time Options
Boot-Time OptionsBoot-Time Options
ExtRqst* and Release* are used to transfer control of the SysAD and
SysCmd buses between the processor and an external device. When an
external device needs to control the interface, it asserts ExtRqst*. The
RC4640 responds by asserting Release* to release the system interface
to slave state.
ValidOut* and ValidIn* are used by the RC4640 and the external
device respectively to indicate that there is a valid command or data on
the SysAD and SysCmd buses. The RC4640 asserts ValidOut* when it
is driving these buses with a valid command or data, and the external
device drives ValidIn* when it has control of the buses and is driving a
valid command or data.
Non-overlapping System Interface
Non-overlapping System Interface
Non-overlapping System InterfaceNon-overlapping System Interface
The RC4640 requires a non-overlapping system interface, compatible with the RC4700. This means that only one processor request may
be outstanding at a time and that the request must be serviced by an
external device before the RC4640 issues another request. The RC4640
can issue read and write requests to an external device, and an external
device can issue read and write requests to the RC4640.
The RC4640 asserts ValidOut* and simultaneously drives the
address and read command on the SysAD and SysCmd buses. If the
system interface has RdRdy* or Read transactions asserted, then the
processor tristates its drivers and releases the system interface to slave
state by asserting Release*. The external device can then begin sending
the data to the RC4640.
Fundamental operational modes for the processor are initialized by
the boot-time mode control interface. The boot-time mode control interface is a serial interface operating at a very low frequency (MasterClock
divided by 256). The low-frequency operation allows the initialization
information to be kept in a low-cost EPROM; alternatively the twenty-orso bits could be generated by the system interface ASIC or a simple
PAL.
Immediately after the VCCOK Signal is asserted, the processor
reads a serial bit stream of 256 bits to initialize all fundamental operational modes. After initialization is complete, the processor continues to
drive the serial clock output, but no further initialization bits are read.
Boot-Time Modes
Boot-Time Modes
Boot-Time ModesBoot-Time Modes
The boot-time serial mode stream is defined in Table 6. Bit 0 is the bit
presented to the processor when VCCOK is asserted; bit 255 is the last.
Power Management
Power Management
Power ManagementPower Management
CP0 is also used to control the power management for the RC4640.
This is the standby mode and it can be used to reduce the power
consumption of the internal core of the CPU. The standby mode is
entered by executing the WAIT instruction with the SysAD bus idle and
is exited by any interrupt.
Standby Mode Operation
Standby Mode Operation
Standby Mode OperationStandby Mode Operation
The RC4640 provides a means to reduce the amount of power
consumed by the internal core when the CPU would otherwise not be
performing any useful operations. This is known as “Standby Mode”.
Entering Standby Mode
Entering Standby Mode
Entering Standby ModeEntering Standby Mode
Executing the WAIT instruction enables interrupts and enters
Standby mode. When the WAIT instruction finishes the W pipe-stage, if
the SysAd bus is currently idle, the internal clocks will shut down, thus
freezing the pipeline. The PLL, internal timer, and some of the input pins
(Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run.
Address
DRAM
(80ns)
Control
SCSI
Memory I/O
Controller
7 of 23 April 10, 2001
ENET
RV4640
Boot
ROM
32
9
2
11
Figure 2 Typical RC4640 System Architecture
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