Integrated Device Technology Inc IDT79RV464080MUI, IDT79RV464080MU, IDT79RV4640133DU, IDT79RV4640100MUI, IDT79RV4640100MU Datasheet
...
1997 Integrated Device Technology, Inc.
1
Integrated Device Technology, Inc.
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE
IDT79R4640
™
IDT79RV4640
™
BLOCK DIAGRAM
FEATURES
• High-performance embedded 64-bit microprocessor
- 64-bit integer operations
- 64-bit registers
- Based on the MIPS RISC Architecture
- 80MHz, 100MHz, 133 MHz and 150MHz operation
frequency
- 32-bit bus interface brings 64-bit power to 32-bit system cost
• High-performance DSP capability
- 75 Million Integer Mul-Accumulate operations/sec
@150MHz
- 50 MFlops floating-point operations @150MHz
• High-performance microprocessor
- 75 M Mul-Add/second @150MHz
- 50 MFlops @150MHz
- >340,000 dhrystone (2.1)/sec capability @133MHz
(197 dhrystone MIPS)
• High level of integration
- 64-bit, 150 MHz integer CPU
- 50MFlops single-precision floating-point unit
- 8KB instruction cache; 8KB data cache
- Integer multiply unit with 75M Mul-Add/sec
• Upwardly software compatible with IDT RISController
Family
• Easily upgradable to 64-bit system
• Low-power operation
- Active power management powers-down inactive
units
- Standby mode
• Large, efficient on-chip caches
- Separate 8KB Instruction and 8KB Data caches
- Over 1800MB/sec bandwidth from internal caches
- 2-set associative
- Write-back and write-through support
- Cache locking to facilitate deterministic response
- High performance write protocols for graphics and
data communications
• Bus compatible with
ORION
family
- System interfaces to 67 MHz, provides bandwidth
up to 266 MB/sec
- Direct interface to 32-bit wide systems
- Synchronized to external reference clock for multi-
master operation
• Improved real-time support
- Fast interrupt decode
- Optional cache locking
150 MHz 64-bit ORION CPU
64-bit Register File
64-bit Adder
Store Aligner
Logic Unit
Load Aligner
High-Performance
Integer Multiply
Pipeline Control
FP Register File
FP Add/Sub/Cvt/
Pack/Unpack
FP Multiply
Pipeline Control
50MFlops Single-Precision FPA
Div/Sqrt
32-bit
Synchronized
System Interface
Address Translation/
Cache Attribute Control
Exception Management
Functions
System Control Coprocessor
Data Cache
Data Cache
Instruction Bus
Control Bus
Data Bus
Set A
(Lockable)
Set B
Instruction Cache
Set B
Instruction Cache
Set A
(Lockable)
LOW-COST EMBEDDED
ORION
™
RISC
MICROPROCESSOR
MAY 1997
The IDT logo is a registered trademark and ORION, R4650, R4640, RV4640, R4600, R3081, R3052, R3051, R3041, R5000, R36100 , RISController, and RISCore
3486/1
Integrated Device Technology, Inc.
are trademarks of
R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE
2
DESCRIPTION
The IDT79R4640 is a low-cost member of the
Integrated Device Technology, Inc.
ORION
family, targeted
to a variety of performance-hungry embedded applications. The R4640 continues the
ORION
tradition of highperformance through high-speed pipelines, high-bandwidth caches and bus interface, 64-bit architecture, and
careful attention to efficient control. The cost of this
performance is reduced by removing functional units
frequently not required for many embedded applications.
The R4640 supports a wide variety of embedded
processor-based applications, such as internetworking
equipment (routers, switches), office automation equipment (printers, scanners), and consumer multimedia
game systems. Also, being upwardly software-compatible
with the RISController family as well as bus- and upw ardly
software-compatible with the IDT
ORION
family, the R4640
will serve in many of the same applications. And, the
R4640 supports applications that require integer digital
signal processing (DSP) functions.
The R4640 brings
ORION
performance levels to lower
cost systems.
ORION
performance is preserved by
retaining large on-chip two-way set-associative caches, a
streamlined high-speed pipeline, high bandwidth, 64-bit
execution, and facilities such as early restart for data
cache misses.
These techniques allow the system designer over 1.8
GB/sec aggregate internal bandwidth, 266 MB/sec bus
bandwidth, almost 200 Dhrystone MIPS, 50MFlops, and
75 M Mul-Add/sec. An array of tools facilitates rapid
development of R4640-based systems, allowing a wide
variety of customers access to the processor’s highperformance capabilities while maintaining short time-tomarket goals.
HARDWARE OVERVIEW
Some key elements of the R4640 are briefly
described below. More detailed information is available in
the
IDT79R4640/IDT79R4650 RISC Processor Hard-
ware User’s Manual
.
Pipeline
The R4640 uses a 5-stage pipeline that is similar to
the IDT79R3000 and the IDT79R4700 processors. The
simplicity of this pipeline allows the R4640 to cost less
than super-scalar processors and require less power than
super-pipelined processors. So, unlike superscalar
processors, applications that have large data dependencies or require a great deal of load/stores can still achieve
peak performance.
Integer Execution Engine
The R4640 implements the MIPS-III Instruction Set
Architecture, and thus is fully upward compatible with
applications running on the earlier generation parts. The
R4640 is software-compatible with the R4650, and
includes the instruction set found in the R4700 microprocessor, targeted at higher performance while maintaining
binary compatibility with earlier R30xx processors. The
extensions result in better code density, greater multiprocessing support, improved performance for commonly
used code sequences in operating system kernels, and
faster execution of floating-point intensive applications. All
resource dependencies are made transparent to the
programmer, insuring transportability among implementations of the MIPS instruction set architecture. In addition,
MIPS-III specifies new instructions defined to take
advantage of the 64-bit architecture of the processor.
Finally, the R4640 also implements additional instructions, which are considered extensions to the MIPS-III
architecture. These instructions improve the multiply and
multiply-add throughput of the CPU, making it well suited
to a wide variety of imaging and DSP applications. These
extensions, which use opcodes allocated by MIPS
Technologies for this purpose, are supported by a wide
variety of development tools.
The MIPS integer unit implements a load/store architecture with single cycle ALU operations (logical, shift,
add, sub) and autonomous multiply/divide unit. The 64-bit
register resources include: 32 general-purpose
orthogonal integer registers, the HI/LO result registers for
the integer multiply/divide unit, and the program counter.
In addition, the on-chip floating-point co-processor adds
32 floating-point registers, and a floating-point
control/status register.
Register File
The R4640 has 32 general-purpose 64-bit registers.
These registers are used for scalar integer operations and
address calculation. The register file consists of two read
ports and one write port and is fully bypassed to minimize
operation latency in the pipeline.
Arithmetic Logic Unit
The R4640 ALU consists of the integer adder and
logic unit. The adder performs address calculations in
addition to arithmetic operations; the logic unit performs
all of the logic and shift operations. Each unit is highly
optimized and can perform an operation in a single pipeline cycle.
Integer Multiply/Divide
The R4640 uses a dedicated integer multiply/divide
unit, optimized for high-speed multiply and multiplyaccumulate operation. Table 1 shows the performance,
expressed in terms of pipeline clocks, achieved by the
R4640 integer multiply unit.
R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE
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The MIPS-III architecture defines that the results of a
multiply or divide operation are placed in the HI and LO
registers. The values can then be transferred to the
general purpose register file using the MFHI/MFLO
instructions.
The R4640 adds a new multiply instruction, “MUL”,
which can specify that the multiply results bypass the “Lo”
register and are placed immediately in the primary
register file. By avoiding the explicit “Move-from-Lo”
instruction required when using “Lo”, throughput of
multiply-intensive operations is increased.
An additional enhancement offered by the R4640 is an
atomic “multiply-add” operation, MAD, used to perform
multiply-accumulate operations. This instruction multiplies
two numbers and adds the product to the current contents
of the HI and LO registers. This operation is used in
numerous DSP algorithms, and allows the R4640 to cost
reduce systems requiring a mix of DSP and control
functions.
Finally, aggressive implementation techniques feature
low latency for these operations along with pipelining to
allow new operations to be issued before a previous one
has fully completed. Table 1 also shows the repeat rate
(peak issue rate), latency, and number of processor stalls
required for the various operations. The R4640 performs
automatic operand size detection to determine the size of
the operand, and implements hardware interlocks to
prevent overrun, allowing this high-performance to be
achieved with simple programming.
Floating-Point Coprocessor
The R4640 incorporates an entire single-precision
floating-point coprocessor on chip, including a floatingpoint register file and execution units. The floating-point
coprocessor forms a “seamless” interface with the integer
unit, decoding and executing instructions in parallel with
the integer unit.
Opcode Operand
Size
Latency Repeat Stall
MULT/U,
MAD/U
16 bit 3 2 0
32 bit 4 3 0
MUL 16 bit 3 2 1
32 bit 4 3 2
DMULT,
DMULTU
any 6 5 0
DIV, DIVU any 36 36 0
DDIV,
DDIVU
any 68 68 0
Table 1: R4640 Integer Multiply Operation
The floating-point unit of the R4640 directly implements single-precision floating-point operations, which
enables the R4640 to perform functions such as graphics
rendering without requiring extensive die area or power
consumption. The single-precision unit of the R4640 is
directly compatible with the single-precision operation of
the R4700, and features the same latencies and repeat
rates.
The R4640 does not directly implement the doubleprecision operations found in the R4700. However, to
maintain software compatibility, the R4640 will signal a
trap when a double-precision operation is initiated,
allowing the requested function to be emulated in
software. Alternatively, the system architect could use a
software library emulation of double-precision functions,
selected at compile time, to eliminate the overhead
associated with trap and emulation.
Floating-Point Units
The R4640’s floating-point execution units perform
single precision arithmetic, as specified in IEEE Standard
754. The execution unit is broken into a separate multiply
unit and a combined add/convert/divide/square root unit.
Overlap of multiply and add/subtract is supported. The
multiplier is partially pipelined, allowing a new multiplication instruction to begin every 6 cycles.
As in the IDT79R4700, the R4640 maintains fully
precise floating-point exceptions while allowing both
overlapped and pipelined operations. Precise exceptions
are extremely important in mission-critical environments,
such as ADA, and highly desirable for debugging in any
environment.
The floating-point unit’s operation set includes floatingpoint add, subtract, multiply, divide, square root,
conversion between fixed-point and floating-point format,
conversion among floating-point formats, and floatingpoint compare. These operations comply with IEEE
Standard 754. Double precision operations are not
directly supported; attempts to execute double-precision
floating point operations, or refer directly to doubleprecision registers, result in the R4640 signalling a “trap”
to the CPU, enabling emulation of the requested function.
R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE
4
Table 2 gives the latencies of some of the floating-point
instructions in internal processor cycles.
Floating-Point General Register File
The floating-point register file is made up of thirty-two
32-bit registers. These registers are used as source or
target registers for the single-precision operations.
References to these registers as 64-bit registers (as
supported in the R4700) will cause a trap to be signalled
to the integer unit.
The floating-point control register space contains two
registers; one for determining configuration and revision
information for the coprocessor and one for control and
status information. These are primarily involved with
diagnostic software, exception handling, state saving and
restoring, and control of rounding modes.
System Control Coprocessor (CP0)
The system control coprocessor in the MIPS architecture is responsible for the virtual to physical address
translation and cache protocols, the exception control
system, and the diagnostics capability of the processor. In
the MIPS architecture, the system control coprocessor
(and thus the kernel software) is implementation
dependent.
In the R4640, significant changes in CP0 relative to the
R4600 have been implemented. These changes are
designed to simplify memory management, facilitate
debug, and speed real-time processing.
Operation
Instruction
Latency
ADD 4
SUB 4
MUL 8
DIV 32
SQRT 31
CMP 3
FIX 4
FLOAT 6
ABS 1
MOV 1
NEG 1
LWC1 2
SWC1 1
Table 2: Floating-Point Operation
System Control Coprocessor Registers
The R4640 incorporates all system control coprocessor (CP0) registers on-chip. These registers
provide the path through which the virtual memory
system’s address translation is controlled, exceptions are
handled, and operating modes are controlled (kernel vs.
user mode, interrupts enabled or disabled, cache
features). In addition, the R4640 includes registers to
implement a real-time cycle counting facility, which aids in
cache diagnostic testing, assists in data error detection,
and facilitates software debug. Alternatively, this timer
can be used as the operating system reference timer, and
can signal a periodic interrupt.
Table 3 shows the CP0 registers of the R4640.
Operation modes
The R4640 supports two modes of operation: user
mode and kernel mode.
Kernel mode operation is typically used for exception
handling and operating system kernel functions, including
Number Name Function
0 IBase Instruction address space base (new in
R4640)
1 IBound Instruction address space bound (new
in R4640)
2 DBase Data address space base (new in
R4640)
3 DBound Data address space bound (new in
R4640)
4-7, 10,
20-25,
29, 31
- Not used
8 BadVAddr Virtual address on address exceptions
9 Count Counts every other cycle
11 Compare Generate interrupt when Count =
Compare
12 Status Miscellaneous control/status
13 Cause Exception/Interrupt information
14 EPC Exception PC
15 PRId Processor ID
16 Config Cache and system attributes
17 CAlg Cache attributes for the 8 512MB
regions of the virtual address space
18 IWatch Instruction breakpoint virtual address
19 DWatch Data breakpoint virtual address
26 ECC Used in cache diagnostics
27 CacheErr Cache diagnostic information
28 TagLo Cache index information
30 ErrorEPC CacheError exception PC
Table 3: R4640 CPO Registers
R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE
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CP0 management and access to IO devices. In kernel
mode, software has access to the entire address space
and all of the co-processor 0 registers, and can select
whether to enable co-processor 1 accesses. The
processor enters kernel mode at reset, and whenever an
exception is recognized.
User mode is typically used for applications programs.
User mode accesses are limited to a subset of the virtual
address space, and can be inhibited from accessing CP0
functions.
Virtual-to-Physical Address Mapping
The 4GB virtual address space of the R4640 is shown
in figure 3. The 4 GB address space is divided into
addresses accessible in either kernel or user mode
(kuseg), and addresses only accessible in kernel mode
(kseg2:0).
The R4640 supports the use of multiple user tasks
sharing common virtual addresses, but mapped to
separate physical addresses. This facility is implemented
via the “base-bounds” registers contained in CP0.
When a user virtual address is asserted (load, store, or
instruction fetch), the R4640 compares the virtual address
with the contents of the appropriate “bounds” register
(instruction or data). If the virtual address is “in bounds”,
the value of the corresponding “base” register is added to
0xFFFFFFFF
0xC0000000
Kernel virtual address space
(kseg2)
Unmapped, 1.0 GB
0xBFFFFFFF
0xA0000000
Uncached kernel physical address space
(kseg1)
Unmapped, 0.5GB
0x9FFFFFFF
0x80000000
Cached kernel physical address space
(kseg0)
Unmapped, 0.5GB
0x7FFFFFF
0x00000000
User virtual address space
(useg)
Mapped, 2.0GB
Figure 3: Mode Virtual Addressing (32-bit mode)
the virtual address to form the physical address for that
reference. If the address is not within bounds, an
exception is signalled.
This facility enables multiple user processes in a single
physical memory without the use of a TLB. This type of
operation is further supported by a number of development tools for the R4640, including real-time operating
systems and “position independent code”.
Kernel mode addresses do not use the base-bounds
registers, but rather undergo a fixed virtual to physical
address translation.
Debug Support
To facilitate software debug, the R4640 adds a pair of
“watch” registers to CP0. When enabled, these registers
will cause the CPU to take an exception when a
“watched” address is appropriately accessed.
Interrupt Vector
The R4640 also adds the capability to speed interrupt
exception decoding. Unlike the R4700, which utilizes a
single common exception vector for all exception types
(including interrupts), the R4640 allows kernel software to
enable a separate interrupt exception vector. When
enabled, this vector location speeds interrupt processing
by allowing software to avoid decoding interrupts from
general purpose exceptions.
Cache Memory
To keep the R4640’s high-performance pipeline full and
operating efficiently, the R4640 incorporates on-chip
instruction and data caches that can each be accessed in
a single processor cycle. Each cache has its own 64-bit
data path and can be accessed in parallel. The cache
subsystem provides the integer and floating-point units
with an aggregate bandwidth of over 1800 MB per second
at a pipeline clock frequency of 150MHz. The cache
subsystem is similar in construction to that found in the
R4600, although some changes have been implemented.
Table 6 is an overview of the caches found on the R4640.
Instruction Cache
The R4640 incorporates a two-way set associative onchip instruction cache. This virtually indexed, physically
tagged cache is 8KB in size and is parity protected.
Because the cache is virtually indexed, the virtual-tophysical address translation occurs in parallel with the
cache access, thus further increasing performance by
allowing these two operations to occur simultaneously.
The tag holds a 20-bit physical address and valid bit, and
is parity protected.
The instruction cache is 64-bits wide, and can be
refilled or accessed in a single processor cycle.
Instruction fetches require only 32 bits per cycle, for a
peak instruction bandwidth of 600MB/sec at 150MHz.
Sequential accesses take advantage of the 64-bit fetch to
reduce power dissipation, and cache miss refill, can write
R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE
6
64 bits-per-cycle to minimize the cache miss penalty. The
line size is eight instructions (32 bytes) to maximize
performance.
In addition, the contents of one set of the instruction
cache (set “A”) can be “locked” by setting a bit in a CP0
register. Locking the set prevents its contents from being
overwritten by a subsequent cache miss; refill occurs then
only into “set B”.
This operation effectively “locks” time critical code into
one 4kB set, while allowing the other set to service other
instruction streams in a normal fashion. Thus, the benefits
of cached performance are achieved, while deterministic
real-time response is preserved.
Data Cache
For fast, single cycle data access, the R4640 includes
an 8KB on-chip data cache that is two-way set
associative with a fixed 32-byte (eight words) line size.
Table 4 lists the R4640 cache attributes.
The data cache is protected with byte parity and its tag
is protected with a single parity bit. It is virtually indexed
and physically tagged to allow simultaneous address
translation and data cache access
The normal write policy is writeback, which means that
a store to a cache line does not immediately cause
memory to be updated. This increases system performance by reducing bus traffic and eliminating the
bottleneck of waiting for each store operation to finish
before issuing a subsequent memory operation. Software
can however select write-through for certain address
ranges, using the CAlg register in CP0. Cache protocols
supported for the data cache are:
• Uncached . Addresses in a memory area indicated as
uncached will not be read from the cache. Stores to
such addresses will be written directly to main memory,
Characteristics Instruction Data
Size
8KB 8KB
Organization
2-way set associative
2-way set associative
Line size
32B 32B
Index
vAddr
11..0
vAddr
11..0
Tag
pAddr
31..12
pAddr
31..12
Write policy
n.a. writeback /writethru
Line transfer order
read sub-block
order
read sub-block
order
write sequential write sequential
Miss restart after
transfer of
entire line first word
Parity
per-word per-byte
Cache locking
set A set A
Table 4: R4640 Cache Attributes
without changing cache contents.
• Writeback . Loads and instruction fetches will first
search the cache, reading main memory only if the
desired data is not cache resident. On data store oper ations, the cache is first searched to see if the target
address is cache resident. If it is resident, the cache
contents will be updated, and the cache line marked for
later writeback. If the cache lookup misses, the target
line is first brought into the cache before the cache is
updated.
• Write-through with write allocate. Loads and instruction fetches will first search the cache, reading main
memory only if the desired data is not cache resident.
On data store operations, the cache is first searched to
see if the target address is cache resident. If it is resident, the cache contents will be updated and main
memory will also be written; the state of the “writeback”
bit of the cache line will be unchanged. If the cache
lookup misses, the target line is first brought into the
cache before the cache is updated.
• Write-through without write-allocate. Loads and
instruction fetches will first search the cache, reading
main memory only if the desired data is not cache resident. On data store operations, the cache is first
searched to see if the target address is cache resident.
If it is resident, the cache contents will be updated, and
the cache line marked for later writeback. If the cache
lookup misses, then only main memory is written.
Associated with the Data Cache is the store buffer.
When the R4640 executes a Store instruction, this singleentry buffer gets written with the store data while the tag
comparison is performed. If the tag matches, then the
data is written into the Data Cache in the next cycle that
the Data Cache is not accessed (the next non-load cycle).
The store buffer allows the R4640 to execute a store
every processor cycle and to perform back-to-back stores
without penalty.
Write buffer
Writes to external memory, whether cache miss write-
backs or stores to uncached or write-through addresses,
use the on-chip write buffer. The write buffer holds up to
four address and data pairs. The entire buffer is used for
a data cache writeback and allows the processor to
proceed in parallel with memory update. For uncached
and write-through stores, the write buffer significantly
increases performance over the R4000 family of
processors.
System Interface
The R4640 supports a 64-bit system interface that is
bus compatible with the R4700 system interface. In
addition, the R4640 supports a 32-bit system interface
mode, allowing the CPU to interface directly with a lower
cost memory system.
R4640/RV4640 COMMERCIAL/INDUSTRIAL TEMPERATURE RANGE
7
The interface consists of a 64-bit Address/Data bus with
8 check bits and a 9-bit command bus protected with
parity. In addition, there are 8 handshake signals and 6
interrupt inputs. The interface has a simple timing specification and is capable of transferring data between the
processor and memory at a peak rate of 533MB/sec at
133MHz.
Figure 4 shows a typical system using the R4640. In
this example two banks of DRAMs are used to supply and
accept data with a DDxxDD data pattern.
The R4640 clocking interface allows the CPU to be
easily mated with external reference clocks. The CPU
input clock is the bus reference clock, and can be
between 25 and 67MHz (somewhat dependent on
maximum pipeline speed for the CPU).
An on-chip phase-locked-loop generates the pipeline
clock from the system interface clock by multiplying it up
an amount selected at system reset. Supported multipliers are values 2 through 8 inclusive, allowing systems
to implement pipeline clocks at significantly higher
frequency than the system interface clock.
System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used
to transfer addresses and data between the R4640 and
the rest of the system. It is protected with an 8-bit parity
check bus, SysADC. When initialized for 32-bit operation,
SysAD can be viewed as a 32-bit multiplexed bus, with 4
parity check bits.
The system interface is configurable to allow easier
interfacing to memory and I/O systems of varying
frequencies. The bus frequency and reference timing of
the R4640 are taken from the input clock. The rate at
which the CPU transmits data to the system interface is
programmable via boot time mode control bits. The rate at
which the processor receives data is fully controlled by
the external device. Therefore, either a low cost interface
requiring no read or write buffering or a faster, high performance interface can be designed to communicate with
the R4640. Again, the system designer has the flexibility
to make these price/performance trade-offs.
System Command Bus
The R4640 interface has a 9-bit System Command
(SysCmd) bus. The command bus indicates whether the
SysAD bus carries an address or data. If the SysAD
carries an address, then the SysCmd bus also indicates
what type of transaction is to take place (for example, a
read or write). If the SysAD carries data, then the SysCmd
bus also gives information about the data (for example,
this is the last data word transmitted, or the cache state of
this data line is clean exclusive). The SysCmd bus is
bidirectional to support both processor requests and
external requests to the R4640. Processor requests are
initiated by the R4640 and responded to by an external
device. External requests are issued by an external
device and require the R4640 to respond.
The R4640 supports single datum (one to eight byte)
and 8-word block transfers on the SysAD bus. In the case
of a single-datum transfer, the low-order 3 address bits
gives the byte address of the transfer, and the SysCmd
bus indicates the number of bytes being transferred. The
choice of 32- or 64-bit wide system interface dictates
whether a cache line block transaction requires 4 double
RV4640
Memory I/O
Controller
Control
Address
SCSI
ENET
32
9
Boot
ROM
DRAM
(80ns)
2
11
Figure 4: Typical R4640 System Architecture
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