IDT IDT74LVCH16501A User Manual

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IDT74LVCH16501A

3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O

INDUSTRIAL TEMPERATURE RANGE

3.3V CMOS 18-BIT
REGISTERED BUS TRANSCEIVER
WITH 5V TOLERANT I/O
AND BUS-HOLD

FEA TURES:

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)

•VCC = 3.3V ± 0.3V, Normal Range

•VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

• Available in SSOP, TSSOP, and TVSOP packages

DRIVE FEA TURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICA TIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

µµ

µ W typ. static)

µµ

IDT74LVCH16501A

DESCRIPTION:

This 18-bit registered transceiver is built using advanced dual metal
CMOS technology. This high-speed, low power 18-bit registered bus
transceiver combines D-type latches and D-type flip-flops to allow data flow
in transparent latched and clocked modes. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch enable (LEAB and
LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in transparent mode when LEAB is high. When LEAB is
low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB
is low, the A bus data is stored in the latch/flip-flop on the low-to-high transition
of CLKAB. OEAB performs the output enable function on the B port. Data
flow from B port to A port is similar but requires using OEBA, LEBA and
CLKBA. Flow-through organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.

The LVCH16501A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.

The LVCH16501A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.

FUNCTIONAL BLOCK DIAGRAM

A1

1

30

28

27

55

2

3

OEAB

CLKBA

LEBA

OEBA

CLKAB

LEAB

C
D

C
D

C
D

C
D

54

B1

TO 17 OTHER CHANNELS

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

OCTOBER 1999INDUSTRIAL TEMPERATURE RANGE

© 1999 Integrated Device Technology, Inc. DSC-3688/1

1

IDT74LVCH16501A

3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O

INDUSTRIAL TEMPERATURE RANGE

PIN CONFIGURATION

OEAB

LEAB

A1

GND

A
A3

VCC

A4
A5

A

GND

A7
A8

A9

A
A11
A12

GND

A13
A14

A15

VCC

A
A17

GND

A18

OEBA

LEBA

2
3
4

5

2

6
7

8
9
10

6

11
12
13
14

10

16

15
16
17

18
19

20
21
22
23

24
25
26
27

28

SSOP/ TSSOP/ TVSOP

TOP VIEW

561
55
54
53
52

51
50

48
47
46

45
44
43

42
41
40

38
37
36
35
34
33

32
31
30
29

49

39

GND
CLKAB
B

1

GND
B2

B

3

VCC
B4

B5
B6
GND

7

B
B8

B9
B10

11

B
B12
GND

B13
B14

15

B
VCC

B16
B

17

GND
B

18

CLKBA
GND

PIN DESCRIPTION

Pin Names Description

OEAB A-to-B Output Enable Input
OEBA B-to-A Output Enable Input (Active LOW)

LEAB A-to-B Latch Enable Input

LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input

Ax A-to-B Data Inputs or B-to-A 3-State Outputs
Bx B-to-A Data Inputs or A-to-B 3-State Outputs

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

(1)

(1)

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Description Max Unit

VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –50 to +50 mA
I

IK Continuous Clamp Current, –50 mA

IOK VI < 0 or VO < 0
I

CC Continuous Current through each ±100 mA

ISS VCC or GND

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol Parameter

CIN Input Capacitance VIN = 0V 4.5 6 pF
COUT Output Capacitance VOUT = 0V 6.5 8 pF
C

I/O I/O Port Capacitance VIN = 0V 6.5 8 pF

NOTE:

1. As applicable to the device type.

FUNCTION TABLE

OEAB LEAB CLKAB Ax Bx

LXXX Z
HH X L L
HH X H H
HL ↑ LL
HL ↑ HH
HL L X B
HL H X B

NOTES:

1. A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, and
CLKBA.

2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition

3. Output level before the indicated steady-state input conditions were established.

4. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.

2

(1)

Conditions Typ. Max. Unit

(1,2)

Inputs Output

(3)
(4)

IDT74LVCH16501A

3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O

INDUSTRIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C

Symbol Parameter Test Conditions Min. Typ.

V

IH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V

VCC = 2.7V to 3.6V 2 — —

IL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V

V

VCC = 2.7V to 3.6V — — 0.8

IH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5µA

I

IIL
IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA
IOZL (3-State Output pins)
IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 µA

VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V
VH Input Hysteresis VCC = 3.3V — 100 — mV

I

CCL Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC —— 10µA

ICCH
ICCZ 3.6 ≤ VIN ≤ 5.5V

(2)

—— 10

∆ICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 500 µA

Variation

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

(1)

Max. Unit

BUS-HOLD CHARACTERISTICS

Symbol Parameter

(1)

Test Conditions Min. Typ.

IBHH Bus-Hold Input Sustain Current VCC = 3V VI = 2V – 75 — — µA
IBHL VI = 0.8V 75 — —
IBHH Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V — — — µ A
IBHL VI = 0.7V — — —

IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V — — ±500 µA
IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

3

(2)

Max. Unit