IDT IDT74LC374A User Manual
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IDT74LVC374A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS OCTAL
EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
FEA TURES:
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4
• Rail-to-rail output swing for increased noise margin
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SOIC, SSOP, QSOP, and TSSOP packages
DRIVE FEA TURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICA TIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
µµ
µ W typ. static)
µµ
IDT74LVC374A
DESCRIPTION:
The LVC374A octal edge triggered D-type flip-flop is built using advanced
dual metal CMOS technology. This device features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads.
The LVC374A device is particularly suitable for implementing buffer registers, input-output (I/O) ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set
to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide
the capability to drive bus lines without interface or pullup components. OE
does not affect internal operations of the latch. Old data can be retained or
new data can be entered while the outputs are in the high-impedance state.
The LVC374A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
CC through a pullup resistor; the minimum value of the
FUNCTIONAL BLOCK DIAGRAM
1D
1
11
C1
3
TO SEVEN OTHER CHANNELS
D
1
2
1Q
APRIL 1999INDUSTRIAL TEMPERATURE RANGE
1
OE
CLK
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 1999 Integrated Device Technology, Inc. DSC-4618/2
IDT74LVC374A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
20
19
18
17
16
15
14
13
12
11
CC
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
ABSOLUTE MAXIMUM RATINGS
Symbol Description Max Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –50 to +50 mA
I
IK Continuous Clamp Current, –50 mA
IOK VI < 0 or VO < 0
I
CC Continuous Current through each ±100 mA
ISS VCC or GND
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
(1)
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol Parameter
CIN Input Capacitance VIN = 0V 4.5 6 pF
COUT Output Capacitance VOUT = 0V 5.5 8 pF
C
I/O I/O Port Capacitance VIN = 0V 6.5 8 pF
NOTE:
1. As applicable to the device type.
(1)
Conditions Typ. Max. Unit
PIN DESCRIPTION
Pin Names Description
OE Output Enable Input (Active LOW)
CLK Clock Input
xD Data Inputs
xQ Data Outputs
FUNCTION T ABLE (EACH FLIP-FLOP)
Inputs Outputs
xD CLK OE xQ
H ↑ LH
L ↑ LL
X H or L L Q
XXH Z
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
↑ = LOW-to-HIGH Transition
2. Output level before the indicated steady-state input conditions were established.
(1)
(2)
2
IDT74LVC374A
3.3V CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol Parameter Test Conditions Min. Typ.
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
IL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
V
VCC = 2.7V to 3.6V — — 0.8
IH Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5µA
I
IIL
IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 µA
IOZL (3-State Output pins)
IOFF Input/Output Power Off Leakage VCC = 0V, V IN or VO ≤ 5.5V — — ±50 µA
VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V
VH Input Hysteresis VCC = 3.3V — 100 — mV
I
CCL Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC ——10µA
ICCH
ICCZ 3.6 ≤ VIN ≤ 5.5V
(2)
—— 10
∆ICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 500 µA
Variation
(1)
Max. Unit
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
VCC = 2.3V IOH = – 6mA 2 —
VCC = 2.3V IOH = – 12mA 1.7 —
VCC = 2.7V 2.2 —
VCC = 3V 2.4 —
VCC = 3V IOH = – 24mA 2.2 —
VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V
VCC = 2.3V IOL = 6mA — 0.4
VCC = 2.7V IOL = 12mA — 0.4
VCC = 3V IOL = 24mA — 0.55
(1)
Min. Max. Unit
IOL = 12mA — 0.7
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3