Integrated Device Technology Inc IDT74FST16163233PV, IDT74FST16163233PF, IDT74FST16163233PA Datasheet
Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• Bus switches provide zero delay paths
• Extended commercial range of –40°C to +85°C
• Low switch on-resistance:
FST163xxx – 7Ω
• TTL-compatible input and output levels
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in SSOP, TSSOP and TVSOP
COMMERCIAL TEMPERATURE RANGE AUGUST 1996
1996 Integrated Device Technology, Inc. DSC-3512/1
1
IDT74FST163233
ADVANCE INFORMATION
16-BIT 2:1 MUX/DEMUX
SWITCH
their own while providing a low resistance path for an external
driver. These devices connect input and output ports through
an n-channel FET. When the gate-to-source junction of this
FET is adequately forward-biased the device conducts and
the resistance between input and output ports is small. Without adequate bias on the gate-to-source junction of the FET,
the FET is turned off, therefore with no VCC applied, the device
has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
The FST163233 provides three 16-bit TTL-compatible
ports that support 2:1 multiplexing. The SEL
0,1 and TEST0,1
pins provide switch enable and mux select control as shown
below.
The A port can be connected to port 1B or port 2B or both
ports 1B and 2B.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
SEL0
One of Eight
Channels
TEST0
0A
1-8
2B1-
8
1B1-
8
SEL1
One of Eight
Channels
TEST1
1A
9-16
2B9-
16
1B9-
16
Pin Names I/O Description
A, 1B, 2B I/O Buses A, 1B, 2B
SEL
0-1,
TEST
0-1
I Control Pins for Mux and Switch
Enable Functions
3512 tbl 01
3512 drw 01
DESCRIPTION:
The FST163233 belongs to IDT's family of Bus switches.
Bus switch devices perform the function of connecting or
isolating two ports without providing any inherent current sink
or source capability. Thus they generate little or no noise of
2
IDT74FST163233
16-BIT 2:1 MUX/DEMUX SWITCH COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
PIN CONFIGURATION
FUNCTION TABLE
SSOP/
TSSOP/TVSOP
TOP VIEW
5
6
7
8
9
10
1
2
3
4
54
53
52
51
50
49
48
47
46
45
0A
7
1B2
2B2
0A3
1B4
2B4
0A5
1B6
2B6
0A2
1B3
2B3
0A4
1B5
0A6
1B7
1B1
2B1
1B8
11
12
55
56
2B
8
2B7
0A8
17
18
19
20
21
22
13
14
15
16
42
41
40
39
38
37
36
35
34
33
1B
14
VCC
1A9
1B10
GND
2B
10
1A11
1B12
2B12
1A13
1B9
2B9
1A10
1B11
2B11
1A12
1B13
2B13
GND
V
CC
SO56-1
SO56-2
SO56-3
2B
14
23
24
43
44
1A
15
1A14
1B15
25
26
32
31
30
29
2B
16
1B16 2B15
1A16
TEST0
27
28
TEST
1
SEL0
SEL1
0A1
2B5
SEL
0
TEST
0
Function
L L 0A to 1B
H
L
0A to 2B
X H 0A to 1B and
0A to 2B
SEL
1
TEST
1
Function
L L 1A to 1B
H L 1A to 2B
X H 1A to 1B and
1A to 2B
3512 drw 02
3512 tbl 04
Symbol Description Max. Unit
VTERM
(2)
Terminal Voltage with Respect
to GND
–0.5 to +7.0 V
TSTG Storage Temperature –65 to +150 °C
IOUT Maximum Continuous Channel
Current
128 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating condiitions for extended
periods may affect reliability.
2. V
CC, Control and Switch terminals.
3512 tbl 02
CAPACITANCE
(1)
Symbol Parameter Conditions
(2)
Typ. Unit
CIN Control Input Capacitance 4 pF
CI/O
Switch Input/Output
Capacitance
Switch Off
pF
3512 tbl 03
NOTES:
1. Capacitance is characterized but not tested
2. T
A = 25°C, f = 1MHz, VIN = 0V, VOUT = 0V
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