Integrated Device Technology Inc IDT74FST16163214PV, IDT74FST16163214PF, IDT74FST16163214PA Datasheet
Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• Bus switches provide zero delay paths
• Extended commercial range of –40°C to +85°C
• Low switch on-resistance:
FST163xxx – 4Ω
• TTL-compatible input and output levels
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in SSOP, TSSOP and TVSOP
COMMERCIAL TEMPERATURE RANGE AUGUST 1996
1996 Integrated Device Technology, Inc. DSC-3509/1
1
IDT74FST163214
ADVANCE INFORMATION
12-BIT 3:1 MUX/DEMUX
SWITCH
their own while providing a low resistance path for an external
driver. These devices connect input and output ports through
an n-channel FET. When the gate-to-source junction of this
FET is adequately forward-biased the device conducts and
the resistance between input and output ports is small. Without adequate bias on the gate-to-source junction of the FET,
the FET is turned off, therefore with no VCC applied, the device
has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
The FST163214 provides a 12-bit TTL- compatible A port
and three 12-bit TTL compatible B ports. The S
0-2 pins
provide mux select and disable control. The A port can be
connected to any one of the three B ports by selecting
appropriate S0-2 states.
DESCRIPTION:
The FST163214 belong to IDT's family of Bus switches.
Bus switch devices perform the function of connecting or
isolating two ports without providing any inherent current sink
or source capability. Thus they generate little or no noise of
1A1
1B3
1
B1
1
B2
S0
S1
S2
Flow Control
1 of 12 Channels
FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION
3209 drw 01
3209 tbl 01
Pin Names I/O Description
A1 I/O Bus A1
B1, B2, B3 I/O Buses B1, B2, B3
S0-2 I Select Lines
2
IDT74FST163214
12-BIT 3:1 MUX/DEMUX SWITCH COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
PIN CONFIGURATION
FUNCTION TABLE
5
6
7
8
9
10
1
2
3
4
54
53
52
51
50
49
48
47
46
45
4B
3
1A
1
1B
3
2A
1
S0
2B
3
3B
3
GND
4A
1
1B
1
1B
2
2B
1
2B
2
3B
1
GND
3B
2
4B
1
SI
S2
5A
1
11
12
55
56
5B
3
4B
2
5B
1
17
18
19
20
21
22
13
14
15
16
42
41
40
39
38
37
36
35
34
33
9B
3
6B
3
7A
1
7B
3
6A
1
V
CC
8A
1
GND
8B
3
9A
1
6B
2
7B
1
7B
2
8B
1
GND
8B
2
9B
1
9B
2
5B
2
6B
1
SO56-1
SO56-2
SO56-3
10A
1
23
24
43
44
10B
3
10B
1
10B
2
25
26
32
31
30
29
11B
3
11A
1
11B
1
11B
2
12A
1
27
28
12B
3
12B
1
12B
2
3A
1
SSOP/
TSSOP/TVSOP
TOP VIEW
3209 drw 02
3209 tbl 04
S2 S1 S0 A1 Function
L L L Z Disconnect
LLHB1 A to B1
LHLB2 A to B2
L H H Z Disconnect
H L L Z Disconnect
HLHB3 A to B3
HHLB1 A to B1
HHHB2 A to B2
Symbol Description Max. Unit
VTERM
(2)
Terminal Voltage with Respect
to GND
–0.5 to +7.0 V
TSTG Storage Temperature –65 to +150 °C
IOUT Maximum Continuous Channel
Current
128 mA
3209 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating condiitions for extended
periods may affect reliability.
2. V
CC, Control and Switch terminals.
3209 tbl 03
NOTES:
1. Capacitance is characterized but not tested
2. T
A = 25°C, f = 1MHz, VIN = 0V, VOUT = 0V
CAPACITANCE
(1)
Symbol Parameter Conditions
(2)
Typ. Unit
CIN Control Input Capacitance 4 pF
CI/O
Switch Input/Output
Capacitance
Switch Off
pF
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