Integrated Device Technology Inc IDT74FCT88915TT133PYB, IDT74FCT88915TT133LB, IDT74FCT88915TT133L, IDT74FCT88915TT133JB, IDT74FCT88915TT133J Datasheet

IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

LOW SKEW PLL-BASED
CMOS CLOCK DRIVER

Integrated Device Technology, Inc.

FEATURES:

• 0.5 MICRON CMOS Technology

• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)

• Max. output frequency: 133MHz

• Pin and function compatible with MC88915T

• 5 non-inverting outputs, one inverting output, one 2x
output, one ÷2 output; all outputs are TTL-compatible

• 3-State outputs

• Output skew < 500ps (max.)

• Duty cycle distortion < 500ps (max.)

• Part-to-part skew: 1ns (from t

PD max. spec)

• TTL level output voltage swing

• 64/–15mA drive at TTL output voltage levels

• Available in 28 pin PLCC, LCC and SSOP packages

DESCRIPTION:

The IDT54/74FCT88915TT uses phase-lock loop technol­ogy to lock the frequency and phase of outputs to the input
reference clock. It provides low skew clock distribution for
high performance PCs and workstations. One of the outputs

(WITH 3-STATE)

IDT54/74FCT88915TT

55/70/100/133

PRELIMINARY

is fed back to the PLL at the FEEDBACK input resulting in
essentially delay across the device. The PLL consists of the
phase/frequency detector, charge pump, loop filter and VCO.
The VCO is designed for a 2Q operating frequency range of
40MHz to f2Q Max.

The IDT54/74FCT88915TT provides 8 outputs with 500ps
skew. The
runs at twice the Q frequency and Q/2 runs at half the Q
frequency.

The FREQ_SEL control provides an additional ÷ 2 option in
the output path. PLL _EN allows bypassing of the PLL, which
is useful in static test modes. When PLL_EN is low, SYNC
input may be used as a test clock. In this test mode, the input
frequency is not limited to the specified range and the polarity
of outputs is complementary to that in normal operation
(PLL_EN = 1). The LOCK output attains logic HIGH when the
PLL is in steady-state phase and frequency lock. When OE/
RST is low, all the outputs are put in high impedance state and
registers at Q, Q and Q/2 outputs are reset.

The IDT54/74FCT88915TT requires one external loop
filter component as recommended in Figure 1.

Q5 output is inverted from the Q outputs. The 2Q

FUNCTIONAL BLOCK DIAGRAM

FEEDBACK

SYNC (0)

SYNC (1)

0

M
u
x

1

Phase/Freq.
Detector

Charge Pump

Voltage
Controlled
Oscilator

REF_SEL

PLL_EN

FREQ_SEL

OE/RST

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

01

Mux

Divide

-By-2

(

(

÷1)

÷2)

1

M
u
x

0

D

D
CP

CP

D
CP

D

CP

D

CP

D

CP

D

CP

D
CP

Q

Q

Q

Q

R

Q

R

Q

R

Q

R

Q

R

Q

R

Q

R

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995

1995 Integrated Device Technology, Inc. 9.7 DSC-4247/1

9.7 1

LOCK

LF

2Q
Q0

Q1

Q2

Q3

Q4

Q5

Q/2

3072 drw 01

1

IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

FEEDBK

REF_SEL

SYNC(0)

V

CC

(AN)

LF

GND(AN)

SYNC(1)

CC

OE/RST

Q5

V

GND

Q4

284 3 2 1 27 26

5
6
7
8

J28-1,
L28-1

9
10
11

12 13 14 15 16 17 18

CC

GND

Q0

Q1

V

FREQ_SEL

PLCC/LCC

TOP VIEW

CC

V

GND

2Q

25
24
23
22
21
20
19

PLL_EN

3072 drw 02

Q/2
GND
Q3
V

CC

Q2
GND
LOCK

GND

Q5

V

CC

OE/RST

FEEDBACK

REF_SEL

SYNC(0)

V

CC

(AN)

LF

GND(AN)

SYNC(1)

FREQ_SEL

GND

Q0

1
2
3
4

5
6
7
8
9
10
11

12
13

SO28-7

SSOP

TOP VIEW

28
27
26

25
24
23

22
21
20
19
18
17

16
1514

Q4

CC

V

2Q

Q/2

GND

Q3

V

CC

Q2
GND

LOCK

PLL_EN
GND

Q1

CC

V

3072 drw 03

PIN DESCRIPTION

Pin Name I/O Description

SYNC(0) I Reference clock input.
SYNC(1) I Reference clock input.
REF_SEL I Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).
FREQ_SEL I Selects between ÷1 and ÷2 frequency options. (Refer to functional block diagram).
FEEDBACK I Feedback input to phase detector.
LF I Input for external loop filter connection.
Q0-Q4 O Clock output.
Q5
2Q O Clock output (2 x Q frequency).
Q/2 O Clock output (Q frequency ÷ 2).
LOCK O Indicates phase lock has been achieved (HIGH when locked).
OE/RST

PLL_EN I Disables phase-lock for low frequency testing. (Refer to functional block diagram).

O Inverted clock output.

I Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are

enabled. When LOW, outputs are in HIGH impedance.

3072 tbl 01

9.7 2

IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

VTERM

Terminal Voltage

–0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND

(3)

VTERM

TA Operating

Terminal Voltage
with Respect to
GND

–0.5 to V

+0.5

CC

–0.5 to V

CC

+0.5

0 to +70 –55 to +125 °C

V

Temperature

TBIAS Temperature

–55 to +125 –65 to +135 °C
Under Bias

TSTG Storage

–55 to +125 –65 to +150 °C
Temperature

IOUT DC Output

–60 to +120 –60 to +120 mA
Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed

CC by +0.5V unless otherwise noted.

V

2. Input and V

3. Output and I/O terminals.

CC terminals.

3072 tbl 02

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

C

IN

Input
Capacitance

C

OUT

Output
Capacitance

NOTE:

1. This parameter is measured at characterization but not tested.

(1)

Conditions Typ. Max. Unit

VIN = 0V 4.5 6.0

V

OUT

= 0V 5.5 8.0

pF

pF

3072 lnk 03

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: T

Symbol Parameter Test Conditions

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current VCC = Max. VI = VCC ——±1µA
II L Input LOW Current VI = GND — — ±1 µA
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
IOZL VO = 0.5V — — ±1 µA
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
VH Input Hysteresis — — 100 — mV
VOH Output HIGH Voltage VCC = Min. IOH = –3mA 2.5 3.5 — V

VOL Output LOW Voltage VCC = Min.

ICCL
ICCH
ICCZ

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Duration of the condition can not exceed one second.

A = 0°C to 70°C, VCC = 5.0V ± 5%

(1)

VIN = VIH or VIL IOH = –12mA MIL.

OH = –15mA COM'L.

I
IOH = –24mA MIL.

OH = –32mA COM'L.

I
IOL = 48mA MIL.

IN = VIH or VIL

V

OL = 64mA COM'L.

I

Quiescent Power Supply Current VCC = Max., VIN = GND or VCC

(Test mode)

(3)

Min. Typ.

(2)

Max. Unit

2.4 3.5 — V

2.0 3.0 — V

— 0.2 0.55 V

— 2.0 4.0 mA

3072 tbl 04

9.7 3

IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions

∆ICC Quiescent Power Supply Current

TTL Inputs HIGH

ICCD Dynamic Power Supply

(4)

Current

VCC = Max.
V

IN = VCC –2.1V

VCC = Max.
All Outputs Open

(3)

(1)

VIN = VCC
V

IN = GND

Min. Typ.

— 0.5 1.5 mA

— 0.25 0.4 mA/

CPD Power Dissipation Capacitance 50% Duty Cycle — 15 40 pF
IC Total Power Supply Current

(5,6)

VCC = Max.

—2540mA

PLL_EN = 1, LOCK = 1, FEEDBACK = Q/2
SYNC frequency = 20MHz. Q/2 loaded with 50pF
All other outputs open

VCC = Max.

—4260mA

PLL_EN = 1, LOCK = 1, FEEDBACK = Q/2
SYNC frequency = 20MHz. Q/2 loaded with 50Ω
Thevenin termination. All other outputs open

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.

2. Typical values are at V

3. Per TTL driven input; all other inputs at V

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.

5. Values for these conditions are examples of the I

6. I

C = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (f) + ILOAD
ICC = Quiescent Current (ICCL, ICCH and ICCZ)

CC = Power Supply Current for a TTL High Input

∆I

H = Duty Cycle for TTL Inputs High

D
N

T = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q frequency

LOAD = Dynamic Current due to load.

I

CC = 5.0V, +25°C ambient.

CC or GND.

CC formula. These limits are guaranteed but not tested.

(2)

Max. Unit

MHz

3072 tbl 05

SYNC INPUT TIMING REQUIREMENTS

Symbol Parameter Min. Max. Unit

TRISE/FALL Rise/Fall Times,

— 3.0 ns
SYNC inputs
(0.8V to 2.0V)

Frequency Input Frequency,

10

(1)

2Q fmax MHz

SYNC Inputs

Duty Cycle Input Duty Cycle,

25% 75% —

SYNC Inputs

3053 tbl 06

OUTPUT FREQUENCY SPECIFICATIONS

Max.

Symbol Parameter Min. 55 70 100 133 Unit

f2Q Operating frequency 2Q Output 40 55 70 100 133 MHz
fQ

Operating frequency Q0-Q4,

Q5 Outputs

20 27.5 35 50 66.7 MHz

fQ/2 Operating frequency Q/2 Output 10 13.75 17.5 25 33.3 MHz

NOTES:

1. Note 8 in "General AC Specification Notes" and Figure 2 describes this specification and its actual limits depending on the feedback connection.

2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.

(2)

3072 tbl 07

9.7 4