Integrated Device Technology, Inc.
FAST CMOS
BUS INTERFACE
LATCHES
IDT54/74FCT841AT/BT/CT/DT
FEATURES:
• Common features:
– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT841T:
– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 48mA IOL)
– Power off disable outputs permit “live insertion”
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
DESCRIPTION:
The FCT8xxT series is built using an advanced dual metal
CMOS technology.
The FCT8xxT bus interface latches are designed to eliminate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths or
buses carrying parity. The FCT841T are buffered, 10-bit wide
versions of the popular FCT373T function. They are ideal for
use as an output port requiring high IOL/IOH.
All of the FCT8xxT high-performance interface family can
drive large capacitive loads, while providing low-capacitance
bus loading at both inputs and outputs. All inputs have clamp
diodes to ground and all outputs are designed for low-capacitance bus loading in high-impedance state.
D4
D5
D8
D9
D
Q
LE
LE
OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
D
Q
LE
0
Y
D
Q
LE
1
Y
D
Q
LE
2
Y
D
Q
LE
3
Y
D
Q
LE
4
Y
Y
D
Q
LE
5
D
Q
LE
8
Y
Y
9
2571 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES JUNE 1996
1996 Integrated Device Technology, Inc. 6.22 2571/6
1
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
PIN CONFIGURATIONS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OE
D
D1
D2
D3
D4
D5
D6
D7
D
D9
GND
VCC1
24
2
0
3
P24-1
4
D24-1
5
SO24-2
6
SO24-7
7
SO24-8
8
&
9
E24-1
10
8
11
12
23
22
21
20
19
18
17
16
15
14
13
Y
Y1
Y2
Y3
Y4
Y
Y6
Y7
Y8
Y9
LE
0
5
INDEX
D
D
D
NC
D
D
D
1
D
4
2
5
3
6
4
7
8
5
9
6
10
7
11
1213
8
D
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
2571 drw 02 2571 drw 03
PIN DESCRIPTION FUNCTION TABLE
Name I/O Description
DI I The latch data inputs.
LE I The latch enable input. The latches are
transparent when LE is HIGH. Input data
is latched on the HIGH-to-LOW
transition.
YI O The 3-state latch outputs.
OE
I The output enable control. When OE is
LOW, the outputs are enabled. When
is HIGH, the outputs V
are in high-
I
OE
impedance (off) state.
2571 tbl 01
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
(2)
VTERM
Terminal Voltage
–0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND
(3)
VTERM
TA Operating
Terminal Voltage
with Respect to
GND
–0.5 to
V
CC +0.5
–0.5 to
VCC +0.5
0 to +70 –55 to +125 °C
V
Temperature
TBIAS Temperature
–55 to +125 –65 to +135 °C
Under Bias
TSTG Storage
–55 to +125 –65 to +150 °C
Temperature
PT Power Dissipation 0.5 0.5 W
IOUT DC Output
–60 to +120 –60 to +120 mA
Current
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
CC by +0.5V unless otherwise noted.
V
2. Input and V
3. Outputs and I/O terminals only.
CC terminals only.
2571 lnk 03
OE
NOTE: 2571 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, Z = High Impedance
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
CIN Input
COUT Output
NOTE:
1. This parameter is measured at characterization but not tested.
Inputs Internal Output
OE
LE DI QI YI Function
H H L L Z High Z
H H H H Z High Z
H L X NC Z Latched (High Z)
L H L L L Transparent
L H H H H Transparent
L L X NC NC Latched
Capacitance
Capacitance
OE
NC
1
L28-1
CC
V
Y
Y
262728
25
Y
24
Y
23
Y
NC
22
Y
21
Y
20
Y
19
0
D
32
0
1
1817161514
NC
LE
9
8
Y
Y
9
D
GND
LCC
TOP VIEW
(1)
(1)
Conditions Typ. Max. Unit
VIN = 0V 6 10 pF
VOUT = 0V 8 12 pF
2
3
4
5
6
7
2571 lnk 04
6.22 2
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol Parameter Test Conditions
(1)
Min. Typ.
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current
II L Input LOW Current
(4)
(4)
VI = 0.5V — — ±1
VCC = Max. VI = 2.7V — — ±1 µA
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA
(4)
(4)
VO = 0.5V — — ±1
VCC = Max., VI = VCC (Max.) — — ±1 µA
IOZL (3-State Output pins)
II Input HIGH Current
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
VH Input Hysteresis — — 200 — mV
ICC Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 0.01 1 mA
(2)
Max. Unit
2571 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT841T
Symbol Parameter Test Conditions
V
OH
V
OL
I
OS
I
OFF
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
5. This parameter is guaranteed but not tested.
Output HIGH Voltage VCC = Min.
IN
= V
IH
or V
V
IL
Output LOW Voltage VCC = Min.
IN
= V
IH
or V
V
IL
Short Circuit Current VCC = Max., VO = GND
Input/Output Power Off Leakage
(5)
A = –55°C.
VCC = 0V, V
IN
or V
O
(3)
≤ 4.5V — —
(1)
IOH = –6mA MIL.
OH
= –8mA COM'L.
I
IOH = –12mA MIL.
OH
= –15mA COM'L.
I
I
OL
= 32mA MIL.
OL
= 48mA COM'L.
I
Min. Typ.
2.4 3.3 — V
2.0 3.0 — V
— 0.3 0.5 V
–60 –120 –225 mA
(2)
Max. Unit
±
1
µ
A
2571 lnk 06
6.22 3