Integrated Device Technology Inc IDT74FCT810CTPY, IDT74FCT810CTPB, IDT74FCT810CTP, IDT74FCT810CTLB, IDT74FCT810CTL Datasheet

Integrated Device Technology, Inc.

FAST CMOS
BUFFER/CLOCK DRIVER

IDT54/74FCT810BT/CT

FEATURES:

• 0.5 MICRON CMOS technology

• Guaranteed low skew < 600ps (max.)

• Very low duty cycle distortion < 700ps (max.)

• Low CMOS power levels

• TTL compatible inputs and outputs

• TTL level output voltage swings

• High drive: –32mA I

OH, 48mA IOL

• Two independent output banks with 3-state control
– One 1:5 Inverting bank
– One 1:5 Non-Inverting bank

• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)

• Available in DIP, SOIC, SSOP, QSOP, CERPACK and

FUNCTIONAL BLOCK DIAGRAMS

OE

A

IN

OE

IN

A

B

B

5

OA1-OA

5

5

OB1-OB

5

3103 drw 01

LCC packages

• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:

The IDT54/74FCT810BT/CT is a dual bank inverting/ non­inverting clock driver built using advanced dual metal CMOS
technology. It consists of two banks of drivers, one inverting
and one non-inverting. Each bank drives five output buffers
from a standard TTL-compatible input. The IDT54/
74FCT810BT/CT have low output skew, pulse skew and
package skew. Inputs are designed with hysteresis circuitry
for improved noise immunity. The outputs are designed with
TTL output levels and controlled edge rates to reduce signal
noise. The part has multiple grounds, minimizing the effects of
ground inductance.

PIN CONFIGURATIONS

V

CC

OA
OA
OA

GND

OA
OA

GND

OE

IN

A

A

1
2

1

2

3

3

4
5

4

6

5

7
8

9
10

DIP/SOIC/SSOP/QSOP/CERPACK

P20-1

D20-1
SO20-2
SO20-7
SO20-8

&

E20-1

TOP VIEW

20
19
18
17
16
15
14
13
12
11

V

CC

OB
OB
OB
GND
OB
OB
GND
OE

B

IN

1

2

3

4

5

B

3103 drw 02

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDEX

OA

GND

OA
OA

GND

OA2

3 2 20 19

4

3

5

4

6

5

7
8

910111213

OEA

TOP VIEW

OA1

1

L20-2

INA

LCC

VCC

INB

VCC

OEB

OB1

18
17
16
15
14

GND

OB
OB
GND

OB
OB

2
3

4
5

3103 drw 03

MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1995

1995 Integrated Device Technology, Inc. 9.4 DSC-4646/3

1

IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Pin Names Description

OE

A, OEB 3-State Output Enable Inputs (Active LOW)

INA, INB Clock Inputs
OAn,

OB

n Clock Outputs

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

CIN Input

Capacitance

COUT Output

Capacitance

NOTE:

1. This parameter is measured at characterization but not tested.

(1)

Conditions Typ. Max. Unit

VIN = 0V 4.5 6.0 pF

VOUT = 0V 5.5 8.0 pF

3103 tbl 01

3103 lnk 02

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

VTERM

Terminal Voltage

–0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND

(3)

VTERM

TA Operating

Terminal Voltage
with Respect to
GND

–0.5 to V

+0.5

CC

–0.5 to V

CC

+0.5

0 to +70 –55 to +125 °C

V

Temperature

TBIAS Temperature

–55 to +125 –65 to +135 °C
Under Bias

TSTG Storage

–55 to +125 –65 to +150 °C
Temperature

IOUT DC Output

–60 to +120 –60 to +120 mA
Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed

CC by +0.5V unless otherwise noted.

V

2. Input and V

3. Output and I/O terminals.

CC terminals.

3103 lnk 03

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

(5)

(5)

VCC = Max. VI = 2.7V — — ±1 µA
VCC = Max. VI = 0.5V — — ±1 µA

II H Input HIGH Current
II L Input LOW Current
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA

(5)

(5)

VO = 0.5V — — ±1 µA

VCC = Max., VI = VCC (Max.) — — ±1 µA

IOZL (3-State Output pins)
II Input HIGH Current
VIK Clamp Diode Voltage VCC = Min., IIN= –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.
VOH Output HIGH Voltage VCC = Min.

IN = VIH or VIL

V

VOL Output LOW Voltage VCC = Min.

IN = VIH or VIL

V

IOFF Input/Output Power Off Leakage
VH Input Hysteresis for all inputs — — 150 — mV

ICCL

Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA

(5)

VCC = 0V, VIN or VO ≤ 4.5V — — ±1 µA

(3)

, VO = GND –60 –120 –225 mA

IOH = –12mA MIL.

OH = –15mA COM'L.

I
IOH = –24mA MIL.

OH = –32mA COM'L.

I
IOL = 32mA MIL.

OL = 48mA COM'L.

I

2.4 3.3 — V

2.0 3.0 —

(4)

— 0.3 0.55 V

ICCH
ICCZ

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5.0V, +25°C ambient.

3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.

4. Duration of the condition can not exceed one second.

5. The test limit for this parameter is ± 5µA at T

A = –55°C.

(2)

Max. Unit

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9.4 2