Integrated Device Technology Inc IDT74FCT273CTSOB, IDT74FCT273CTSO, IDT74FCT273CTQB, IDT74FCT273ATSOB, IDT74FCT273ATSO Datasheet

Integrated Device Technology, Inc.

FAST CMOS
OCTAL D FLIP-FLOP
WITH MASTER RESET

IDT54/74FCT273T/AT/CT

FEATURES:

• Std., A, and C speed grades

• Low input and output leakage ≤1µA (max.)

• CMOS power levels

• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)

• High drive outputs (-15mA IOH, 48mA IOL)

• Meets or exceeds JEDEC standard 18 specifications

• Product available in Radiation Tolerant and Radiation

Enhanced versions

• Military product compliant to MIL-STD-883, Class B

and DESC listed (dual marked)

• Available in DIP, SOIC, QSOP, CERPACK and LCC

packages

FUNCTIONAL BLOCK DIAGRAM

D

0

CP

CP

R

D

1

Q

D

CP

D

R

D

2

D

Q D

QD

CP

R

D

D

DESCRIPTION:

The IDT54/74FCT273T/AT/CT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT273T/AT/CT have eight edge-triggered D-type flip­flops with individual D inputs and O outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and

reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.

All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.

D

3

CP

R

Q D

D

D

4

CP

R

D

Q D

D

5

Q D

CP

R

D

D

6

D

Q D

CP

R

D

7

Q

CP

R

D

MR

O

0

O

1

O

2

O

3

O

4

O

5

O

6

O

7

2568 drw 03

PIN CONFIGURATIONS

MR

O

D0
D1

O1
O2
D2
D3
O3

GND

0

2
3
4

5
6
7
8
9
10 11

P20-1

D20-1
SO20-2
SO20-8

&

E20-1

20
19
18
17

16
15
14
13
12

VCC1
O
D7
D6
O6

O5
D5
D4
O4

CP

7

DIP/SOIC/QSOP/CERPACK

TOP VIEW

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

2568 drw 01

INDEX

D

1

O

1

O

2

D

2

D

3

0D0

O

3 2 20 19

4

1

5
6

L20-2

7
8

9 10111213

3

O

GND

LCC

TOP VIEW

MILITARY AND COMMERCIAL TEMPERATURE RANGES APRIL 1995

1995 Integrated Device Technology, Inc. 6.10 DSC-4209/3

MR

CP

CC

V

4

O

7

O

18

D

7

17

D

6

O
O
D

6
5

5

2568 drw 02

1

4

D

16
15
14

IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION FUNCTION TABLE

Pin Names Description

DN Data Inputs

MR

Master Reset (Active LOW)
CP Clock Pulse Input (Active Rising Edge)
ON Data Outputs

2568 tbl 01

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Military Unit

(2)

VTERM

Terminal Voltage

–0.5 to +7.0 –0.5 to +7.0 V
with Respect to
GND

(3)

VTERM

TA Operating

Terminal Voltage
with Respect to
GND

–0.5 to

CC +0.5

V

–0.5 to

VCC +0.5

0 to +70 –55 to +125 °C

V

Temperature

TBIAS Temperature

–55 to +125 –65 to +135 °C
Under Bias

TSTG Storage

–55 to +125 –65 to +150 °C
Temperature

PT Power Dissipation 0.5 0.5 W
IOUT DC Output

–60 to +120 –60 to +120 mA
Current

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not

implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability. No terminal voltage may exceed

CC by +0.5V unless otherwise noted.

V

2. Input and V

3. Outputs and I/O terminals only.

CC terminals only.

2568 lnk 03

Operating Mode

Reset (Clear) L X X L

Load "1" H ↑ hH
Load "0" H ↑ IL

NOTE: 2568 tbl 02

1. H = HIGH voltage level steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t Care
↑ = LOW-to-HIGH Clock Transition

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

CIN Input

Capacitance

COUT Output

Capacitance

NOTE:

1. This parameter is measured at characterization but not tested.

(1)

Inputs Outputs

CP DN ON

Conditions Typ. Max. Unit

(1)

MR

MR

VIN = 0V 6 10 pF

VOUT = 0V 8 12 pF

2568 lnk 04

6.10 2

IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol Parameter Test Conditions

(1)

Min. Typ.

VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

(4)

(4)

(4)

VCC = Max. VI = 2.7V — — ±1 µA
VCC = Max. VI = 0.5V — — ±1 µA
VCC = Max., VI = VCC (Max.) — — ±1 µA

II H Input HIGH Current
II L Input LOW Current
II Input HIGH Current
VIK Clamp Diode Voltage VCC = Min., IN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.
VOH Output HIGH Voltage VCC = Min.

V

IN = VIH or VIL

VOL Output LOW Voltage VCC = Min.

V

IN = VIH or VIL

(3)

, VO = GND –60 –120 –225 mA

IOH = –6mA MIL.
I

OH = –8mA COM'L.

IOH = –12mA MIL.
I

OH = –15mA COM'L.

IOL = 32mA MIL.
I

OL = 48mA COM'L.

2.4 3.3 — V

2.0 3.0 — V

— 0.3 0.5 V

VH Input Hysteresis — — 200 — mV
ICC Quiescent Power Supply Current VCC = Max.

V

IN = GND or VCC

NOTES: 2568 tbl 05

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. The test parameter for this parameter is ±5µA at T

CC = 5.0V, +25°C ambient.

A = -55°C.

— 0.01 1 mA

(2)

Max. Unit

6.10 3