Integrated Device Technology Inc IDT74FCT541ASOB, IDT74FCT541ASO, IDT74FCT541AP, IDT74FCT541ALB, IDT74FCT541AL Datasheet

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Integrated Device Technology, Inc.
FAST CMOS OCTAL BUFFER/LINE DRIVER
IDT54/74FCT240/A/C IDT54/74FCT241/A/C IDT54/74FCT244/A/C IDT54/74FCT540/A/C IDT54/74FCT541/A/C
FEATURES:
• IDT54/74FCT240A/241A/244A/540A/541A 25% faster than FAST
• IDT54/74FCT240C/241C/244C/540C/541C up to 55% faster than FAST
•IOL = 64mA (commercial) and 48mA (military)
• CMOS power levels (1mW typ. static)
• Product available in Radiation Tolerant and Radiation Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Meets or exceeds JEDEC Standard 18 specifications
FUNCTIONAL BLOCK DIAGRAMS 2529 cnv* 01–03
OE
DA OB DA OB DA
OB DA
OB
A
OE
0
0
1
1
2 2
3
3
OA DB OA
DB OA
DB OA
DB
OE
A
B 0
DA
0
0
OB
0
DA OB DA
OB DA
OB
1
1
2
2
3
3
1 1
2 2
3 3
DESCRIPTION:
TM
The IDT octal buffer/line drivers are built using an advanced dual metal CMOS technology. The IDT54/74FCT240/A/C, IDT54/74FCT241/A/C and IDT54/74FCT244/A/C are designed to be employed as memory and address drivers, clock drivers and bus-oriented transmitter/receivers which provide improved board density.
The IDT54/74FCT540/A/C and IDT54/74FCT541/A/C are similar in function to the IDT54/74FCT240/A/C and IDT54/ 74FCT244/A/C, respectively, except that the inputs and out­puts are on opposite sides of the package. This pinout arrangement makes these devices especially useful as output ports for microprocessors and as backplane drivers, allowing ease of layout and greater board density.
241 Only
OEB* OA DB
OA DB
OA DB
OA DB
OE
A
0
0
1 1
2 2
3 3
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
OE
O0* O1*
O O O O O O
B
2
*
3
*
4
*
5
*
6
*
7
*
IDT54/74FCT240
IDT54/74FCT241/244
*OEB for 241, OEB for 244
IDT54/74FCT540/541
*Logic diagram shown for 'FCT540. 'FCT541 is the non-inverting option.
2606 dwg 01–03
The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES MAY 1992
1992 Integrated Device Technology, Inc. 7.8 DSC-4610/3
1
IDT54/74FCT240/241/244/540/541/A/C FAST CMOS OCTAL BUFFER/LINE DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT240 2529 cnv* 04–09
OEA DA0
OB0 DA1
OB1 DA2 OB2 DA3 OB3
GND
IDT54/74FCT241/244
20
2 3
4 5 6 7 8 9
P20-1 D20-1
SO20-2
E20-1
19 18 17 16 15
&
14 13 12
10 11
DIP/SOIC/CERPACK
TOP VIEW
VCC1 OE
OA0 DB0
OA1 DB1
OA2 DB2 OA3
DB3
B
INDEX
DA1 OB1 DA2
OB2 DA3
DA0
OB0
OEA
3 2 20 19
4
1
5 6
L20-2
7 8
9 10111213
3
DB
OB3
GND
LCC
TOP VIEW
VCC
OA3
OEB
18 17 16 15 14
DB2
OA0 DB0 OA1 DB1
OA2
OEA DA0
OB0 DA1
OB1 DA2 OB2 DA3 OB3
GND
*OEB for 241,
OE
B for 244
IDT54/74FCT540/541
OEA
D0 D1
D2
D3 D4 D5 D6
D7
GND
*
O
X for 540, OX for 541
20
2 3 4
5 6 7 8 9
P20-1 D20-1
SO20-2
E20-1
19 18 17 16 15
&
14 13 12
10 11
DIP/SOIC/CERPACK
TOP VIEW
20
2 3 4
5 6 7 8 9
P20-1 D20-1
SO20-2
E20-1
19 18 17
16 15
&
14 13 12
10 11
DIP/SOIC/CERPACK
TOP VIEW
VCC1 OE
OA DB0 OA1 DB1
OA2 DB2 OA3 DB3
CC1
V OE
O0*
1*
O
2*
O
3*
O
4*
O
5*
O
6*
O O7*
INDEX
VCC
DA0
OB0
B* 0
DA1 OB1 DA2
OB2 DA3
3 2 20 19
4
1
5 6
L20-2 7 8
OEB*
OEA
18
OA0
17
DB0 OA1
16
DB1
15
OA2
14
9 10111213
3
3
DB
OA3
OB
GND
DB2
LCC
TOP VIEW
INDEX
D1
D0
VCC
OEA
B
3 2 20 19
D2 O0* D
D4 D5
D6
4
3
5 6 7 8
1
L20-2
OEB
18 17 16 15 14
1*
O O
2* 3*
O O
4*
9 10111213
7
D
GND
6*
5*
O7*
O
O
LCC
TOP VIEW
2606 cnv* 04–09
7.8 2
IDT54/74FCT240/241/244/540/541/A/C FAST CMOS OCTAL BUFFER/LINE DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION FUNCTION TABLE
Pin Names Description
OE
A, OEB 3–State Output Enable Inputs (Active LOW)
(1)
OEB
3–State Output Enable Input (Active HIGH) Dxx Inputs Oxx Outputs
NOTE: 2606 tbl 04
1. OEB for 241 only.
(1)
OE
OE
Inputs
A
OE
B
OE
OE
(2)
B
D 240 241 244 540 541
Outputs
LLHLHL LLHHLHHLH HHLXZZZZZ
NOTES:
1. H = High Voltage Level X = Don’t Care L = Low Voltage Level Z = High Impedance
2. OE
B for 241 only.
(1)
LHL
2606 tbl 05
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Commercial Military Unit
(2)
V
TERM
Terminal Voltage
–0.5 to +7.0 –0.5 to +7.0 V with Respect to GND
(3)
V
TERM
Terminal Voltage
–0.5 to V
CC
–0.5 to V
CC
V with Respect to GND
T
A
Operating
0 to +70 –55 to +125°C
Temperature
T
BIAS
Temperature
–55 to +125 –65 to +135°C
Under Bias
T
STG
Storage
–55 to +125 –65 to +150°C
Temperature
P I
OUT
T
Power Dissipation 0.5 0.5 W DC Output
120 120 mA
Current
NOTES: 2606 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed V
2. Input and V
3. Outputs and I/O terminals only.
CC by +0.5V unless otherwise noted.
CC terminals only.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter
C
IN
Input Capacitance
C
OUT
Output Capacitance
NOTE: 2606 tbl 02
1. This parameter is measured at characterization but not tested.
(1)
Conditions Typ. Max. Unit
VIN = 0V 6 10 pF
V
OUT
= 0V 8 12 pF
7.8 3
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