Integrated Device Technology Inc IDT74FCT16652TPVB, IDT74FCT16652TPV, IDT74FCT16652TPFB, IDT74FCT16652TPF, IDT74FCT16652TPAB Datasheet
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Integrated Device Technology, Inc.
FAST CMOS 16-BIT BUS
TRANSCEIVER/
REGISTERS
IDT54/74FCT16652T/AT/CT/ET
IDT54/74FCT162652T/AT/CT/ET
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical t
SK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP,15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
–VCC = 5V ±10%
• Features for FCT16652T/AT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162652T/AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
DESCRIPTION:
The FCT16652T/AT/CT/ET and FCT162652T/AT/CT/ET
16-bit registered transceivers are built using advanced dual
metal CMOS technology. These high-speed, low-power de-
vices are organized as two independent 8-bit bus transceivers
with 3-state D-type registers. For example, the xOEAB and
x
OEBA
signals control the transceiver functions.
The xSAB and xSBA control pins are provided to select
either real time or stored data transfer. The circuitry used for
select control will eliminate the typical decoding glitch that
occurs in a multiplexer during the transition between stored
and real time data. A LOW input level selects real-time data
and a HIGH level selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D-flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (xCLKAB or xCLKBA), regardless of the
select or enable control pins. Flow-through organization of
signal pins simplifies layout. All inputs are designed with
hysteresis for improved noise margin.
The FCT16652T/AT/CT/ET are ideally suited for driving
high capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162652T/AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
FCT162652T/AT/CT/ET are plug-in replacements for the
FCT16652T/AT/CT/ET and ABT16652 for on-board bus interface applications.
FUNCTIONAL BLOCK DIAGRAM
OEAB
1B1
2
2OEBA
2CLKBA
CLKAB
2
1
2SBA
2SAB
2A1
A REG
D
C
TO 7 OTHER CHANNELS
B REG
D
C
2B1
2549 drw 02
1
OEAB
OEBA
1
1
CLKBA
1
SBA
1
CLKAB
1
SAB
B REG
D
C
1A1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
A REG
D
C
TO 7 OTHER CHANNELS
2549 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGE AUGUST 1996
1996 Integrated Device Technology, Inc. DSC-2549/8
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1
OEAB
1
CLKAB
1
SAB
GND
V
GND
GND
V
GND
2
SAB
2
CLKAB
2OEAB
1A1
1
A
CC
A
1
1
A
1A5
1
A
1
A
A
1
2A1
2
A
A
2
A
2
2A5
2A6
CC
2
A
2A8
1
2
3
4
5
6
2
7
8
3
9
4
10
11
6
12
7
13
8
14
SO56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
OEBA
1
1
CLKBA
1
SBA
GND
1B1
1
B
2
V
CC
1B3
1
B
4
1
B
5
GND
1
B
6
1B7
B
8
1
SO56-2
15
SO56-3
2
16
3
17
18
4
19
20
21
22
7
23
24
42
41
40
39
38
37
36
35
34
33
3225
26
27
28
31
30
29
B
1
2
2
B
2
2B3
GND
2
B
4
B
5
2
B
6
2
V
CC
2B7
2
B
8
GND
2
SBA
2
CLKBA
2
OEBA
1OEAB
1CLKAB
1SAB
GND
1A1
1
A2
VCC
1
A3
1
A4
1A5
GND
1
A6
1
A7
1
A8
2A1
2
A2
2
A3
GND
A4
2
2A5
2A6
VCC
A7
2
2A8
GND
SAB
2
2
CLKAB
2OEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3225
31
30
29
1
OEBA
1CLKBA
1SBA
GND
1
B1
1
B2
VCC
1B3
1
B4
1
B5
GND
1
B6
1B7
1
B8
2
B1
2
B2
2B3
GND
2
B4
B5
2
B6
2
VCC
2B7
2
B8
GND
2SBA
2CLKBA
2OEBA
SSOP/
TSSOP/TVSOP
TOP VIEW
2549 drw 03
CERPACK
2549 drw 04
TOP VIEW
2
IDT54/74FCT16652T/AT/CT/ET, FCT162652T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names Description
xAx Data Register A Inputs
Data Register B Outputs
xBx Data Register B Inputs
Data Register A Outputs
xCLKAB, xCLKBA Clock Pulse Inputs
xSAB, xSBA Output Data Source Select Inputs
xOEAB, x
FUNCTION TABLE
xOEAB x
OEBA
Output Enable Inputs
(2)
Inputs Data I/O
OEBA
OEBA
L
L
X
H
L
L
L
L
H
H
xCLKAB xCLKBA xSAB xSBA xAx xBx
H
H
H
H
X
L
L
L
H
H
H or L
↑
↑
↑
H or L
↑
X
X
X
H or L
H or L
↑
H or L
↑
↑
↑
X
H or L
X
X
2549 tbl 01
X
X
X
(2)
X
X
X
X
X
L
H
X
X
X
X
X
X
L
H
X
X
CAPACITANCE (TA = +25°C, f = 1.0MHz)
(1)
Output
Input
Input
(1)
Conditions Typ. Max. Unit
VIN = 0V 4.5 6.0 pF
VOUT = 0V 5.5 8.0 pF
Operation or Function
Store A and B Data
(1)
Store A, Hold B
Store A in Both Registers
Hold A, Store B
Store B in both Registers
Stored B Data to A Bus
Stored A Data to B Bus
Symbol Parameter
CIN Input
Capacitance
CI/O I/O
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
Input Input Isolation
Input
Unspecified
Input
(1)
(2)
Unspecified
Output
Output Input Real Time B Data to A Bus
Input Output Real Time A Data to B Bus
H L H or L H or L H H Output Output Stored A Data to B Bus and
Stored B Data to A Bus
NOTES:
1. The data output functions may be enabled or disabled by various signals at the xOEAB or x
Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH
transition on the clocks inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't care
↑ = LOW-to-HIGH Transition
ABSOLUTE MAXIMUM RATINGS
Symbol Description Max. Unit
VTERM
VTERM
OEBA
inputs.
(2)
Terminal Voltage with Respect to
GND
(3)
Terminal Voltage with Respect to
GND
(1)
–0.5 to +7.0 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
–0.5 to
CC +0.5
V
2549 lnk 02
2549 tbl 03
V
2549 lnk 04
3
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