Integrated Device Technology Inc IDT74FCT16646CTPFB, IDT74FCT16646CTPF, IDT74FCT16646CTPAB, IDT74FCT16646CTPA, IDT74FCT16646CTEB Datasheet
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Integrated Device Technology, Inc.
FAST CMOS 16-BIT BUS
TRANSCEIVER/
REGISTERS (3-STATE)
IDT54/74FCT16646T/AT/CT/ET
IDT54/74FCT162646T/AT/CT/ET
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
–VCC = 5V ±10%
• Features for FCT16646T/AT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162646T/AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
– Reduced system switching noise
– Typical V
OLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
DESCRIPTION:
The IDT54/74FCT16646T/AT/CT/ET and IDT54/
74FCT162646T/AT/CT/ET 16-bit registered transceivers are
built using advanced dual metal CMOS technology. These
high-speed, low-power devices are organized as two independent 8-bit bus transceivers with 3-state D-type registers.
The control circuitry is organized for multiplexed transmission
of data between A bus and B bus either directly or from the
internal storage registers. Each 8-bit transceiver/register features direction control (xDIR), over-riding Output Enable control (xOE) and Select lines (xSAB and xSBA) to select either
real-time data or stored data. Separate clock inputs are
provided for A and B port registers. Data on the A or B data
bus, or both, can be stored in the internal registers by the
LOW-to-HIGH transitions at the appropriate clock pins. Flowthrough organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.
The IDT54/74FCT16646T/AT/CT/ET are ideally suited for
driving high-capacitance loads and low-impedance
backplanes. The output buffers are designed with power off
disable capability to allow "live insertion" of boards when used
as backplane drivers.
The IDT54/74FCT162646T/AT/CT/ET have balanced
output drive with current limiting resistors. This offers low
ground bounce, minimal undershoot, and controlled output
fall times–reducing the need for external series terminating
resistors. The IDT54/74FCT162646T/AT/CT/ET are plug-in
replacements for the IDT54/74FCT16646T/AT/CT/ET and
54/74ABT16646 for on-board bus interface applications.
FUNCTIONAL BLOCK DIAGRAM
1
OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
B REG
D
C
A1
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
A REG
D
C
TO 7 OTHER CHANNELS
2540 drw 01
1B1
MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996
1996 Integrated Device Technology, Inc. 5.13 DSC-4231/9
2
2
2
CLKBA
2
SBA
2
CLKAB
2
SAB
OE
DIR
2A1
A REG
D
C
TO 7 OTHER CHANNELS
B REG
D
C
2B1
2540 drw 02
1
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1DIR
1CLKAB
1SAB
GND
1A1
A2
1
VCC
A3
1
A4
1
1A5
GND
A6
1
A7
1
A8
1
2A1
A2
2
2
A3
GND
2
A4
2A5
2A6
VCC
A7
2
2A8
GND
SAB
2
2
CLKAB
2DIR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
SO56-1
SO56-2
SO56-3
48
43
56
55
54
53
52
51
50
49
47
46
45
44
42
41
40
39
38
37
36
35
34
33
3225
31
30
29
1
OE
1CLKBA
1SBA
GND
1B1
B2
1
VCC
1B3
B4
1
B5
1
GND
B6
1
1B7
B8
1
B1
2
B2
2
2B3
GND
2
B4
2
B5
2
B6
VCC
2B7
B8
2
GND
2SBA
2CLKBA
2OE
1DIR
1CLKAB
1SAB
GND
1A1
A2
1
VCC
A3
1
A4
1
1A5
GND
A6
1
A7
1
A8
1
2A1
A2
2
A3
2
GND
2
A4
2A5
2A6
VCC
2
A7
2A8
GND
SAB
2
CLKAB
2
2DIR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3225
31
30
29
1OE
1CLKBA
1
SBA
GND
1
B1
B2
1
VCC
1B3
B4
1
1
B5
GND
B6
1
1B7
B8
1
B1
2
B2
2
2B3
GND
B4
2
2
B5
2
B6
VCC
2B7
2
B8
GND
2SBA
2CLKBA
2OE
SSOP/
TSSOP/TVSOP
TOP VIEW
2540 drw 03
CERPACK
2540 drw 04
TOP VIEW
5.13 2
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names Description
xAx Data Register A Inputs
Data Register B Outputs
xBx Data Register B Inputs
Data Register A Outputs
xCLKAB, xCLKBA Clock Pulse Inputs
xSAB, xSBA Output Data Source Select Inputs
xDIR, x
OE
FUNCTION TABLE
x
OE
OE
H
H
L
L
L
L
NOTES: 2540 tbl 03
1. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data
input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition
on the clock inputs.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition
Output Enable Inputs
2540 tbl 01
(2)
Inputs Data I/O
xDIR xCLKAB xCLKBA xSAB xSBA xAx xBx
X
X
L
L
H
H
H or L
↑
X
X
X
H or L
H or L
↑
X
H or L
X
X
X
X
X
X
L
H
CAPACITANCE (TA = +25°C, f = 1.0MHz)
(1)
(1)
Conditions Typ. Max. Unit
VIN = 0V 3.5 6.0 pF
VOUT = 0V 3.5 8.0 pF
Operation or Function
Store A and B Data
Stored B Data to A Bus
Stored A Data to B Bus
Symbol Parameter
CIN Input
Capacitance
CI/O I/O
Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
X
Input Input Isolation
X
L
Output Input Real Time B Data to A Bus
H
X
Input Output Real Time A Data to B Bus
X
2540 tbl 02
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Description Max. Unit
(2)
VTERM
VTERM
Terminal Voltage with Respect to
GND
(3)
Terminal Voltage with Respect to
GND
–0.5 to +7.0 V
–0.5 to
CC +0.5
V
V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
2540 tbl 04
5.13 3
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