Integrated Device Technology Inc IDT54FCT162260CTPAB, IDT54FCT162260CTPF, IDT54FCT162260CTPFB, IDT54FCT162260CTPV, IDT54FCT162260CTPVB Datasheet

Integrated Device Technology, Inc.

FAST CMOS
12-BIT TRI-PORT
BUS EXCHANGER

IDT54/74FCT16260AT/CT/ET

IDT54/74FCT162260AT/CT/ET

FEATURES:

• Common features:

– 0.5 MICRON CMOS Technology

– High-speed, low-power CMOS replacement for

ABT functions

– Typical t
– Low input and output leakage ≤1µA (max.)

– ESD > 2000V per MIL-STD-883, Method 3015;
– Packages include 25 mil pitch SSOP, 19.6 mil pitch

TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
–VCC = 5V ±10%

• Features for FCT16260AT/CT/ET:

– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at

VCC = 5V, TA = 25°C

• Features for FCT162260AT/CT/ET:

– Balanced Output Drivers: ±24mA (commercial),
– Reduced system switching noise

– Typical VOLP (Output Ground Bounce) < 0.6V at

VCC = 5V,TA = 25°C

SK(o) (Output Skew) < 250ps

> 200V using machine model (C = 200pF, R = 0)

±16mA (military)

DESCRIPTION:

The FCT16260AT/CT/ET and the FCT162260AT/CT/ET
Tri-Port Bus Exchangers are high-speed 12-bit latched bus
multiplexers/transceivers for use in high-speed microproces­sor applications. These Bus Exchangers support memory
interleaving with latched outputs on the B ports and address
multiplexing with latched inputs on the B ports.

The Tri-Port Bus Exchanger has three 12-bit ports. Data
may be transferred between the A port and either/both of the
B ports. The latch enable (LE1B, LE2B, LEA1B and LEA2B)
inputs control data storage. When a latch-enable input is
HIGH, the latch is transparent. When a latch-enable input is
LOW, the data at the input is latched and remains latched until
the latch enable input is returned HIGH. Independent output
enables (

writing to the other port.
capacitance loads and low impedance backplanes. The

output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.

with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times - reduc­ing the need for external series terminating resistors.

OE1B

and

OE2B

) allow reading from one port while

The FCT16260AT/CT/ET are ideally suited for driving high

The FCT162260AT/CT/ET have balanced output drive

FUNCTIONAL BLOCK DIAGRAM

OE1B

LEA1B

LE1B

12

SEL

OEA

A

1:12

12

LE2B

LEA2B 12

OE2B

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

12

1

M
U

X

0

12

12

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996

1996 Integrated Device Technology, Inc. 5.4 DSC-3032/6

A-1B

LATCH

1B-A

LATCH

2B-A

LATCH

A-2B

LATCH

12

1B1:12

12

12

2B1:12

3032 drw 01

1

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

PIN CONFIGURATIONS

OEA

LE1B

2B3

GND

2B
2B1

VCC

A1
A2
A3

GND

A
A5
A6
A7
A8
A9

GND

A10
A11
A12

VCC

1B1
1B2

GND

1B

LE2B

SEL

1
2
3
4

2

5
6
7
8
9
10
11

4

12
13
14

SO56-1
SO56-2

15

SO56-3
16
17
18
19
20
21
22
23
24
25

3

26

27

28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

OE2B
LEA2B
2B

4

GND

5

2B
2B6
VCC
2B7
2B8
2B9
GND

10

2B
2B11
2B12
1B12
1B11
1B10
GND
1B

9

1B8
1B7
VCC
1B6
1B5
GND

4

1B
LEA1B
OE1B

OEA

LE1B

2B

GND

2B
2B1
VCC

A1
A2
A

GND

A4
A5
A6
A
A8
A9

GND

A10
A11

A
VCC
1B1
1B

GND

1B3

LE2B

SEL

1
2

3

3
4

2

5
6
7
8
9

3

10
11
12
13
14

E56-1

7

15
16
17
18
19
20

12

21
22
23

2

24

56
55
54
53
52
51
50
49

48

47
46
45
44

43

42
41
40
39
38
37
36
35
34
33

3225
26
27
28

31

30

29

OE2B
LEA2B

2B4
GND

5

2B
2B6
VCC

7

2B
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11

10

1B
GND
1B9
1B8
1B7
VCC

6

1B
1B5
GND

4

1B
LEA1B

OE1B

SSOP/

TSSOP/TVSOP

TOP VIEW

3032 drw 02

CERPACK
TOP VIEW

5.4 2

3032 drw 03

IDT54/74FCT16260AT/CT/ET, 162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER MILITARY AND COMMERCIAL TEMPERATURES RANGES

PIN DESCRIPTION

Signal I/O Description

A

(1:12) I/O Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.

(1:12) I/O Bidirectional Data Port 1B. Connected to the even path or even bank of memory.

1B
2B

(1:12) I/O Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.

LEA1B I Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on

the HIGH to LOW transition of LEA1B.

LEA2B I Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on

the HIGH to LOW transition of LEA2B.

LE1B I Latch Enable Input for the 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched

on the HIGH to LOW transition of LE1B.

LE2B I Latch Enable Input for the 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched

on the HIGH to LOW transition of LE2B.

SEL I 1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables

data transfer from 2B Port to A Port.

OEA

OE1B
OE2B

ABSOLUTE MAXIMUM RATINGS

Symbol Description Max. Unit

(2)

VTERM

(3)

VTERM

TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

2. All device terminals except FCT162XXXT Output and I/O terminals.

3. Output and I/O terminals for FCT162XXXT.

CAPACITANCE (TA = +25°C, F = 1.0MHZ)

Symbol Parameter

CIN Input

CI/O I/O

NOTE:

1. This parameter is measured at characterization but not tested.

I Output Enable for A Port (Active LOW).
I Output Enable for 1B Port (Active LOW).

I Output Enable for 2B Port (Active LOW).

(1)

Terminal Voltage with Respect to
GND
Terminal Voltage with Respect to
GND

(1)

Conditions Typ. Max. Unit

VIN = 0V 3.5 6.0 pF

Capacitance

VOUT = 0V 3.5 8.0 pF

Capacitance

–0.5 to +7.0 V

–0.5 to

CC +0.5

V

V

3032 tbl 02

3032 tbl 03

3032 tbl 01

FUNCTION TABLES

(2)

Inputs Output

1B 2B SEL LE1B LE2B

OEA

OEA

A

HXHHXL H

LXHHXL L

XXHLXL A

(1)

XHLXHL H
XLLXHL L
XXLXLL A

(1)

XXXXXH Z

3032 tbl 04

Inputs Outputs

A LEA1BLEA2B

OE1B

OE1B

OE2B

OE2B

1B 2B

HHHLL H H

LHHLL L L

HHLLL H B

LHLLL L B

HLHLL B

LLHLL B

XLLLL B

(1)
(1)
(1)

(1)
(1)

H
L

(1)

B
XXXHH Z Z
X X X L H Active Z
X X X H L Z Active
X X X L L Active Active

NOTES:

1. Output level before the indicated steady-state input conditions were
established.

2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
↑ = LOW-to-HIGH Transition

3032 tbl 05

5.4 3