Integrated Device Technology Inc IDT74ALVCH16245PA, IDT74ALVCH16245PF, IDT74ALVCH16245PV Datasheet

IDT74ALVCH16245

3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

3.3V CMOS 16-BIT BUS
TRANSCEIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD

FEA TURES:

• 0.5 MICRON CMOS Technology

• Typical tSK(o) (Output Skew) < 250ps

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)

•VCC = 3.3V ± 0.3V, Normal Range

•VCC = 2.7V to 3.6V, Extended Range

•VCC = 2.5V ± 0.2V

• CMOS power levels (0.4

• Rail-to-Rail output swing for increased noise margin

• Available in SSOP, TSSOP, and TVSOP packages

DRIVE FEA TURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

APPLICA TIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

µµ

µ W typ. static)

µµ

IDT74ALVCH16245

DESCRIPTION:

This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. The ALVCH16245 is designed for asynchronous communication
between data buses. The control-function implementation minimizes external
timing requirements.

This device can be used as two 8-bit transceivers or one 16-bit transceiver.
It allows data transmission from the A bus to the B bus or from the B bus to the
A bus, depending on the logic level at the direction-control (DIR) input. The
output-enable (OE) input can be used to disable the device so that the buses
are effectively isolated.

The ALVCH16245 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.

The ALVCH16245 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.

FUNCTIONAL BLOCK DIAGRAM

1

1DIR

47

1A1

46

1

A2

44

1

A3

43

1

A4

41

1

A5

40

1

A6

38

1

A7

37

1

A8

24

2DIR

48

OE

1

36

2A1

2

B1

1

35

2

3

B2

1

5

B3

1

6

B4

1

8

B5

1

9

B6

1

11

B7

1

12

B8

1

A2

33

2

A3

32

2

A4

30

2

A5

29

2

A6

27

2

A7

26

2

A8

25

OE

2

13

B1

2

14

B2

2

16

B3

2

17

B4

2

19

B5

2

20

B6

2

22

B7

2

23

2

B8

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

MARCH 1999INDUSTRIAL TEMPERATURE RANGE

© 1999 Integrated Device Technology, Inc. DSC-4697/1

1

IDT74ALVCH16245

3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

PIN CONFIGURATION

1DIR

1B1

1B2

GND

1

B3

1

B4

V

CC

B5

1
1

B6

GND

B7

1
1

B8

B1

2

2

B2

GND

2B3

B4

2

VCC

B5

2

B6

2

GND

B7

2
2B8

2

DIR

2
3
4

5
6

7
8
9

10
11

12
13
14
15
16
17
18

19

20
21
22

23
24

481
47
46
45
44

43
42

41

40
39
38

37
36
35

34
33
32

31

30
29
28
27
26
25

1OE
1A1

1A2

GND

A3

1

A4

1

V

CC

A5

1

A6

1

GND

A7

1
1

A8
A1

2
2

A2

GND

2A3

A4

2

VCC

2

A5

2

A6

GND

2

A7

2A8

OE

2

ABSOLUTE MAXIMUM RATINGS

Symbol Description Max Unit

(2)

VTERM
VTERM
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –50 to +50 mA
I

IK Continuous Clamp Current, ±50 mA

IOK Continuous Clamp Current, VO < 0 –50 mA
I

CC Continuous Current through each ±100 mA

SS VCC or GND

I

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. V

3. All terminals except VCC.

Terminal Voltage with Respect to GND –0.5 to +4.6 V

(3)

Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V

VI < 0 or VI > VCC

CC terminals.

(1)

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol Parameter

CIN Input Capacitance VIN = 0V 5 7 pF
COUT Output Capacitance VOUT = 0V 7 9 pF
C

I/O I/O Port Capacitance VIN = 0V 7 9 pF

NOTE:

1. As applicable to the device type.

(1)

Conditions Typ. Max. Unit

PIN DESCRIPTION

Pin Names Description

xOE Output Enable Inputs (Active LOW)

DIR Direction Control Inputs

xAx Side A Inputs or 3-State Outputs
xBx Side B Inputs or 3-State Outputs

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

(1)

(1)

SSOP/ TSSOP/ TVSOP

TOP VIEW

FUNCTION T ABLE (EACH 8-BIT SECTION)

Inputs

xOE xDIR Outputs

L L Bus B Data to Bus A
L H Bus A Data to Bus B

H X High Z state

NOTE:

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care

2

(1)