Integrated Device Technology Inc IDT54823ATEB, IDT54823ATL, IDT54823ATLB, IDT54823ATP, IDT54823ATPB Datasheet

...

Integrated Device Technology Inc IDT54823ATEB, IDT54823ATL, IDT54823ATLB, IDT54823ATP, IDT54823ATPB, IDT54823ATPY, IDT54823ATPYB, IDT54823ATQ, IDT54823ATQB, IDT54823ATSO, IDT54823ATSOB, IDT54823BTD, IDT54823BTDB, IDT54823BTE, IDT54823BTEB, IDT54823BTL, IDT54823BTLB, IDT54823BTP, IDT54823BTPB, IDT54821ATDB, IDT54821ATE, IDT54821ATEB, IDT54821ATL, IDT54821BTQB, IDT54821BTSO, IDT54821BTSOB, IDT54821CTD, IDT54821CTDB, IDT54821CTE, IDT54821CTEB, IDT54821CTL, IDT54821CTLB, IDT54821CTP, IDT54823BTPY, IDT54823BTPYB, IDT54823BTQ, IDT54823BTQB, IDT54823BTSOB, IDT54823CTD, IDT54823CTDB, IDT54823CTE, IDT54823CTEB, IDT54823CTL, IDT54823CTLB, IDT54823CTP, IDT54823CTPB, IDT54823CTPY, IDT54823CTPYB, IDT54823CTQ, IDT54823CTQB, IDT54823CTSO, IDT54823CTSOB, IDT54821ATLB, IDT54821ATP, IDT54821ATPB, IDT54821ATPY, IDT54821ATPYB, IDT54821ATQ, IDT54821ATQB, IDT54821ATSO, IDT54821ATSOB, IDT54821BTD, IDT54821CTPB, IDT54821CTPY, IDT54821CTPYB, IDT54821CTQ, IDT54821CTQB, IDT54821CTSO, IDT54821CTSOB, IDT54823ATD, IDT54823ATDB, IDT54823ATE, IDT54821BTDB, IDT54821BTE, IDT54821BTEB, IDT54821BTL, IDT54821BTLB, IDT54821BTP, IDT54821BTPB, IDT54821BTPY, IDT54821BTPYB, IDT54821BTQ, IDT54823DTD, IDT54823DTDB, IDT54823DTE, IDT54823DTEB, IDT54823DTL, IDT54823DTLB, IDT54823DTP, IDT54823DTPB, IDT54823DTPY, IDT54825ATLB, IDT54825ATP, IDT54825ATPB, IDT54825ATPY, IDT54825ATPYB, IDT54825ATQ, IDT54825ATQB, IDT54825ATSO, IDT54825ATSOB, IDT54825BTD, IDT54825CTP, IDT54825CTPB, IDT54825CTPY, IDT54825CTPYB, IDT54825CTQ, IDT54825CTQB, IDT54825CTSO, IDT54825CTSOB, IDT54825BTDB, IDT54825BTE, IDT54825BTEB, IDT54825BTL, IDT54825BTLB, IDT54825BTP, IDT54825BTPB, IDT54825BTPY, IDT54825BTPYB, IDT54825BTQ, IDT54825BTQB, IDT54825BTSO, IDT54825BTSOB, IDT54825CTD, IDT54825CTDB, IDT54825CTE, IDT54825CTEB, IDT54825CTL, IDT54825CTLB, IDT54823DTPYB, IDT54823DTQ, IDT54823DTQB, IDT54823DTSO, IDT54823DTSOB, IDT54825ATD, IDT54825ATDB, IDT54825ATE, IDT54825ATEB, IDT54825ATL, IDT74821ATD, IDT74821ATDB, IDT74821ATE, IDT74821ATEB, IDT74821ATL, IDT74821ATLB, IDT74823ATSOB, IDT74823BTD, IDT74823BTDB, IDT74823BTE, IDT74823BTEB, IDT74823BTL, IDT74823BTLB, IDT74823BTP, IDT74823BTPB, IDT74823BTPY, IDT74821ATP, IDT74821ATPB, IDT74821ATPY, IDT74821ATPYB, IDT74821ATQ, IDT74821ATQB, IDT74821ATSO, IDT74821ATSOB, IDT74821BTD, IDT74821BTDB, IDT74821CTPB, IDT74821CTPY, IDT74821CTPYB, IDT74821CTQ, IDT74821CTQB, IDT74821CTSO, IDT74821CTSOB, IDT74823ATD, IDT74823ATDB, IDT74823ATE, IDT74821BTQB, IDT74821BTSO, IDT74821BTSOB, IDT74821CTD, IDT74821CTDB, IDT74821CTE, IDT74821CTEB, IDT74821CTL, IDT74821CTLB, IDT74821CTP, IDT74823DTQB, IDT74823DTSO, IDT74823DTSOB, IDT74825ATD, IDT74825ATDB, IDT74825ATEB, IDT74825ATL, IDT74825ATLB, IDT74825ATP, IDT74825ATPB, IDT74821BTE, IDT74821BTEB, IDT74821BTL, IDT74821BTLB, IDT74821BTP, IDT74821BTPB, IDT74821BTPY, IDT74821BTPYB, IDT74821BTQ, IDT74823CTLB, IDT74823CTP, IDT74823CTPB, IDT74823CTPY, IDT74823CTPYB, IDT74823CTQ, IDT74823CTQB, IDT74823CTSO, IDT74823CTSOB, IDT74823DTD, IDT74823ATEB, IDT74823ATL, IDT74823ATLB, IDT74823ATP, IDT74823ATPB, IDT74823ATPY, IDT74823ATPYB, IDT74823ATQ, IDT74823ATQB, IDT74823ATSO, IDT74823DTDB, IDT74823DTE, IDT74823DTEB, IDT74823DTL, IDT74823DTLB, IDT74823DTP, IDT74823DTPB, IDT74823DTPY, IDT74823DTPYB, IDT74823DTQ, IDT74823BTPYB, IDT74823BTQ, IDT74823BTQB, IDT74823BTSO, IDT74823BTSOB, IDT74823CTD, IDT74823CTDB, IDT74823CTE, IDT74823CTEB, IDT74823CTL, IDT74825BTEB, IDT74825BTL, IDT74825BTLB, IDT74825BTP, IDT74825BTPB, IDT74825BTPY, IDT74825BTPYB, IDT74825BTQ, IDT74825BTQB, IDT74825BTSO, IDT74825BTSOB, IDT74825CTD, IDT74825CTDB, IDT74825CTE, IDT74825CTEB, IDT74825CTL, IDT74825CTLB, IDT74825CTP, IDT74825CTPB, IDT74825CTPY, IDT74825CTQ, IDT74825CTQB, IDT74825CTSO, IDT74825CTSOB, IDT74825DTPY, IDT74825DTPYB, IDT74825ATPY, IDT74825ATPYB, IDT74825ATQ, IDT74825ATQB, IDT74825ATSO, IDT74825ATSOB, IDT74825BTD, IDT74825BTDB, IDT74825BTE Datasheet

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.21 1

Integrated Device Technology, Inc.

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT54/74FCT821AT/BT/CT

IDT54/74FCT823AT/BT/CT/DT

IDT54/74FCT825AT/BT/CT

FEATURES:

• Common features:

– Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility

– VOH = 3.3V (typ.) – V

OL = 0.3V (typ.)

– Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation

Enhanced versions

– Military product compliant to MIL-STD-883, Class B

and DESC listed (dual marked)

– Available in DIP, SOIC, SSOP, QSOP, CERPACK

and LCC packages

• Features for FCT821T/FCT823T/FCT825T:

– A, B, C and D speed grades – High drive outputs (-15mA IOH, 48mA IOL) – Power off disable outputs permit “live insertion”

DESCRIPTION:

The FCT82xT series is built using an advanced dual metal CMOS technology. The FCT82xT series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT821T are buffered, 10-bit wide versions of the popular FCT374T function. The FCT823T are 9-bit wide buffered registers with Clock Enable (EN) and Clear (

CLR

) – ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT825T are 8-bit buffered registers with all the FCT823T controls plus multiple enables (OE1, OE2, OE3) to allow multiuser control of the interface, e.g., CS, DMA and RD/WR. They are ideal for use as an output port requiring high I

OL/IOH.

The FCT82xT high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state.

MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995

1995 Integrated Device Technology, Inc 6.21 DSC-4202/5

FUNCTIONAL BLOCK DIAGRAM

CLR

2567 drw 01

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.21 2

PIN CONFIGURATIONS

FCT821 10-BIT REGISTER

2567 drw 04

2567 drw 03

FCT823 9-BIT REGISTER

2567 drw 02

INDEX

Y2 Y3 Y4 NC Y

GND

LCC

TOP VIEW

20 19

4 5 6 7 8

1817161514

9 10 11

1213

L28-1

D3 D4

D6 D7

Y6 Y7

262728

INDEX

NC Y

LCC

TOP VIEW

20 19

4 5 6 7 8

1817161514

9 10

1213

L28-1

GND

262728

CLR

INDEX

Y1 Y2 Y3 NC Y

VCCOE

LCC

TOP VIEW

20 19

4 5 6 7 8

1817161514

9 10 11

1213

L28-1

D5 D6

GND

Y5 Y6

262728

CLR

GND

1 2 3 4 5 6 7 8 9 10

P24-1

D24-1 SO24-2 SO24-7 SO24-8

E24-1

11 12

CLR

DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEW

D1 D2 D3 D4 D5 D6 D7

GND

Y1 Y2 Y3 Y4

VCC1 2 3 4 5 6 7 8 9 10

P24-1

D24-1 SO24-2 SO24-7 SO24-8

E24-1

11 12

Y8 Y9

DIP/SOIC/SSOP/QSOP/CERPACK

TOP VIEW

FCT825 8-BIT REGISTER

OE1

D0 D1 D2 D3 D4 D5 D6 D7

GND

Y1 Y2 Y3 Y4

VCC1 2 3 4 5 6 7 8 9 10

P24-1

D24-1 SO24-2 SO24-8

E24-1

11 12

DIP/SOIC/QSOP/CERPACK

TOP VIEW

OE2

CLR

OE3

IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.21 3

FUNCTION TABLE

(1)

PIN DESCRIPTION

2567 tbl 01

ABSOLUTE MAXIMUM RATINGS

(1)

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Rating Commercial Military Unit

VTERM

(2)

Terminal Voltage with Respect to GND

–0.5 to +7.0 –0.5 to +7.0 V

VTERM

(3)

Terminal Voltage with Respect to GND

–0.5 to

CC +0.5

–0.5 to

VCC +0.5

TA Operating

Temperature

0 to +70 –55 to +125 °C

TBIAS Temperature

Under Bias

–55 to +125 –65 to +135 °C

TSTG Storage

Temperature

–55 to +125 –65 to +150 °C

PT Power Dissipation 0.5 0.5 W IOUT DC Output

Current

–60 to +120 –60 to +120 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed V

CC by +0.5V unless otherwise noted.

2. Input and V

CC terminals only.

3. Outputs and I/O terminals only.

NOTE:

1. This parameter is measured at characterization but not tested.

2567 lnk 03

2567 lnk 04

Symbol Parameter

(1)

Conditions Typ. Max. Unit

CIN Input

Capacitance

VIN = 0V 6 10 pF

COUT Output

Capacitance

VOUT = 0V 8 12 pF

Inputs

Internal/ Outputs

OEOECLR

CLRENEN

DI CP QI YI

Function

H H

L L

↑ ↑

Z Z

High Z

L L

X X

L L

Z L

Clear

H H

X X

XXNC

NCZNC

Hold

H H

L L

H H H H

L L L L

↑ ↑ ↑ ↑

Z Z L

Load

Names I/O Description

DI I The D flip-flop data inputs.

CLR

I When the clear input is LOW and OE is

LOW, the Q

I outputs are LOW. When

the clear input is HIGH, data can be entered into the register.

CP I Clock Pulse for the Register; enters

data into the register on the LOW-toHIGH transition.

YI O The register 3-state outputs.

I Clock Enable. When the clock enable is

LOW, data on the D

I input is transferred

to the Q

I output on the LOW-to-HIGH

clock transition. When the clock enable is HIGH, the Q

I outputs do not change

state, regardless of the data or clock input transitions.

I Output Control. When the OE input is

HIGH, the Y

I outputs are in the high-

impedance state. When the OE input is LOW, the TRUE register data is present at the Y

I outputs.

NOTE: 2567 tbl 02

1. H = HIGH L = LOW X = Don’t Care NC = No Change ↑ = LOW-to-HIGH Transition Z = High Impedance

+ 6 hidden pages

Integrated Device Technology Inc IDT54823ATEB, IDT54823ATL, IDT54823ATLB, IDT54823ATP, IDT54823ATPB Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual