IDT IDT72V7230, IDT72V7240, IDT72V7250, IDT72V7260, IDT72V7270 User Manual

...

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3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 72-BIT FIFO 512 x 72, 1,024 x 72 2,048 x 72, 4,096 x 72 8,192 x 72, 16,384 x 72 32,768 x 72, 65,536 x 72

FEATURES:

••

Choose among the following memory organizations:

•

••

IDT72V7230 IDT72V7240 IDT72V7250 IDT72V7260 IDT72V7270 IDT72V7280 IDT72V7290 IDT72V72100

••

• 100 MHz operation (10 ns read/write cycle time)

••

User selectable input and output port bus-sizing

•

••

- x72 in to x72 out

- x72 in to x36 out

- x72 in to x18 out

- x36 in to x72 out

- x18 in to x72 out

••

•

Big-Endian/Little-Endian user selectable word representation

••

• Fixed, low first word latency

••

• Zero latency retransmit

••

• Auto power down minimizes standby power consumption

••



 512 x 72

 

 1,024 x 72

 

 2,048 x 72

 

 4,096 x 72

 

 8,192 x 72

 

 16,384 x 72

 

 32,768 x 72

 

 65,536 x 72



IDT72V7230, IDT72V7240 IDT72V7250, IDT72V7260 IDT72V7270, IDT72V7280

IDT72V7290, IDT72V72100

••

•

Master Reset clears entire FIFO

••

•

Partial Reset clears data, but retains programmable settings

••

•

Empty, Full and Half-Full flags signal FIFO status

••

• Programmable Almost-Empty and Almost-Full flags, each flag can

••

default to one of eight preselected offsets

••

• Selectable synchronous/asynchronous timing modes for Almost-

••

Empty and Almost-Full flags

••

• Program programmable flags by either serial or parallel means

••

• Select IDT Standard timing (using EF and FF flags) or First Word

••

Fall Through timing (using OR and IR flags)

••

Output enable puts data outputs into high impedance state

•

••

• Easily expandable in depth and width

••

• Independent Read and Write Clocks (permit reading and writing

••

simultaneously)

••

• Asynchronous operation of Output Enable, OE

••

•

Read Chip Select ( RCS ) on Read Side

••

• Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)

••

• Features JTAG (Boundary Scan)

••

• High-performance submicron CMOS technology

••

• Industrial temperature range (–40

••

°°

°C to +85

°°

°C) is available

°°

FUNCTIONAL BLOCK DIAGRAM

WEN

WCLK

WRITE CONTROL

LOGIC

WRITE POINTER

MRS

PRS

TCK

TRST

TMS TDO

TDI

CONTROL

LOGIC

BUS

CONFIGURATION

RESET

LOGIC

JTAG

CONTROL

(BOUNDARY SCAN)

-D

(x72, x36 or x18)

INPUT REGISTER

RAM ARRAY

512 x 72 1,024 x 72 2,048 x 72 4,096 x 72

8,192 x 72 16,384 x 72 32,768 x 72 65,536 x 72

OUTPUT REGISTER

Q0 -Qn (x72, x36 or x18)

SEN

OFFSET REGISTER

FLAG

LOGIC

READ POINTER

READ

CONTROL

LOGIC

SCLK

RCLK

REN

RCS

FF/IR PAF EF/OR PAE HF

FWFT/SI PFM FSEL0

FSEL1

4680 drw01

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

DECEMBER 2003

DSC-4680/9

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

COMMERCIAL TEMPERATURE RANGE

DESCRIPTION:

The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/ 72V7290/72V72100 are exceptionally deep, high speed, CMOS First-In-FirstOut (FIFO) memories with clocked read and write controls and a flexible BusMatching x72/x36/x18 data flow.

These FIFOs offer several key user benefits:

• Flexible x72/x36/x18 Bus-Matching on both read and write ports

• The period required by the retransmit operation is fixed and short.

• The first word data latency period, from the time the first word is written to an

empty FIFO to the time it can be read, is fixed and short.

• High density offerings up to 4 Mbit

PIN CONFIGURATION

A1 BALL PAD CORNER

Q33

Q35

Q47

Q50

Q53

Q65

Q32

Q34

Q46

Q49

Q52

Q64

Q30

Q45

Q31

Q48

Q51

Q63

Q29

Q28

Q27

VCC

GND

VCC

GND

Q17

Q16

Q15

VCC

Q14

Q13

Q12

GND

VCC

Q11

Q10

VCC

GND

VCC

GND

Q62

Q61

Q60

VCC

GND

Q59

Q58

Q57

VCC

GND

Q56

Q55

Q54

VCC

Q44

Q43

Q42

VCC

GND

VCC

Q41

Q40

Q39

VCC

GND

VCC

Q38

Q37

Q36

PFM

Q26

Q25

Q18

Q24

Q21

Q19

Q23

Q22

Q20

Q68

Q67

Q66

GND

RCS

REN

Q71

Q70

Q69

TCK

VCC

GND

PAE

RCLK

Bus-Matching Sync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.

Each FIFO has a data input port (D

n) and a data output port (Qn), both of

which can assume either a 72-bit, 36-bit or a 18-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), and BusMatching (BM) pin during the Master Reset cycle.

The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input

D71

D70

D69

TDI

GND

FS1

MRS

PAF

D68

D67

D66

TRST

VCC

FS0

PRS

WEN

WCLK

D65

D64

D63

TDO

GND

FWFT/ SI

D50

D53

D49

D52

D48

D51

TMS

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

GNDVCC

GND SCLK

SEN

D47

D46

D45

D27

D15

D12

D60

D57

D54

D42

D39

D36

D18

D19

D20

D35

D34

D30

D28

D16

D13

D10

D61

D58

D55

D43

D40

D37

D25

D21

D22

D33

D32

D31

D29

D17

D14

D11

D62

D59

D56

D44

D41

D38

D26

D24

D23

12 3456 78910111213141516

4680 drw02

PBGA (BB256-1, order code: BB)

TOP VIEW

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

COMMERCIAL TEMPERATURE RANGE

DESCRIPTION (CONTINUED)

and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. An Output Enable (OE) input is provided for three-state control of the outputs.

A Read Chip Select (RCS) input is also provided for synchronous enable and disable of the read port control input, REN. The RCS input is synchronized to the read clock, and also provides three-state control of the Q RCS is disable, REN will be disabled internally and data outputs will be in High-Impedance state.

The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other.

There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use.

n outputs. When

For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial. Eight default offset settings are also provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and the PAF threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins.

For serial programming, SEN together with LD on each rising edge of SCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WEN together with LD on each rising edge of WCLK, are used to load the offset registers via D

n. REN together with LD on each rising edge

of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected.

PARTIAL RESET (PRS)

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

(x72, x36, x18) DATA IN (D

0 - Dn)

SERIAL IN CLOCK(SCLK)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE ALMOST-FULL (PAF)

INTERSPERSED/

NON-INTERSPERSED PARITY (IP)

BIG-ENDIAN/LITTLE-ENDIAN (BE)

INPUT WIDTH (IW)

MASTER RESET (MRS)

IDT 72V7230 72V7240 72V7250 72V7260 72V7270 72V7280 72V7290

72V72100

BUS-

MATCHING

(BM)

READ CLOCK (RCLK) READ ENABLE (REN) READ CHIP SELECT (RCS) OUTPUT ENABLE (OE) (x72, x36, x18) DATA OUT (Q0 - Qn)

RETRANSMIT (RT)

EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE) HALF-FULL FLAG (HF)

JTAG CLOCK (TCLK)

JTAG RESET (TRST)

JTAG MODE (TMS)

(TDO)

(TDI)

OUTPUT WIDTH (OW)

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Figure 1. Single Device Configuration Signal Flow Diagram

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

COMMERCIAL TEMPERATURE RANGE

During Master Reset (MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode.

The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programming method, and default or programmed offset settings existing before Partial Reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable.

It is also possible to select the timing mode of the PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAE and PAF flags.

If asynchronous PAE/PAF configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOWto-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOWto-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.

If synchronous PAE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during master reset by the state of the Programmable Flag Mode (PFM) pin.

The Retransmit function allows data to be reread from the FIFO more than once. A LOW on the RT input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. A zero-latency retransmit timing mode can be selected using the Retransmit timing Mode pin (RM). During Master Reset, a LOW on RM will select zero latency retransmit. A HIGH on RM during Master Reset will select normal latency.

If zero latency retransmit operation is selected, the first data word to be retransmitted will be placed on the output register with respect to the same RCLK edge that initiated the retransmit based on RT being LOW.

Refer to Figure 16 and 17 for Retransmit Timing with normal latency. Refer to Figure 18 and 19 for Zero Latency Retransmit Timing.

The device can be configured with different input and output bus widths as

shown in Table 1.

A Big-Endian/Little-Endian data word format is provided. This function is useful when the FIFO is used in Bus-Matching mode, to determine order of the words. As an example, if Big-Endian mode is selected, then the most significant word of the long word written into the FIFO will be read out of the FIFO first, followed by the least significant word. If Little-Endian format is selected, then the least significant word of the long word written into the FIFO will be read out first, followed by the most significant word. The mode desired is configured during master reset by the state of the Big-Endian (BE) pin.

The Interspersed/Non-Interspersed Parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFO will assume that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If Non-Interspersed Parity mode is selected, then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during Master Reset by the state of the IP input pin.

If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state.

Both an Asynchronous Output Enable pin (OE) and Synchronous Read Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip Select is synchronized to the RCLK. Both the output enable and read chip select control the output buffer of the FIFO, causing the buffer to be either HIGH impedance or LOW impedance.

JTAG test pins are also provided, the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.

The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/ 72V7290/72V72100 are fabricated using IDT’s high speed submicron CMOS technology.

TABLE 1 — BUS-MATCHING CONFIGURATION MODES

BM IW OW Write Port Width Read Port Width

L X X x72 x72 H H L x36 x72 H H H x18 x72 H L L x72 x36 H L H x72 x18

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol Name I/O Description

0–D71 Data Inputs I Data inputs for a 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused input pins should be tied

LOW.

MRS Master Reset I MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset,

the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmable flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.

PRS Partial Reset I PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,

the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained.

RT Retransmit I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to

HIGH in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable flag settings. RT is useful to reread data from the first physical location of the FIFO.

FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions

Through/Serial In as a serial input for loading offset registers. O W Output Width I This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration. I W Input Width I This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration. BM Bus-Matching I BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size

configuration.

BE Big-Endian/ I During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset

Little-Endian will select Little-Endian format. RM Retransmit Timing I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select

Mode normal latency mode. PFM Programmable I During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on

Flag Mode PFM will select Synchronous Programmable flag timing mode. IP Interspersed Parity I During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed

Parity mode.

FSEL0 Flag Select Bit 0 I During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the

programmable flags PAE and PAF. There are up to eight possible settings available.

FSEL1 Flag Select Bit 1 I During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the

programmable flags PAE and PAF. There are up to eight possible settings available.

WCLK Write Clock I When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the programmable

registers for parallel programming. WEN Write Enable I WEN enables WCLK for writing data into the FIFO memory and offset registers. RCLK Read Clock I When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the

programmable registers. (RCS must be active).

REN Read Enable I REN enables RCLK for reading data from the FIFO memory and offset registers. (RCS must be active). OE Output Enable I OE provides asynchronous control of the output impedance of Q

input is the only input that provide High-Impedance control of the data outputs. RCS Read Chip Select I RCS provides synchronous control of the read port and output impedance of Q

a Master or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance

regardless of RCS. SCLK Serial Input Clock I when enabled by SEN, the rising edge of SCLK writes one bit of data (present on the SI input), into the

programmable register for serial programming.

SEN Serial Enable I SEN enables serial loading of programmable flag offsets. LD Load I This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,

determines one of eight default offset values for the PAE and PAF flags, along with the method by which these

offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing

to and reading from the offset registers. FF/IR Full Flag/ O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full.

Input Ready In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing

to the FIFO memory.

n. During a Master or Partial Reset the OE

n, synchronous to RCLK. During

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTION (CONTINUED)

Symbol Name I/O Description

EF/OR Empty Flag/ O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.

Output Ready In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs.

PAF Programmable O PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in

Almost-Full Flag the Full Offset register. PAF goes LOW if the number offree locations in the FIFO memory is less than or

equal to m.

PAE Programmable O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty

Almost-Empty Offset register. PAE goes HIGH if the number of Flag words in the FIFO memory is greater than or equal to

offset n.

HF Half-Full Flag O HF indicates whether the FIFO memory is more or less than half-full.

0–Q71 Data Outputs O Data outputs for an 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused output pins should not

be connected. Data Outputs are not 5V tolerant regardless of the state of the OE and RCS.

(1)

TCK

TDI

TDO

TMS

TRST

NOTE:

1. These pins are for the JTAG port. Please refer to pages 22-25 and Figures 5-7.

JTAG Clock I Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations

of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.

(1)

JTAG Test Data Input I One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,

test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.

(1)

JTAG Test Data Output O One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,

test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.

(1)

JTAG Mode Select I TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the

the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.

(1)

JTAG Reset I TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically

reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Unit

TERM Terminal Voltage –0.5 to +4.5 V

with respect to GND

STG Storage –55 to +125 °C

Temperature

OUT DC Output Current –50 to +50 mA

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 3.15 3.3 3.45 V

V GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.0 — VCC+0.3 V

(1)

V T

NOTES:

1. V

2. 1.5V undershoots are allowed for 10ns once per cycle.

Input Low Voltage — — 0.8 V

A Operating Temperature 0 — 70 °C

Commercial

CC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; JEDEC JESD8-A compliant)

IDT72V7230L IDT72V7240L IDT72V7250L IDT72V7260L IDT72V7270L IDT72V7280L IDT72V7290L IDT72V72100L

Commercial

CLK = 10, 15 ns

Symbol Parameter Min. Max. Unit

(1)

(2)

I V

OH Output Logic “1” Voltage, IOH = –2 mA 2.4 — V

OL Output Logic “0” Voltage, IOL = 4 mA — 0.4 V

(3,4,5)

CC1

(3,6)

CC2

NOTES:

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2. OE

≥ VIH, 0.4 ≤ VOUT ≤ VCC.

3. Tested with outputs open (IOUT = 0).

4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

5. Typical I f

S/2, CL = capacitive load (in pF).

6. All Inputs = V

Input Leakage Current –1 0 1 0 µ A Output Leakage Current –1 0 1 0 µA

Active Power Supply Current — 7 5 mA Standby Current — 15 mA

CC1 = 15.5 + 2.275*fS + 0.002*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at

CC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

(2)

Capacitance

(1,2)

OUT

Capacitance

NOTES:

1. With output deselected, (OE ≥ V

2. Characterized values, not currently tested.

(1)

Conditions Max. Unit

Input VIN = 0V 10 pF

Output VOUT = 0V 10 pF

IH).

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

AC ELECTRICAL CHARACTERISTICS

(1)

COMMERCIAL TEMPERATURE RANGE

(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; JEDEC JESD8-A compliant)

Commercial

IDT72V7230L10 IDT72V7230L15 IDT72V7240L10 IDT72V7240L15 IDT72V7250L10 IDT72V7250L15 IDT72V7260L10 IDT72V7260L15 IDT72V7270L10 IDT72V7270L15 IDT72V7280L10 IDT72V7280L15 IDT72V7290L10 IDT72V7290L15 IDT72V72100L10 IDT72V72100L15

Symbol Parameter Min. Max. Min. Max. Unit

S Clock Cycle Frequency — 100 — 66.7 MHz A Data Access Time 1 6.5 1 10 ns

CLK Clock Cycle Time 10 — 15 — ns

CLKH Clock High Time 4.5 — 6 — ns

CLKL Clock Low Time 4.5 — 6 — ns

DS Data Setup Time 3.5 — 4 — ns

DH Data Hold Time 0.5 — 1 — ns

ENS Enable Setup Time 3.5 — 4 — ns

ENH Enable Hold Time 0.5 — 1 — ns

LDS Load Setup Time 3 .5 — 4 — ns

LDH Load Hold Time 0.5 — 1 — ns

RS Reset Pulse Width

RSS Reset Setup Time 10 — 15 — ns

RSR Reset Recovery Time 1 0 — 15 — ns

RSF Reset to Flag and Output Time — 15 — 1 5 ns

FWFT Mode Select Time 0 — 0 — ns

RTS Retransmit Setup Time 3.5 — 4 — ns

OLZ Output Enable to Output in Low Z

OE Output Enable to Output Valid 1 6 1 8 ns

OHZ Output Enable to Output in High Z

WFF Write Clock to FF or IR — 6.5 — 10 ns

REF Read Clock to EF or OR — 6.5 — 10 ns

PAFA Clock to Asynchronous Programmable Almost-Full Flag — 16 — 20 ns

PAFS Write Clock to Synchronous Programmable Almost-Full Flag — 6.5 — 1 0 ns

PAEA Clock to Asynchronous Programmable Almost-Empty Flag — 1 6 — 2 0 ns

PAES Read Clock to Synchronous Programmable Almost-Empty Flag — 6.5 — 10 ns

HF Clock to HF —16—20ns

RCSS RCS Setup Time 3.5 — 5 — ns

RCSH RCS Hold Time 0.5 — 1 — ns

RCSLZ RCLK to Active from High-Z

RCSHZ RCLK to High-Z

SKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 7—9—ns

SKEW2 Skew time between RCLK and WCLK for PAE and PAF 10 — 14 — ns

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

4. Data Sheet slow conditions: 85°c, 3.0V. Data Sheet fast conditions: -40°c, 3.6V.

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 2

(2)

(3)

10 — 15 — ns

1—1—ns

1618ns

1 6.5 1 10 ns 1 6.5 1 10 ns

3.3V

330Ω

D.U.T.

510Ω

Figure 2. Output Load

* Includes jig and scope capacitances

30pF*

4680 drw04

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

COMMERCIAL TEMPERATURE RANGE

FUNCTIONAL DESCRIPTION

TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE

The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/ 72V7290/72V72100 support two different timing modes of operation: IDT Standard mode or First Word Fall Through (FWFT) mode. The selection of which mode will operate is determined during Master Reset, by the state of the FWFT/SI input.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO. It also uses the Full Flag function (FF) to indicate whether or not the FIFO has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate whether or not the FIFO has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK.

Various signals, both input and output signals operate differently depending

on which timing mode is in effect.

IDT STANDARD MODE

In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN) must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of the Write Clock (WCLK). After the first write is performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table

2. This parameter is also user programmable. See section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read operations were taking place, the Half-Full flag (HF) would toggle to LOW once the 257th word for IDT72V7230, 513rd word for IDT72V7240, 1,025th word for IDT72V7250, 2,049th word for IDT72V7260, 4,097th word for IDT72V7270, 8,193th word for the IDT72V7280, 16,385th word for the IDT72V7290 and 32,769th word for the IDT72V72100, respectively was written into the FIFO. Continuing to write data into the FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW after (512-m) writes for the IDT72V7230, (1,024-m) writes for the IDT72V7240, (2,048-m) writes for the IDT72V7250, (4,096-m) writes for the IDT72V7260, (8,192-m) writes for the IDT72V7270, (16,384-m) writes for the IDT72V7280, (32,768-m) writes for the IDT72V7290 and (65,536-m) writes for the IDT72V72100. The offset “m” is the full offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading.

When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write operations. If no reads are performed after a reset, FF will go LOW after D writes to the FIFO. D = 512 writes for the IDT72V7230, 1,024 writes for the IDT72V7240, 2,048 writes for the IDT72V7250, 4,096 writes for the IDT72V7260, 8,192 writes for the IDT72V7270, 16,384 writes for the IDT72V7280, 32,768 writes for the IDT72V7290, 65,536 writes for the IDT72V72100, respectively.

If the FIFO is full, the first read operation will cause FF to go HIGH. Subsequent read operations will cause PAF and HF to go HIGH at the conditions described in Table 3. If further read operations occur, without write operations, PAE will go LOW when there are n words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, the EF will go LOW inhibiting further read operations. REN is ignored when the FIFO is empty.

When configured in IDT Standard mode, the EF and FF outputs are double register-buffered outputs.

Relevant timing diagrams for IDT Standard mode can be found in Figure 10,11,12,16 and 18.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of WCLK. After the first write is performed, the Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table

2. This parameter is also user programmable. See section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read operations were taking place, the HF would toggle to LOW once the 258th word for the IDT72V7230, 514th word for the IDT72V7240, 1,026th word for the IDT72V7250, 2,050th word for the IDT72V7260, 4,098th word for the IDT72V7270, 8,194th word for the IDT72V7280, 16,386th word for the IDT72V7290 and 32,770th word for the IDT72V72100, respectively was written into the FIFO. Continuing to write data into the FIFO will cause the PAF to go LOW. Again, if no reads are performed, the PAF will go LOW after (513-m) writes for the IDT72V7230, (1,025-m) writes for the IDT72V7240, (2,049-m) writes for the IDT72V7250, (4,097-m) writes for the IDT72V7260 and (8,193-m) writes for the IDT72V7270, 16,385 writes for the IDT72V7280, 32,769 writes for the IDT72V7290 and 65,537 writes for the IDT72V72100, where m is the full offset value. The default setting for these values are stated in the footnote of Table 2.

When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations. If no reads are performed after a reset, IR will go HIGH after D writes to the FIFO. D = 513 writes for the IDT72V7230, 1,025 writes for the IDT72V7240, 2,049 writes for the IDT72V7250, 4,097 writes for the IDT72V7260 and 8,193 writes for the IDT72V7270, 16,385 writes for the IDT72V7280, 32,769 writes for the IDT72V7290, 65,537 writes for the IDT72V72100, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register.

If the FIFO is full, the first read operation will cause the IR flag to go LOW. Subsequent read operations will cause the PAF and HF to go HIGH at the conditions described in Table 4. If further read operations occur, without write operations, the PAE will go LOW when there are n + 1 words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, OR will go HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.

When configured in FWFT mode, the OR flag output is triple registerbuffered, and the IR flag output is double register-buffered.

Relevant timing diagrams for FWFT mode can be found in Figure 13, 14,15, 17, and 19.

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

COMMERCIAL TEMPERATURE RANGE

TABLE 2 — DEFAULT PROGRAMMABLE FLAG OFFSETS

IDT72V7230, 72V7240

LD FSEL1 FSEL0 Offsets n,m

LH L511 L L H 255 L L L 127

LHH63 HL L31 HH L15 HLH7 HH H3

LD FSEL1 FSEL0 Program Mode

H X X Serial

L X X Parallel

IDT72V7250, 72V7260, 72V7270, 72V7280

LD FSEL1 FSEL0 Offsets n,m

H L L 1,023

LH L511

L L H 255

L L L 127

LHH63 HH L31 HLH15 HH H7

LD FSEL1 FSEL0 Program Mode

H X X Serial

L X X Parallel

IDT72V7290, 72V72100

LD FSEL1 FSEL0 Offsets n,m

L H L 16,383 L L H 8,191 L H H 4,095 H H L 2,047 H L L 1,023 HLH511 HHH255 LLL127

(3)

(4)

(3)

(4)

PROGRAMMING FLAG OFFSETS

Full and Empty Flag offset values are user programmable. The IDT72V7230/ 72V7240/72V7250/72V7260/72V7270/72V7280/72V7290/72V72100 have internal registers for these offsets. There are eight default offset values selectable during Master Reset. These offset values are shown in Table 2. Offset values can also be programmed into the FIFO in one of two ways; serial or parallel loading method. The selection of the loading method is done using the LD (Load) pin. During Master Reset, the state of the LD input determines whether serial or parallel flag offset programming is enabled. A HIGH on LD during Master Reset selects serial loading of offset values. A LOW on LD during Master Reset selects parallel loading of offset values.

In addition to loading offset values into the FIFO, it is also possible to read the current offset values. Offset values can be read via the parallel output port Q

0-Qn, regardless of the programming mode selected (serial or parallel). It is

not possible to read the offset values in serial fashion.

Figure 3, Programmable Flag Offset Programming Sequence, summaries the control pins and sequence for both serial and parallel programming modes. For a more detailed description, see discussion that follows.

The offset registers may be programmed (and reprogrammed) any time after Master Reset, regardless of whether serial or parallel programming has been selected. Valid programming ranges are from 0 to D-1.

SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION

The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/ 72V7290/72V72100 can be configured during the Master Reset cycle with either synchronous or asynchronous timing for PAF and PAE flags by use of the PFM pin.

If synchronous PAF/PAE configuration is selected (PFM, HIGH during MRS), the PAF is asserted and updated on the rising edge of WCLK only and not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous PAF timing and Figure 24 for synchronous PAE timing.

If asynchronous PAF/PAE configuration is selected (PFM, LOW during

MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE

is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure 25 for asynchronous PAF timing and Figure 26 for asynchronous PAE timing.

LD FSEL1 FSEL0 Program Mode

H X X Serial

L X X Parallel

NOTES:

1. n = empty offset for PAE.

2. m = full offset for PAF.

3. As well as selecting serial programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.

4. As well as selecting parallel programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.

(3)

(4)

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

COMMERCIAL TEMPERATURE RANGE

PAE EF

HL L

FF PAF

(1)

1 to n

IDT72V7260

(1)

1 to n

LHH

(n+1) to 2,048

(n+1) to 1,024

HHLH H

4,096

(4,096-m) to 4,095

2,049 to (4,096-(m+1))

to 2,047

2,048

(2048-m)

1,025 to (2048-(m+1))

PAE EF

HL L

FF PAF

(1)

1 to n

IDT72V72100

(1)

1 to n

IDT72V7290

LH H

(n+1) to 32,768

LH H

HHLH H

to 65,535

65,536

(65,536-m)

32,769 to (65,536-(m+1))

(32,768-m) to 32,767

16,385 to (32,768-(m+1))

PAE OR

IR PAF

IDT72V7250 IDT72V7260IDT72V7230

LH L

HL H

1 to n+1

(n+2) to 1,025 (n+2) to 2,049

LH L

LHLHL

to 4,096

(4,097-m)

2,049 4,097

(2,049-m) to 2,048

1,026 to (2,049-(m+1)) 2,050 to (4,097-(m+1))

PAE OR

HL H

IR PAF

1 to n+1

IDT72V7290 IDT72V72100

(n+2) to 32,769

4680 drw 05

LHL

LHLH L

65,537

(65,537-m) to 65,536

32,770 to (65,537-(m+1))

to 32,768

(32,769-m)

16,386 to (32,769-(m+1))

(1)

1 to n

(1)

1 to n

Number of

(n+1) to 512

(n+1) to 256

Words in

IDT72V7240 IDT72V7250

IDT72V7230

TABLE 3 STATUS FLAGS FOR IDT STANDARD MODE

1,024

(1024-m) to 1,023

513 to (1,024-(m+1))

512

(512-m) to 511

257 to (512-(m+1))

FIFO

(

1 to n

(1)

1 to n

IDT72V7270 IDT72V7280

Number of

to 16,383

(n+1) to 8,192 (n+1) to 16,384

(16,384-m)

8,193 to (16,384-(m+1))

to 8,191

(n+1) to 4,096

(8,192-m)

4,097 to (8,192-(m+1))

Words in

FIFO

16,384 32,768

8,192

NOTE:

1. See table 2 for values for n, m.

1 to n+1

IDT72V7240

1 to n+1

TABLE 4 STATUS FLAGS FOR FWFT MODE

Number of

to 1,024

(n+2) to 513

(1,025-m)

514 to (1,025-(m+1))

to 512

(n+2) to 257

(513-m)

258 to (513-(m+1))

Words in

FIFO

1,025

513

1 to n+1

IDT72V7270 IDT72V7280

Number of

Words in

to 16,384

16,385 32,769

(n+2) to 8,193 (n+2) to 16,385

(16,385-m)

8,194 to (16,385-(m+1))

to 8,192

8,193

(n+2) to 4,097

(8,193-m)

4,098 to (8,193-(m+1))

FIFO

NOTE:

1. See table 2 for values for n, m.

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

WEN

REN

SEN

WCLK RCLK

SCLK

COMMERCIAL TEMPERATURE RANGE

IDT72V7230 IDT72V7240 IDT72V7250 IDT72V7260 IDT72V7270 IDT72V7280 IDT72V7290 IDT72V72100

Parallel write to registers: Empty Offset Full Offset

Parallel read from registers: Empty Offset

Full Offset

Serial shift into registers:

18 bits for the IDT72V7230 20 bits for the IDT72V7240 22 bits for the IDT72V7250 24 bits for the IDT72V7260 26 bits for the IDT72V7270 28 bits for the IDT72V7280 30 bits for the IDT72V7290 32 bits for the IDT72V72100

1 bit for each rising WCLK edge

Starting with Empty Offset (LSB) Ending with Full Offset (MSB)

No Operation

Write Memory

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

Figure 3. Programmable Flag Offset Programming Sequence

Read Memory

No Operation

4680 drw06

IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO

512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72

COMMERCIAL TEMPERATURE RANGE

D/Q71 D/Q19

D/Q35 D/Q19

1st Parallel Offset Write/Read Cycle

D/Q17

D/Q8

EMPTY OFFSET REGISTER (PAE)

1415

910111213

2nd Parallel Offset Write/Read Cycle

D/Q17

D/Q8

FULL OFFSET REGISTER (PAF)

910111213

1415

x72 Bus Width

1st Parallel Offset Write/Read Cycle

D/Q17

EMPTY OFFSET REGISTER (PAE)

1415

910111213

D/Q8

# of Bits Used

D/Q0

Non-Interspersed

56781213

234 234

D/Q0

234 234

D/Q0

234 234

Parity

Interspersed Parity

Non-Interspersed Parity

Interspersed Parity

Non-Interspersed Parity

Interspersed Parity

D/Q35 D/Q19

D/Q17

FULL OFFSET REGISTER (PAF)

2nd Parallel Offset Write/Read Cycle

1415

1st Parallel Offset Write/Read Cycle

D/Q17

Data Inputs/Outputs

EMPTY OFFSET (LSB) REGISTER (PAE)

1415

1213

D/Q8

2nd Parallel Offset Write/Read Cycle

D/Q17

D/Q16

Data Inputs/Outputs

FULL OFFSET (LSB) REGISTER (PAF)

1112

1011121314

D/Q8

141516

x18 Bus Width

D/Q8

910111213

x36 Bus Width

56789101112131415 5678

# of Bits Used

2345678

56781213

# of Bits Used

D/Q0D/Q16

Non-Interspersed Parity

1234

Interspersed

1234

Parity

D/Q0

12345678910 1

234 234

D/Q0

Non-Interspersed Parity

Interspersed Parity

# of Bits Used:

09 bits for the IDT72V7230 10 bits for the IDT72V7240 11 bits for the IDT72V7250 12 bits for the IDT72V7260 13 bits for the IDT72V7270 14 bits for the IDT72V7280 15 bits for the IDT72V7290 16 bits for the IDT72V72100 Note: All unused input bits are don’t care.

4680 drw07

Figure 3. Programmable Flag Offset Programming Sequence (Continued)

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IDT IDT72V7230, IDT72V7240, IDT72V7250, IDT72V7260, IDT72V7270 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual