IDT IDT72V3686, IDT72V3696, IDT72V36106 User Manual

3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING

16,384 x 36 x 2
32,768 x 36 x 2
65,536 x 36 x 2

FEATURES

••

• Memory storage capacity:

••

IDT72V3686 – 16,384 x 36 x 2
IDT72V3696 – 32,768 x 36 x 2
IDT72V36106 – 65,536 x 36 x 2

••

•

Clock frequencies up to 100 MHz (6.5ns access time)

••

••

Two independent FIFOs buffer data between one bidirectional

•

••

36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)

••

• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on

••

Ports B and C

••

• Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag

••

functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)

••

• Programmable Almost-Empty and Almost-Full flags; each has

••

five default offsets (8, 16, 64, 256 and 1024)

FUNCTIONAL BLOCK DIAGRAM

Mail 1

Write

Pointer

Register

RAM ARRAY

16,384 x 36
32,768 x 36
65,536 x 36

Status Flag

Logic

Status Flag

Logic

CLKA

CSA

W/RA

ENA

MBA

LOOP

MRS1

PRS1

FFA/IRA

AFA

FS2

FS0/SD

FS1/SEN

0-A35

A

EFA/ORA

AEA

Port-A

Control

Logic

FIFO1,
Mail1
Reset
Logic

36 36

Input

Register

36

FIFO1

Programmable Flag

Offset Registers

16

FIFO2

IDT72V3686
IDT72V3696

IDT72V36106

••

•

Serial or parallel programming of partial flags

••

••

•

Big- or Little-Endian format for word and byte bus sizes

••

••

•

Loopback mode on Port A

••

••

• Retransmit Capability

••

••

Master Reset clears data and configures FIFO, Partial Reset

•

••

clears data but retains configuration settings

••

• Mailbox bypass registers for each FIFO

••

••

• Free-running CLKA, CLKB and CLKC may be asynchronous or

••

coincident (simultaneous reading and writing of data on a single
clock edge is permitted)

••

Auto power down minimizes power dissipation

•

••

••

• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

••

••

• Pin compatible to the lower density parts, IDT72V3626/72V3636/

••

72V3646/72V3656/72V3666/72V3676

••

• Industrial temperature range (–40

••

Output

Register

Read

Pointer

Timing

Mode

Matching

Output Bus-

°°

°C to +85

°°

°°

°C) is available

°°

18

Port-B

Control

Logic

Common

Port

Control

Logic

(B and C)

MBF1

B

0-B17

CLKB
RENB

CSB

MBB
SIZEB

EFB/ORB
AEB

BE

FWFT
FFC/IRC

AFC

Mail 2

Write

Pointer

36

Matching

Input Bus-

Input

Register

Read

Output

Register

Pointer

36

RAM ARRAY

16,384 x 36
32,768 x 36
65,536 x 36

Register

36

RT1

RTM

RT2

MBF2

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.

FIFO1 and
FIFO2
Retransmit
Logic

COMMERICAL TEMPERATURE RANGE



2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

1

FIFO2,
Mail2
Reset
Logic

18

Port-C

Control

Logic

MRS2

PRS2

C0-C17

CLKC
WENC
MBC
SIZEC

4676 drw01

NOVEMBER 2003

DSC-4676/4

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

TM

COMMERCIAL TEMPERATURE RANGE

DESCRIPTION

The IDT72V3686/72V3696/72V36106 are designed to run off a 3.3V supply
for exceptionally low-power consumption. These devices are a monolithic,
high-speed, low-power, CMOS Triple Bus synchronous (clocked) FIFO
memory which supports clock frequencies up to 100 MHz and has read access
times as fast as 6.5ns. Two independent 16,384/32,768/65,536 x 36 dual-port
SRAM FIFOs on board each chip buffer data between a bidirectional 36-bit bus

PIN CONFIGURATION

40

EFA/ORA

126

41

PRS1/RT1

125

42

CC

V

124

43

AFA

123

44

AEA

122

45

MBF2

MBA

121

120

46

47

FS0/SD

MRS1

118

119

48

49

INDEX

W/RA

ENA

CLKA

GND

A35
A34
A33
A32

Vcc

A31

A30

GND

A29
A28
A27
A26
A25

A24

A23

BE/FWFT

GND

A22

Vcc

A21

A20
A19

A18

GND

A17

A16

A15

A14

A13

Vcc

A12

GND

A11

A10

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

CSA

128

39

FFA/IRA

127

(Port A) and two unidirectional 18-bit buses (Port B transmits data, Port C
receives data.) FIFO data can be read out of Port B and written into Port C using
either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations.

These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or

CC

GND

CLKC

117

116

50

51

FS1/SEN

115

52

MRS2

114

53

MBB

113

54

V

MBF1

111

112

56

55

AEB

110

57

AFC

109

58

EFB/ORB

108

59

FFC/IRC

107

60

GND

106

61

CSB

105

62

WENC

RENB

103

104

102
101

100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

63

64

CLKB

PRS2/RT2
LOOP

C17
C16
C15
C14

RTM
MBC
C13
C12
C11
C10
C9
C8
V

CC

C7
C6
SIZEB
GND
C5
C4
C3
C2
C1
C0
GND
B17
B16
SIZEC

V

CC

B15
B14
B13
B12
GND
B11
B10

A9

A8

A7

A1

CC

FS2

A2

V

A0

A4

A6

GND

A3

A5

GND

B0

B1

B2

B3

B4

B5

B6

GND

CC

V

B7

B8

4676 drw02

B9

TQFP (PK128-1, order code: PF)

TOP VIEW

2

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

TM

COMMERCIAL TEMPERATURE RANGE

coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro­nous control.

Communication between each port may bypass the FIFOs via two mailbox
registers. The mailbox registers' width matches the selected bus width of ports
B and C. Each mailbox register has a flag (MBF1 and MBF2) to signal when
new mail has been stored.

Two kinds of reset are available on these FIFOs: Master Reset and Partial
Reset. Master Reset initializes the read and write pointers to the first location
of the memory array and selects serial flag programming, parallel flag program­ming, or one of five possible default flag offset settings, 8, 16, 64, 256 or 1,024.
Each FIFO has its own, independent Master Reset pin, MRS1 and MRS2.

Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programming method and partial flag default offsets) are retained. Partial Reset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2. Note that the Retransmit Mode, RTM pin must be LOW at the
point a partial reset is performed.

Both FIFO's have Retramsmit capability, when a Retransmit is performed on
a respective FIFO only the read pointer is reset to the first memory location. A
Retransmit is performed by using the Retransmit Mode, RTM pin in conjunction
with the Retransmit pins RT1 or RT2, for each respective FIFO. Note that the
two Retransmit pins RT1 and RT2 are muxed with the Partial Reset pins.

These devices have two modes of operation: In the IDT Standard mode, the
first word written to an empty FIFO is deposited into the memory array. A read
operation is required to access that word (along with all other words residing
in memory). In the First Word Fall Through mode (FWFT), the first word written
to an empty FIFO appears automatically on the outputs, no read operation
required (Nevertheless, accessing subsequent words does necessitate a
formal read request). The state of the BE/FWFT pin during Master Reset
determines the mode in use.

Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/
ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/IRC). The
EF and FF functions are selected in the IDT Standard mode. EF indicates
whether or not the FIFO memory is empty. FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.

Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a
programmable Almost-Full flag (AFA and AFC). AEA and AEB indicate when

a selected number of words remain in the FIFO memory. AFA and AFC indicate
when the FIFO contains more than a selected number of words.

FFA/IRA, FFC/IRC, AFA and AFC are two-stage synchronized to the Port
Clock that writes data into its array. EFA/ORA, EFB/ORB, AEA, and AEB are
two-stage synchronized to the Port Clock that reads data from its array.
Programmable offsets for AEA, AEB, AFA, AFC are loaded in parallel using
Port A or in serial via the SD input. Five default offset settings are also provided.
The AEA and AEB threshold can be set at 8, 16, 64, 256, and 1,024 locations
from the empty boundary and the AFA and AFC threshold can be set at 8, 16,
64, 256 or 1,024 locations from the full boundary. All these choices are made
using the FS0, FS1 and FS2 inputs during Master Reset.

Interspersed Parity can also be selected during a Master Reset of the FIFO.
If Interspersed Parity is selected then during parallel programming of the flag
offset values, the device will ignore data line A8. If Non-Interspersed Parity is
selected then data line A8 will become a valid bit.

A Loopback function is provided on Port A. When the Loop feature is selected
via the LOOP pin, the data output from FIFO2 will be directed to the data input
of FIFO1. If Loop is selected and Port A is set-up for write operation via W/RA
pin, then data output from FIFO2 will be written to FIFO1, but will not be placed
on the output Port A (A0-A35). If Port A is set-up for read operation via W/RA
then data output from FIFO2 will be written into FIFO1 and placed onto Port A
(A0-A35). The Loop will continue to happen provided that FIFO1 is not full and
FIFO2 is not empty. If during a Loop sequence FIFO1 becomes full then any
data that continues to be read out from FIFO2 will only be placed on the Port
A (A0-A35) lines, provided that Port A is set-up for read operation. If during a
Loop sequence the FIFO2 becomes empty, then the last word from FIFO2 will
continue to be clocked into FIFO1 until FIFO1 becomes full or until the Loop
function is stopped. The Loop feature can be useful when performing system
debugging and remote loopbacks.

Two or more FIFOs may be used in parallel to create wider data paths. Such
a width expansion requires no additional, external components. Furthermore,
two IDT72V3686/72V3696/72V36106 FIFOs can be combined with unidirec­tional FIFOs capable of First Word Fall Through timing (i.e. the SuperSync FIFO
family) to form a depth expansion.

If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (ICC) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.

The IDT72V3686/72V3696/72V36106 are characterized for operation from
0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by
special order. They are fabricated using IDT’s high speed, submicron CMOS
technology.

3

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

TM

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS

Symbol Name I/O Description

A0-A35 Port A Data I/O 36-bit bidirectional data port for side A.
AEA Port A Almost- O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2

Empty Flag is less than or equal to the value in the Almost-Empty A Offset register, X2.

AEB Port B Almost- O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1

Empty Flag is less than or equal to the value in the Almost-Empty B Offset register, X1.

AFA Port A Almost- O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations

Full Flag in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.

AFC Port C Almost- O Programmable Almost-Full flag synchronized to CLKC. It is LOW when the number of empty locations

Full Flag in FIFO2 is less than or equal to the value in the Almost-Full C Offset register, Y2.
B0-B17 Port B Data O 18-bit output data port for side B.
BE/FWFT Big-Endian/ I This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.

First Word Fall In this case, depending on the bus size, the most significant byte or word on Port A is read from

Through Select Port B first (A-to-B data flow) or is written to Port C first (C-to-A data flow). A LOW on BE will select

Little-Endian operation. In this case, the least significant byte or word on Port A is read from Port B first
(A-to-B data flow) or is written to Port C first (C-to-A data flow).

After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a
LOW selects First Word Fall Through mode. Once the timing mode has been selected, the level on

FWFT must be static throughout device operation.
C0-C17 Port C Data I 18-bit input data port for side C.
CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through Port A and can be

asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to

the LOW-to-HIGH transition of CLKA.
CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous

or coincident to CLKA. EFB/ORB and AEB are synchronized to the LOW-to-HIGH transition of CLKB.
CLKC Port C Clock I CLKC is a continuous clock that synchronizes all data transfers through Port C and can be asynchronous

or coincident to CLKA. FFC/IRC and AFC are synchronized to the LOW-to-HIGH transition of CLKC.
CSA Port A Chip I CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35

Select outputs are in the high-impedance state when CSA is HIGH.

CSB Port B Chip I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read data on Port B. The B0-B17

Select outputs are in the high-impedance state when CSB is HIGH.

EFA/ORA Port A Empty/ O This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates

Output Ready whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA
Flag indicates the presence of valid data on the A0-A35 outputs, available for reading. EFA/ORA is

synchronized to the LOW-to-HIGH transition of CLKA.
EFB/ORB Port B Empty/ O This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates

Output Ready Flag whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB

indicates the presence of valid data on the B0-B17 outputs, available for reading. EFB/ORB is synchronized

to the LOW-to-HIGH transition of CLKB.
ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
FFA/IRA Port A Full/ O This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates

Input Ready Flag whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA

indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is

synchronized to the LOW-to-HIGH transition of CLKA.
FFC/IRC Port C Full/ O This is a dual function pin. In the IDT Standard mode, the FFC function is selected. FFC indicates

Input Ready Flag whether or not the FIFO2 memory is full. In the FWFT mode, the IRC function is selected. IRC

indicates whether or not there is space available for writing to the FIFO2 memory. FFC/IRC is

synchronized to the LOW-to-HIGH transition of CLKC.

4

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

TM

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS (CONTINUED)

Symbol Name I/O Description

FS0/SD Flag Offset Select 0/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset,

Serial Data FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method. Three Offset register

programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or 1,024),

FS1/SEN Flag Offset Select 1/ I parallel load from Port A, and serial load.

Serial Enable

(1)

FS2

Flag Offset Select 2 I the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on

LOOP Loopback Select I This pin selects the loopback feature for Port A. During Loopback data from FIFO2 will be directed to the input of

MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35

Select outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects

MBB Port B Mailbox I A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are

Select active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output

MBC Port C Mailbox I A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during

Select Master Reset.

MBF1 Mail1 Register O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1

Flag register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a

MBF2 Mail2 Register O MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2

Flag register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a

MRS1 Master Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B

MRS2 Master Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A

PRS1/ Partial Reset/ I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
RT1 Retransmit FIFO1 is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read and write

PRS2/ Partial Reset/ I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
RT2 Retransmit FIFO2 is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read and write

RENB Port B Read Enable I RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B.
RTM Retransmit Mode I This pin is used in conjunction with the RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed on FIFO1

When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to
FS0/SD into the X and Y registers. The number of bit writes required to program the Offset registers is 56 for the

72V3686, 60 for the 72V3696, and 64 for the 72V36106. The first bit write stores the Y-register (Y1) MSB and
the last bit write stores the X-register (X2) LSB.

FIFO1. to initiate a Loop the LOOP pin must be held LOW and the ENA pin must be HIGH.

FIFO2 output-register data for output.

register data for output.

Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.

Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.

output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial or
parallel) and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and
C for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while MRS1 is LOW.

output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1, selects
the programming method (serial or parallel) and one of the five flag default offsets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKC must occur while MRS2 is LOW.

pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently
selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read pointer only to
the first memory location.

selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer only to
the first memory location.

or FIFO2 respectively.

5

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

TM

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS (CONTINUED)

Symbol Name I/O Description

(1)

SIZEB

SIZEC

WENC Port C Write Enable I WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on Port C.
W/RA Port A Write/ I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of

NOTE:

1. FS2, SIZEB and SIZEC inputs are not TTL compatible. These inputs should be tied to GND or V

Port B I SIZEB determines the bus width of Port B. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
Bus Size Select selects word (18-bit) bus size. SIZEB works with SIZEC and BE to select the bus size and endian arrangement

for ports B and C. The level of SIZEB must be static throughout device operation.

(1)

Port C I SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
Bus Size Select selects word (18-bit) bus size. SIZEC works with SIZEB and BE to select the bus size and endian arrangement

for ports B and C. The level of SIZEC must be static throughout device operation.

Read Select CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.

CC.

6

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

TM

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)

Symbol Rating Commercial Unit

V

CC Supply Voltage Range –0.5 to +4.6 V

(2)

I

V

(2)

O

V
I

IK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA

OK Output Clamp Current (VO = < 0 or VO > VCC) ±50 mA

I

OUT Continuous Output Current (VO = 0 to VCC) ±50 mA

I
I

CC Continuous Current Through VCC or GND ±400 mA

STG Storage Temperature Range –65 to 150 °C

T

NOTES:

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

Input Voltage Range –0.5 to VCC+0.5 V
Output Voltage Range –0.5 to VCC+0.5 V

(1)

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 3.15 3.3 3.45 V

V

IH High-Level Input Voltage 2 — VCC+0.5 V

V

IL Low-Level Input Voltage — — 0.8 V

V

OH High-Level Output Current — — – 4 mA

I

OL Low-Level Output Current — — 8 mA

I

A Operating Temperature 0 — 70 °C

T

NOTE:

1. Vcc = 3.3V ± 0.15V, JEDEC JESD8-A compliant

ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)

IDT72V3686
IDT72V3696

IDT72V36106

Commercial

tCLK = 10, 15 ns

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VOH Output Logic "1" Voltage VCC = 3.0V, IOH = –4 mA 2.4 — — V
V

OL Output Logic "0" Voltage VCC = 3.0V, IOL = 8 mA — — 0.5 V

I

LI Input Leakage Current (Any Input) VCC = 3.6V, VI = VCC or 0 — — ±5 µA

I

LO Output Leakage Current VCC = 3.6V, VO = VCC or 0 — — ±5 µA

(3)

I

CC2

I

CC3

C

IN

C

OUT

NOTES:

1. All typical values are at V

2. Vcc = 3.3V ± 0.15V, T

3. For additional I

4. Characterized values, not currently tested.

Standby Current (with CLKA, CLKB and CLKC running) VCC = 3.6V, VI = VCC - 0.2V or 0 — — 5 mA

(3)

Standby Current (no clocks running) VCC = 3.6V, VI = VCC - 0.2V or 0 — — 5 mA

(4)

Input Capacitance VI = 0, f = 1 MHz — 4 — pF

(4)

Output Capacitance VO = 0, f = 1 MHZ — 8 — pF

CC = 3.3V, TA = 25°C.

A = 0° to +70°; JEDEC JESD8-A compliant.

CC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).

(2)

7

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

TM

COMMERCIAL TEMPERATURE RANGE

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION

The I

CC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3686/72V3696/72V36106 with CLKA,

CLKB and CLKC set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs
driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.

CALCULATING POWER DISSIPATION

CC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:

With I

P

T = VCC x ICC(f) + Σ(CL x VCC

2

x fo)

N

where:
N = number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size)

L = output capacitance load

C
f

o = switching frequency of an output

100

90

80

70

60

50

mA

40

30

Supply Current

CC(f)

I

20

f

data

= 1/2 f

TA = 25°C

L

= 0 pF

C

V

CC =

3.6V

CC =

3.0V

V

V

CC =

S

3.3V

10

0

010203040506070

f

S



Clock Frequency

Figure 1. Typical Characteristics: Supply Current (I



MHz

CC) vs. Clock Frequency (fS)

8

80

90

100

4676 drw03

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

TM

COMMERCIAL TEMPERATURE RANGE

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant)

IDT72V3686L10 IDT72V3686L15
IDT72V3696L10 IDT72V3696L15

IDT72V36106L10 IDT72V36106L15

Symbol Parameter Min. Max. Min. Max. Unit

S Clock Frequency, CLKA, CLKB, or CLKC — 100 — 66.7 MHz

f

CLK Clock Cycle Time, CLKA, CLKB, or CLKC 10 — 15 — ns

t
t

CLKH Pulse Duration, CLKA, CLKB, or CLKC HIGH 4.5 — 6 — ns
CLKL Pulse Duration, CLKA, CLKB, OR CLKC LOW 4.5 — 6 — ns

t

DS Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑ 3—4—ns

t
t

ENS1 Setup Time, CSA and W/RA before CLKA↑; CSB 4 — 4.5 — ns

before CLKB↑

ENS2 Setup Time, ENA, and MBA before CLKA↑; RENB 3 — 4.5 — ns

t

and MBB before CLKB↑; WENC and MBC before CLKC↑

RSTS Setup Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 5—5—ns

t

LOW before CLKA↑ or CLKB↑

tFSS Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH 7.5 — 8.5 — ns

BES Setup Time, BE/FWFT before MRS1 and MRS2 HIGH 7.5 — 7.5 — ns

t

SDS Setup Time, FS0/SD before CLKA↑ 3—4—ns

t
t

SENS Setup Time, FS1/SEN before CLKA↑ 3—4—ns
FWS Setup Time, BE/FWFT before CLKA↑ 0—0—ns

t

RTMS Setup Time, RTM before RT1; RTM before RT2 5—5—ns

t
t

DH Hold Time, A0-A35 after CLKA↑ and C0-C17 after CLKC↑ 0.5 — 1 — ns
ENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, 0.5 — 1 — ns

t

RENB, and MBB after CLKB↑; WENC and MBC after CLKC↑

RSTH Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 4—4—ns

t

LOW after CLKA↑ or CLKB↑

tFSH Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH 2 — 2 — ns

BEH Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 2 — 2 — n s

t

SDH Hold Time, FS0/SD after CLKA↑ 0.5 — 1 — ns

t
t

SENH Hold Time, FS1/SEN HIGH after CLKA↑ 0.5 — 1 — ns
SPH Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH 2 — 2 — ns

t

RTMH Hold Time, RTM after RT1; RTM after RT2 5—5—ns

t

(2)

t

SKEW1

Skew Time, between CLKA↑ and CLKB↑ for EFB/ORB and 5 — 7.5 — ns

FFA/IRA; between CLKA↑ and CLKC↑ for EFA/ORA and
FFC/IRC

(2,3)

SKEW2

t

Skew Time, between CLKA↑ and CLKB↑ for AEB and AFA;12—12—ns
between CLKA↑ and CLKC↑ for AEA and AFC

NOTES:

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.

3. Design simulated, not tested.

(1)

(1)

9

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

TM

COMMERCIAL TEMPERATURE RANGE

SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF

(Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant)

IDT72V3686L10 IDT72V3686L15
IDT72V3696L10 IDT72V3696L15

IDT72V36106L10 IDT72V36106L15

Symbol Parameter Min. Max. Min. Max. Unit

tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B17 2 6.5 2 10 ns
t

WFF Propagation Delay Time, CLKA↑ to FFA/IRA and CLKC↑ to 2 6.5 2 8 ns

FFC/IRC

REF Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to 1 6.5 1 8 ns

t

EFB/ORB

PAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 1 6.5 1 8 ns

t
t

PAF Propagation Delay Time, CLKA↑ to AFA and CLKC↑ to AFC 1 6.5 1 8 ns
PMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 0 6.5 0 8 ns

t

HIGH, CLKB↑ to MBF1 HIGH, and CLKC↑ to MBF2 LOW

PMR Propagation Delay Time, CLKA↑ to B0-B17

t

to A0-A35

(2)

tMDV Propagation Delay Time, MBA to A0-A35 valid and MBB to 2 8 2 10 ns

B0-B17 valid

RSF Propagation Delay Time, MRS1 or PRS1 LOW to AEB 110115ns

t

LOW, AFA HIGH, and MBF1 HIGH and MRS2 or PRS2
LOW to AEA LOW, AFC HIGH, and MBF2 HIGH

EN Enable Time, CSA or W/RA LOW to A0-A35 Active and 2 6 2 1 0 n s

t

CSB LOW to B0-B17 Active

t

DIS Disable Time, CSA or W/RA HIGH to A0-A35 at high 1 6 1 8 ns

impedance and CSB HIGH to B0-B17 at HIGH impedance

NOTES:

1. Writing data to the mail1 register when the B0-B17 outputs are active and MBB is HIGH.

2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.

3.

Vcc = 3.3V ± 0.15V; TA = 0° to +70°.

(1)

and CLKC↑ 2 6.5 2 10 ns

10

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

TM

COMMERCIAL TEMPERATURE RANGE

SIGNAL DESCRIPTION

MASTER RESET (MRS1, MRS2)

After power up, a Master Reset operation must be performed by providing

a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memory of the IDT72V3686/72V3696/72V36106 undergoes a complete reset
by taking its associated Master Reset (MRS1) input LOW for at least four Port
A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The
FIFO2 memory undergoes a complete reset by taking its associated Master
Reset (MRS2) input LOW for at least four Port A Clock (CLKA) and four Port
C Clock (CLKC) LOW-to-HIGH transitions. The Master Reset inputs can switch
asynchronously to the clocks. A Master Reset initializes the associated read and
write pointers to the first location of the memory and forces the Full/Input Ready
flag (FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/
ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW and the Almost-Full flag
(AFA, AFC) HIGH. A Master Reset also forces the associated Mailbox Flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the
FIFO's Full/Input Ready flag is set HIGH after two Write Clock cycles. Then the
FIFO is ready to be written to.

A LOW-to-HIGH transition on the FIFO1 Master Reset (MRS1) input latches

the value of the Big-Endian (BE) input for determining the order by which bytes
are transferred through Ports B and C. It also latches the values of the Flag Select
(FS0, FS1 and FS2) inputs for choosing the Almost-Full and Almost-Empty
offsets and programming method.

A LOW-to-HIGH transition on the FIFO2 Master Reset (MRS2) clears the flag

offset registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the FIFO2
Master Reset (MRS2) together with the FIFO1 Master Reset input (MRS1)
latches the value of the Big-Endian (BE) input for Ports B and C and also latches
the values of the Flag Select (FS0, FS1 and FS2) inputs for choosing the Almost­Full and Almost-Empty offsets and programming method (for details see Table
1, Flag Programming, and Almost-Empty and Almost-Full flag offset program-
ming section). The relevant Master Reset timing diagrams can be found in
Figure 4 and 5.

Note that MBC must be HIGH during Master Reset (until FFA/IRA and FFC/

IRC go HIGH). MBA and MBB are "don't care" inputs1 during Master Reset.

PARTIAL RESET (PRS1, PRS2)

The FIFO1 memory of these devices undergoes a limited reset by taking its

associated Partial Reset (PRS1) input LOW for at least four Port A Clock (CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2 memory
undergoes a limited reset by taking its associated Partial Reset (PRS2) input
LOW for at least four Port A Clock (CLKA) and four Port C Clock (CLKC) LOW­to-HIGH transitions. The RTM pin must be LOW during the time of partial reset.
The Partial Reset inputs can switch asynchronously to the clocks. A Partial Reset
initializes the internal read and write pointers and forces the Full/Input Ready
flag (FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/
ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the Almost-Full flag
(AFA, AFC) HIGH. A Partial Reset also forces the Mailbox Flag (MBF1, MBF2)
of the parallel mailbox register HIGH. After a Partial Reset, the FIFO’s Full/Input
Ready flag is set HIGH after two Write Clock cycles.

Whatever flag offsets, programming method (parallel or serial), and timing

mode (FWFT or IDT Standard mode) are currently selected at the time a Partial
Reset is initiated, those settings will remain unchanged upon completion of the
reset operation. A Partial Reset may be useful in the case where reprogramming
a FIFO following a Master Reset would be inconvenient. See Figure 6 and 7
for Partial Reset timing diagrams.

RETRANSMIT (RT1, RT2)

The FIFO1 memory of these devices undergoes a Retransmit by taking its
associated Retransmit (RT1) input LOW for at least four Port A Clock (CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit
initializes the read pointer of FIFO1 to the first memory location.

The FIFO2 memory undergoes a Retransmit by taking its associated
Retransmit (RT2) input LOW for at least four Port A Clock (CLKA) and four Port
C Clock (CLKC) LOW-to-HIGH transitions. The Retransmit initializes the read
pointer of FIFO1 to the first memory location.

The RTM pin must be HIGH during the time of Retransmit. Note that the
RT1input is muxed with the PRS1 input, the state of the RTM pin determining
whether this pin performs a Retransmit or Partial Reset. Also, the RT2 input is
muxed with the PRS2 input, the state of the RTM pin determining whether this
pin performs a Retransmit or Partial Reset. See Figures 30, 31, 32 and 33 for
Retransmit timing diagrams.

BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)

— ENDIAN SELECTION

This is a dual purpose pin. At the time of Master Reset, the BE select function
is active, permitting a choice of Big- or Little-Endian byte arrangement for data
written to Port C or read from Port B. This selection determines the order by which
bytes (or words) of data are transferred through those ports. For the following
illustrations, note that both ports B and C are configured to have a byte (or a
word) bus size.

A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs
go from LOW to HIGH will select a Big-Endian arrangement. When data is
moving in the direction from Port A to Port B, the most significant byte (word) of
the long word written to Port A will be read from Port B first; the least significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the most significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the least
significant byte (word) of the long word.

A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs
go from LOW to HIGH will select a Little-Endian arrangement. When data is
moving in the direction from Port A to Port B, the least significant byte (word) of
the long word written to Port A will be read from Port B first; the most significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the least significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figure 2 and 3 for illustrations
of the BE function. See Figure 4 (FIFO1 Master Reset) and 5 (FIFO2 Master
Reset) for Endian Select timing diagrams.

— TIMING MODE SELECTION

After Master Reset, the FWFT select function is available, permitting a choice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Master Reset (MRS1, MRS2) input is HIGH,
a HIGH on the BE/FWFT input during the next LOW-to-HIGH transition of CLKA
(for FIFO1) and CLKC (for FIFO2) will select IDT Standard mode. This mode
uses the Empty Flag function (EFA, EFB) to indicate whether or not there are
any words present in the FIFO memory. It uses the Full Flag function (FFA,
FFC) to indicate whether or not the FIFO memory has any free space for writing.

NOTE:

1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.

11

IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36

TM

COMMERCIAL TEMPERATURE RANGE

In IDT Standard mode, every word read from the FIFO, including the first, must
be requested using a formal read operation.

Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/
FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and
CLKC (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B17). It also uses the Input Ready function (IRA, IRC)
to indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to the data
outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation.

Following Master Reset, the level applied to the BE/FWFT input to choose
the desired timing mode must remain static throughout FIFO operation. Refer
to Figure 4 (FIFO1 Master Reset) and Figure 5 (FIFO2 Master Reset) for First
Word Fall Through select timing diagrams.

PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS

Four registers in these FIFOs are used to hold the offset values for the Almost­Empty and Almost-Full flags. The Port B Almost-Empty flag (AEB) Offset register
is labeled X1 and the Port A Almost-Empty flag (AEA) Offset register is labeled
X2. The Port A Almost-Full flag (AFA) Offset register is labeled Y1 and the Port
C Almost-Full flag (AFC) Offset register is labeled Y2. The index of each register
name corresponds to its FIFO number. The Offset registers can be loaded with
preset values during the reset of a FIFO, programmed in parallel using the
FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD)
input (see Table 1).

FS0/SD, FS1/SEN and FS2 function the same way in both IDT Standard and
FWFT modes.

— PRESET VALUES

To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers with
one of the five preset values listed in Table 1, the flag select inputs must be HIGH
or LOW during a master reset. For example, to load the preset value of 64 into
X1 and Y1, FS0, FS1 and FS2 must be HIGH when FlFO1 reset (MRS1)

returns HIGH. Flag Offset registers associated with FIFO2 are loaded with one
of the preset values in the same way with FIFO2 Master Reset (MRS2) toggled
simultaneously with FIFO1 Master Reset (MRS1). For relevant Preset value
loading timing diagrams, see Figure 4 and 5.

— PARALLEL LOAD FROM PORT A

To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously with FS2 HIGH or LOW, FS0 and FS1
LOW during the LOW-to-HIGH transition of MRS1 and MRS2. The state of FS2
at this point of reset will determine whether the parallel programming method has
Interspersed Parity or Non-Interspersed Parity. Refer to Table 1 for Flag
Programming Flag Offset setup . It is important to note that once parallel
programming has been selected during a Master Reset by holding both FS0
& FS1 LOW, these inputs must remain LOW during all subsequent FIFO
operation. They can only be toggled HIGH when future Master Resets are
performed and other programming methods are desired.

After this reset is complete, the first four writes to FIFO1 do not store data in
RAM but load the Offset registers in the order Y1, X1, Y2, X2. For Non­Interspersed Parity mode the Port A data inputs used by the Offset registers are
(A13-A0), (A14-A0), or (A15-A0) for the IDT72V3686, IDT72V3696, or
IDT72V36106, respectively. For Interspersed Parity mode the Port A data
inputs used by the Offset registers are (A14-A9, A7-A0), (A15-A9, A7-A0), or
(A16-A9, A7-A0) for the IDT72V3686, IDT72V3696, or IDT72V36106,
respectively. The highest numbered input is used as the most significant bit of
the binary number in each case. Valid programming values for the registers
range from 1 to 16,380 for the IDT72V3686; 1 to 32,764 for the IDT72V3696;
and 1 to 65,532 for the IDT72V36106. After all the Offset registers are
programmed from Port A, the Port C Full/Input Ready flag (FFC/IRC) is set
HIGH, and both FIFOs begin normal operation. Refer to Figure 8 for a timing
diagram illustration for parallel programming of the flag offset values.

INTERSPERSED PARITY

Interspersed Parity is selected during a Master Reset of the FIFO. Refer to
Table 1 for the set-up configuration of Interspersed Parity. The Interspersed

TABLE 1

FS2 FS1/SEN FS0/SD MRS1 MRS2 X1 AND Y1 REGlSTERS

HH H↑ X64 X
HH HX↑ X64
HH L↑ X16 X
HH LX↑ X16
HL H↑ X8 X
HL HX↑ X8

LH H↑ X 256 X
LH HX↑ X 256
LL H↑ X 1,024 X
LL HX↑ X 1,024
LH L↑↑ Serial programming via SD Serial programming via SD

HL L↑↑ Parallel programming via Port A

LL L↑↑ IP Mode

NOTES:

1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.

2. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.

3. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.

4. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.

5. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.



 FLAG PROGRAMMING



12

(4, 5)

(3, 5)

(1)

X2 AND Y2 REGlSTERS

Parallel programming via Port A

IP Mode

(2)

(3, 5)

(4, 5)