IDT IDT72V223, IDT72V233, IDT72V243, IDT72V253, IDT72V263 User Manual

3.3 VOLT HIGH-DENSITY SUPERSYNC II™
NARROW BUS FIFO

512 x 18/1,024 x 9, 1,024 x 18/2,048 x 9
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9
8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9
32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9

FEATURES:

• Choose among the following memory organizations:

IDT72V223
IDT72V233
IDT72V243
IDT72V253
IDT72V263
IDT72V273
IDT72V283
IDT72V293

••

• Functionally compatible with the IDT72V255LA/72V265LA and

••

IDT72V275/72V285 SuperSync FIFOs

••

•

Up to 166 MHz Operation of the Clocks

••

••

•

User selectable Asynchronous read and/or write ports (BGA Only)

••

••

•

User selectable input and output port bus-sizing

••

- x9 in to x9 out

- x9 in to x18 out

- x18 in to x9 out

- x18 in to x18 out

••

• Pin to Pin compatible to the higher density of IDT72V2103/72V2113

••

••

• Big-Endian/Little-Endian user selectable byte representation

••

••

• 5V tolerant inputs

••



 512 x 18/1,024 x 9




 1,024 x 18/2,048 x 9




 2,048 x 18/4,096 x 9




 4,096 x 18/8,192 x 9




 8,192 x 18/16,384 x 9




 16,384 x 18/32,768 x 9




 32,768 x 18/65,536 x 9




 65,536 x 18/131,072 x 9



IDT72V223, IDT72V233
IDT72V243, IDT72V253
IDT72V263, IDT72V273
IDT72V283, IDT72V293

••

• Fixed, low first word latency

••

••

Zero latency retransmit

•

••

••

• Auto power down minimizes standby power consumption

••

••

• Master Reset clears entire FIFO

••

••

•

Partial Reset clears data, but retains programmable settings

••

••

•

Empty, Full and Half-Full flags signal FIFO status

••

••

•

Programmable Almost-Empty and Almost-Full flags, each flag can

••

default to one of eight preselected offsets

••

Selectable synchronous/asynchronous timing modes for Almost-

•

••

Empty and Almost-Full flags

••

• Program programmable flags by either serial or parallel means

••

••

• Select IDT Standard timing (using EF and FF flags) or First Word

••

Fall Through timing (using OR and IR flags)

••

• Output enable puts data outputs into high impedance state

••

••

• Easily expandable in depth and width

••

••

• JTAG port, provided for Boundary Scan function (BGA Only)

••

••

• Independent Read and Write Clocks (permit reading and writing

••

simultaneously)

••

• Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball

••

Grid Array (BGA) (with additional features)

••

• High-performance submicron CMOS technology

••

••

• Industrial temperature range (–40

••

°°

°C to +85

°°

°°

°C) is available

°°

FUNCTIONAL BLOCK DIAGRAM

*Available on the
BGA package only.

ASYW

*

BE

IP

IW

OW

MRS

PRS

TCK

*

TRST

*

TMS

*

TDI

*

TDO

*

IDT and the IDT logo are a registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

WEN

WCLK/WR

WRITE CONTROL

LOGIC

WRITE POINTER

CONTROL

LOGIC

BUS

CONFIGURATION

RESET

LOGIC

JTAG CONTROL

(BOUNDARY SCAN)

*

*

0

-D

n

(x9 or x18)

D

INPUT REGISTER

RAM ARRAY

512 x 18 or 1,024 x 9
1,024 x 18 or 2,048 x 9
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9

8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9

65,536 x 18 or 131,072 x 9

OUTPUT REGISTER

Q

0

OE

-Qn (x9 or x18)

1

OFFSET REGISTER

READ POINTER

LD

FLAG

LOGIC

READ

CONTROL

LOGIC

SEN

FF/IR
PAF
EF/OR
PAE
HF

FWFT/SI
PFM
FSEL0
FSEL1

RT

RM

ASYR

*

RCLK/RD

REN

*

4666 drw01

SEPTEMBER 2003

DSC-4666/12

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION:

The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO)
memories with clocked read and write controls and a flexible Bus-Matching x9/
x18 data flow. These FIFOs offer numerous improvements over previous
SuperSync FIFOs, including the following:

• Flexible x9/x18 Bus-Matching on both read and write ports

• The limitation of the frequency of one clock input with respect to the other

has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs,
RCLK or WCLK, is running at the higher frequency.

PIN CONFIGURATIONS

WCLK

PRS

INDEX

MRSLDFWFT/SI

FF/IR

PAFOWFSEL0HFFSEL1BEIP

• The period required by the retransmit operation is now fixed and short.

• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)

• Asynchronous/Synchronous translation on the read or write ports

• High density offerings up to 1 Mbit
Bus-Matching SuperSync FIFOs are particularly appropriate for network,

video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.

CC

V

PAE

PFM

EF/ORRMRCLK

REN

WEN

SEN

DNC

V

DNC

GND

D17
V

D16
D15
D14
D13

GND

D12
D11
D10

V

CC

IW

CC

D9
D8

CC

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

80

79

1
2

(1)

3
4

(1)

5
6
7

8
9
10
11

12
13
14
15
16
17
18
19
20

22232425262728293031323334353637383940

21

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

RT

OE

V

CC

Q17
Q16
GND

GND
Q15

Q14

CC

V

Q13
Q12

GND
Q11
GND
Q10

V

CC

Q9
Q8
Q7

NOTE:

1. DNC = Do Not Connect.

D7

D6

D5D4D3D2D1

GND

D0

Q0

Q1

Q2

GND

GND

Q3

TQFP (PN80-1, order code: PF)

TOP VIEW

2

CC

V

Q4

Q5

GND

4666 drw02

Q6

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II

IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9

512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION (CONTINUED)

Each FIFO has a data input port (D
which can assume either an 18-bit or a 9-bit width as determined by the state
of external control pins Input Width (IW) and Output Width (OW) during the Master
Reset cycle.

The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).

The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.

n) and a data output port (Qn), both of

PIN CONFIGURATIONS (CONTINUED)

A1 BALL PAD CORNER

During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, and the OE input used
to provide three-state control of the outputs, Qn.

The frequencies of both the RCLK and the WCLK signals may vary from 0

MAX with complete independence. There are no restrictions on the frequency

to f
of the one clock input with respect to the other.

There are two possible timing modes of operation with these devices: IDT

Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does

A

WCLK

PRS LD

PAF

FSEL0

BE ASYR

PFM RM

B

WEN

MRS

HF

FSEL1

IP

PAE

C

ASYW

SEN

FF/IR

V

CC

V

CC

CC

V

V

CC

V

CC

D

D17 IW V

CC

GND GND GND GND V

CC

E

D16

D15

CC

V

GND Q15

GND GND GND V

CC

F

D13

D14 V

CC

GND

GND GND GND V

CC

G

D11 D12 V

CC

GND Q10

GND GND GND V

CC

H

D8 D9 D10 V

CC

CC

V

CC

V

CC

Q1

V

J

D6 D7 D2 D0 Q7

TMS

TCK

TDO Q2 Q4

K

D5 D4 D3 D1

TRST

TDI Q0 Q3 Q5

EF/OR RCLKFWFT/SI OW

RT OE

Q16 Q17

Q14

Q13

Q11

Q9

REN

Q12

Q8

Q6

12 3 4 5 6 7 8 9 10

4666 drw02b

BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC)

TOP VIEW

3

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION (CONTINUED)

not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.

For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and
FF functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that PAE can be set to switch at a predefined number of locations
from the empty boundary and the PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and LD pins.

For serial programming, SEN together with LD on each rising edge of WCLK,
are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via D

n. REN together with LD on each rising edge

of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.

During Master Reset (MRS) the following events occur: the read and
write pointers are set to the first location of the FIFO. The FWFT pin selects
IDT Standard mode or FWFT mode.

The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing
before Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect. PRS is useful for resetting a device in mid­operation, when reprogramming programmable flags would be undesirable.

It is also possible to select the timing mode of the PAE (Programmable Almost­Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.

If asynchronous PAE/PAF configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-

PARTIAL RESET (PRS)

WRITE CLOCK (WCLK/WR*)

WRITE ENABLE (WEN)

LOAD (LD)

SERIAL CLOCK (SCLK)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE ALMOST-FULL (PAF)

INPUT WIDTH (IW)

MASTER RESET (MRS)

IDT
72V223
72V233
72V243
72V253
72V263
72V273
72V283
72V293

BUS-

MATCHING

(BM)

(x9 or x18) DATA OUT (Q0 - Qn)(x9 or x18) DATA IN (D0 - Dn)

OUTPUT WIDTH (OW)

READ CLOCK (RCLK/RD*)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)

INTERSPERSED/
NON-INTERSPERSED PARITY (IP)

4666 drw03

Figure 1. Single Device Configuration Signal Flow Diagram

4

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II

IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9

512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW­to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.

If synchronous PAE/PAF configuration is selected , the PAE is asserted
and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF
is asserted and updated on the rising edge of WCLK only and not RCLK. The
mode desired is configured during master reset by the state of the Programmable
Flag Mode (PFM) pin.

The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the RT input during a rising RCLK edge initiates a
retransmit operation by setting the read pointer to the first location of the memory
array. A zero-latency retransmit timing mode can be selected using the
Retransmit timing Mode pin (RM). During Master Reset, a LOW on RM will select
zero-latency retransmit. A HIGH on RM during Master Reset will select normal
latency.

If zero-latency retransmit operation is selected the first data word to be
retransmitted will be placed on the output register with respect to the same
RCLK edge that initiated the retransmit based on RT being LOW.

Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer
to Figure 13 and 14 for Retransmit Timing with zero-latency.

A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x18) and read
out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read

out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (BE) pin.

The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit position D

8 during the parallel

programming of the flag offsets. If Non-Interspersed Parity mode is selected, then
D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected
during Master Reset by the state of the IP input pin. This mode is relevant only
when the input width is set to x18 mode. Interspersed Parity control only has
an effect during parallel programming of the offset registers. It does not effect the
data written to and read from the FIFO.

A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
Boundary Scan Architecture.

If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.

The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293 are fabricated using IDT’s high speed submicron CMOS technology.

TABLE 1 — BUS-MATCHING CONFIGURATION MODES

IW OW Write Port Width Read Port Width

L L x18 x18
L H x18 x9
H L x9 x18
H H x9 x9

5

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (TQFP & BGA PACKAGES)

Symbol Name I/O Description

(1)

BE

0–D17 Data Inputs I Data inputs for a 18- or 9-bit bus. When in 18-bit mode, D 0–D17 are used. When in 9-bit mode, D0–D8 are used

D

EF/OR Empty Flag/ O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty. In

FF/IR Full Flag/ O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the

FSEL0

FSEL1

FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions

HF Half-Full Flag O HF indicates whether the FIFO memory is more or less than half-full.

(1)

IP

IW

LD Load I This is a dual purpose pin. During Master Reset, the state of the LD input, along with FSEL0 and FSEL1, determines

MRS Master Reset I MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the

OE Output Enable I OE controls the output impedance of Qn.

OW

PAE Programmable O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset

PAF Programmable O PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the

PFM

PRS Partial Reset I PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,

0–Q17 Data Outputs O Data outputs for a 18- or 9-bit bus. When in 18-bit mode, Q0–Q17 are used and when in 9-bit mode, Q0–Q8 are

Q

REN Read Enable I REN enables RCLK for reading data from the FIFO memory and offset registers.
RCLK/ Read Clock/ I If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK

RD Read Strobe reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded

*Big-Endian/ I During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will
Little-Endian select Little-Endian format.

and the unused inputs, D9–D17, should be tied LOW.

Output Ready FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs.

Input Ready FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO

memory.

(1)

Flag Select Bit 0 I During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the

programmable flags PAE and PAF. There are up to eight possible settings available.

(1)

Flag Select Bit 1 I During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the

programmable flags PAE and PAF. There are up to eight possible settings available.

Through/Serial In as a serial input for loading offset registers.

Interspersed Parity I During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed

Parity mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It
does not effect the data written to and read from the FIFO.

(1)

Input Width I This pin selects the bus width of the write port. During Master Reset, when IW is LOW, the write port will be

configured with a x18 bus width. If IW is HIGH, the write port will be a x9 bus width.

one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can
be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the
offset registers.

FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmable
flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency
timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.

(1)

Output Width I This pin selects the bus width of the read port. During Master Reset, when OW is LOW, the read port willbe con fig-

ured with a x18 bus width. If OW is HIGH, the read port will be a x9 bus width.

Almost-Empty Flag register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.

Almost-Full Flag Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.

(1)

Programmable I During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
Flag Mode will select Synchronous Programmable flag timing mode.

the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are
all retained.

used, and the unused outputs, Q

9-Q17 should not be connected. Outputs are not 5V tolerant regardless of the

state of OE.

into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
Asynchronous operation of the RCLK/RD input is only available in the BGA package.

NOTE:

1. Inputs should not change state after Master Reset.

6

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II

IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9

512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES)

Symbol Name I/O Description

(1)

RM

RT Retransmit I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH

SEN Serial Enable I SEN enables serial loading of programmable flag offsets.

WCLK/ Write Clock/ I If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
W R Write Strobe writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the

WEN Write Enable I WEN enables WCLK for writing data into the FIFO memory and offset registers.
V

CC +3.3V Supply I These are VCC supply inputs and must be connected to the 3.3V supply rail.

NOTE:

1. Inputs should not change state after Master Reset.

Retransmit Timing I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
Mode normal latency mode.

in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable
flag settings. RT is useful to reread data from the first physical location of the FIFO.

FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state). Asynchronous operation
of the WCLK/WR input is only available in the BGA package.

PIN DESCRIPTION (BGA PACKAGE ONLY)

Symbol Name I/O Description

(1)

ASYR

ASYW

TCK

(2)

TDI

TDO

TMS

TRST

NOTES:

1. Inputs should not change state after Master Reset.

2. These pins are for the JTAG port. Please refer to pages 41-44 and Figures 31-33.

Asynchronous I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.

(1)

Asynchronous I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
Write Port will select Asynchronous operation.

(2)

JTAG Clock I Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the

device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change
on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.

JTAG Test Data I One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Input serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register.

An internal pull-up resistor forces TDI HIGH if left unconnected.

(2)

JTAG Test Data O One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data
Output serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass

Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.

(2)

JTAG Mode Select I TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through

its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.

(2)

JTAG Reset I TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically reset

upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP
controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used
but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the
JTAG function is not used then this signal needs to be tied to GND.

7

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Com'l & Ind'l Unit

(2)

V

TERM

STG Storage Temperature –55 to +125 °C

T

I

OUT DC Output Current –50 to +50 mA

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

CC terminal only.

2. V

Terminal Voltage –0.5 to +4.5 V
with respect to GND

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

(1)

V

CC

Supply Voltage (Com'l & Ind'l) 3.15 3.3 3.45 V

GND Supply Voltage (Com'l & Ind'l) 0 0 0 V

(2)

IH

Input High Voltage (Com'l & Ind'l) 2.0 — 5.5 V

V

(3)

IL

Input Low Voltage (Com'l & Ind'l) — — 0.8 V

V

A Operating Temperature Commercial 0 — +70 °C

T

A Operating Temperature Industrial -4 0 — +85 °C

T

NOTES:

CC=3.3V ± 0.15V, JEDEC JESD8-A compliant.

1. V

2. Outputs are not 5V tolerant.

3. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)

IDT72V223L
IDT72V233L
IDT72V243L
IDT72V253L
IDT72V263L
IDT72V273L
IDT72V283L
IDT72V293L

Commercial and Industrial

tCLK = 6, 7.5, 10, 15 ns

Symbol Parameter Min. Max. Unit

(2)

ILI
ILO

(3)

Input Leakage Current –1 1 µA

Output Leakage Current –1 0 10 µA
VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — V
VOL Output Logic “0” Voltage, IOL = 8 mA — 0.4 V

(4,5,6)

ICC1

(4,5,6)

ICC1

(4,7)

CC2

I

NOTES:

1. Industrial temperature range product for the 10ns speed grade is available as a standard device.

2. Measurements with 0.4

3. OE

≥ VIH, 0.4 ≤ VOUT ≤ VCC.

4. Tested with outputs open (IOUT = 0).

5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

6. For x 18 bus widths, typical ICC1 = 5 + fS + 0.002*CL*fS (in mA);
for x 9 bus widths, typical I
These equations are valid under the following conditions:
VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).

7. All Inputs = V

Active Power Supply Current (x9 Input to x9 Output) — 30 mA
Active Power Supply Current (x18 Input to x18 Output) — 35 mA
Standby Current — 15 mA

≤ VIN ≤ VCC.

CC1 = 5 + 0.775*fS + 0.002*CL*fS (in mA).

CC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

(1)

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

(2)

IN

C

Input VIN = 0V 10 pF
Capacitance

(1,2)

C

OUT

Output VOUT = 0V 10 pF
Capacitance

NOTES:

1. With output deselected, (OE

2. Characterized values, not currently tested.

(1)

≥ VIH).

Conditions Max. Unit

8

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II

IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9

512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)

Commercial Commercial Com’l & Ind’l

BGA & TQFP BGA & TQFP TQFP Only TQFP Only

IDT72V223L6 IDT72V223L7-5
IDT72V233L6 IDT72V233L7-5
IDT72V243L6 IDT72V243L7-5
IDT72V253L6 IDT72V253L7-5
IDT72V263L6 IDT72V263L7-5 IDT72V263L10 IDT72V263L15
IDT72V273L6 IDT72V273L7-5 IDT72V273L10 IDT72V273L15
IDT72V283L6 IDT72V283L7-5 IDT72V283L10 IDT72V283L15
IDT72V293L6 IDT72V293L7-5 IDT72V293L10 IDT72V293L15

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

fS Clock Cycle Frequency — 166 — 133.3 — 100 — 66.7 MHz
tA Data Access Time

(5)

141

(5)

51

(5)

tCLK Clock Cycle Time 6 — 7.5 — 10 — 15 — ns
tCLKH Clock High Time 2.7 — 3.5 — 4.5 — 6 — ns
tCLKL Clock Low Time 2.7 — 3. 5 — 4.5 — 6 — ns
tDS Data Setup Time 2 — 2.5 — 3.5 — 4 — ns
tDH Data Hold Time 0.5 — 0.5 — 0.5 — 1 — ns
tENS Enable Setup Time 2 — 2.5 — 3.5 — 4 — ns
tENH Enable Hold Time 0.5 — 0.5 — 0.5 — 1 — ns
tLDS Load Setup Time 3 — 3.5 — 3.5 — 4 — ns
tLDH Load Hold Time 0.5 — 0. 5 — 0.5 — 1 — ns
tRS Reset Pulse Width

(3)

10 — 10 — 10 — 15 — ns
tRSS Reset Setup Time 15 — 15 — 15 — 15 — ns
tRSR Reset Recovery Time 1 0 — 10 — 10 — 15 — ns
tRSF Reset to Flag and Output Time — 1 5 — 15 — 15 — 15 ns
tRTS Retransmit Setup Time 3 — 3.5 — 3.5 — 4 — ns
tOLZ Output Enable to Output in Low Z
tOE Output Enable to Output Valid
tOHZ Output Enable to Output in High Z

(4)

(5)

(4,5)

0—0—0 —0—ns
141
141

(5)

(5)

61
61

(5)

(5)

tWFF Write Clock to FF or IR —4—5—6.5—10ns
tREF Read Clock to EF or OR —4—5—6.5—10ns
tPAFA Clock to Asynchronous Programmable Almost-Full Flag — 10 — 12.5 — 16 — 20 ns
tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 4 — 5 — 6.5 — 10 ns
tPAEA Clock to Asynchronous Programmable Almost-Empty Flag — 10 — 12.5 — 16 — 20 ns
tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 4 — 5 — 6.5 — 10 ns
tHF Clock to HF — 10 — 12.5 — 16 — 20 ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 4—5—7 —9—ns

SKEW2 Skew time between RCLK and WCLK for PAE and PAF 5—7—10—14—ns

t

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Industrial temperature range product for the 10ns is available as a standard device. All other speed grades are available by special order.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

5. TQFP package only: for speed grades 7.5ns, 10ns and 15ns the minimum for t

6. The IDT72V223/72V233/72V243/72V253 are only available in 6ns and 7.5ns speed grades.

A, tOE, and tOHZ is 2ns.

(2)

Commercial

6.5 1

61
61

(5)

(5)

(5)

10 ns

8ns
8ns

9

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

— ASYNCHRONOUS TIMING

(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)

Commercial

IDT72V223L6 IDT72V223L7-5
IDT72V233L6 IDT72V233L7-5
IDT72V243L6 IDT72V243L7-5
IDT72V253L6 IDT72V253L7-5
IDT72V263L6 IDT72V263L7-5
IDT72V273L6 IDT72V273L7-5
IDT72V283L6 IDT72V283L7-5
IDT72V293L6 IDT72V293L7-5

Symbol Parameter Min. Max. Min. Max. Unit

(4)

fA
tAA
tCYC
tCYH
tCYL
tRPE
tFFA
tEFA
tPAFA

PAEA

t

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

4. Parameters apply to the BGA package only.

Cycle Frequency (Asynchronous mode) — 10 0 — 83 MHz

(4)

Data Access Time 0.6 8 0.6 10 ns

(4)

Cycle Time 10 — 12 — ns

(4)

Cycle HIGH Time 4.5 — 5 — ns

(4)

Cycle LOW Time 4.5 — 5 — ns

(4)

Read Pulse after EF HIGH 8 — 10 — ns

(4)

Clock to Asynchronous FF —8—10ns

(4)

Clock to Asynchronous EF —8—10ns

(4)

Clock to Asynchronous Programmable Almost-Full Flag — 8 — 1 0 ns

(4)

Clock to Asynchronous Programmable Almost-Empty Flag — 8 — 10 ns

10

TM

)

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II

IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9

512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load for t
Output Load for t

NOTE:

1. For 166Mhz and 133MHz operation input rise/fall times are 1.5ns.

CLK = 10ns, 15 ns See Figure 2a

CLK = 6ns, 7.5ns See Figure 2b & 2c

AC TEST LOADS - 10ns, 15ns Speed Grades

3.3V

330Ω

D.U.T.

510Ω

Figure 2a. Output Load

* Includes jig and scope capacitances.

30pF*

4666 drw04

(1)

AC TEST LOADS - 6ns, 7.5ns Speed Grade

1.5V

50

Ω

I/O

Z0 = 50

Figure 2b. AC Test Load

6

5

4

3

CD

2

t

(Typical, ns)

1

20 30 50 80 100 200

Capacitance (pF

Figure 2c. Lumped Capacitive Load, Typical Derating

Ω

4666 drw04a

4666 drw04b

OUTPUT ENABLE & DISABLE TIMING

Output

Normally

LOW

Output

Normally

HIGH

NOTE:

1. REN is HIGH.

V

V

OE

CC

2

CC

2

Output

Enable

t

OE & tOLZ

100mV

100mV

Output

Disable

100mV

t

OHZ

100mV

4666 drw04c

V

IH

VIL

V

CC

2

V

OL

VOH

V

CC

2

11

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE

The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293 support two different timing modes of operation: IDT Standard mode
or First Word Fall Through (FWFT) mode. The selection of which mode will
operate is determined during Master Reset, by the state of the FWFT/SI input.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
the first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.

Various signals, both input and output signals operate differently depending
on which timing mode is in effect.

IDT STANDARD MODE

In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.

If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
(D/2 + 1) words were written into the FIFO. If x18 Input or x18 Output bus Width
is selected, (D/2 + 1) = the 257th word for the IDT72V223, 513rd word for
IDT72V233, 1,025th word for the IDT72V243, 2,049th word for the IDT72V253,
4,097th word for the IDT72V263, 8,193th word for IDT72V273, 16,385th word
for the IDT72V283 and 32,769th word for the IDT72V293. If both x9 Input and
x9 Output bus Widths are selected, (D/2 + 1) = the 513rd word for the
IDT72V223, 1,025th word for IDT72V233, 2,049th word for the IDT72V243,
4,097th word for the IDT72V253, 8,193rd word for the IDT72V263, 16,385th
word for IDT72V273, 32,769th word for the IDT72V283 and 65,537th word
for the IDT72V293. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are
performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or
x18 Output bus Width is selected, (D-m) = (512-m) writes for the IDT72V223,
(1,024-m) writes for the IDT72V233, (2,048-m) writes for the IDT72V243 and
(4,096-m) writes for the IDT72V253, (8,192-m) writes for the IDT72V263,
(16,384-m) writes for the IDT72V273, (32,768-m) writes for the IDT72V283
and (65,536-m) writes for the IDT72V293. If both x9 Input and x9 Output bus
Widths are selected, (D-m) = (1,024-m) writes for the IDT72V223, (2,048-m)
writes for the IDT72V233, (4,096-m) writes for the IDT72V243, (8,192-m)
writes for the IDT72V253, (16,384-m) writes for the IDT72V263, (32,768-m)
writes for the IDT72V273, (65,536-m) writes for the IDT72V283 and (131,072-m)

writes for the IDT72V293. The offset “m” is the full offset value. The default setting
for these values are stated in the footnote of Table 2. This parameter is also user
programmable. See section on Programmable Flag Offset Loading.

When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. If the x18 Input or x18 Output bus Width is selected, D = 512 writes
for the IDT72V223, 1,024 writes for the IDT72V233, 2,048 writes for the
IDT72V243, 4,096 writes for the IDT72V253, 8,192 writes for the IDT72V263,
16,384 writes for the IDT72V273, 32,768 writes for the IDT72V283 and 65,536
writes for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected,
D = 1024 writes for the IDT72V223, 2,048 writes for the IDT72V233, 4,096
writes for the IDT72V243, 8,192 writes for the IDT72V253, 16,384 writes for
the IDT72V263, 32,768 writes for the IDT72V273, 65,536 writes for the
IDT72V283 and 131,072 writes for the IDT72V293, respectively.

If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.

When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs.

Relevant timing diagrams for IDT Standard mode can be found in Figure
7, 8 and 11.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n+2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of Table

2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the (D/2 + 2)
words were written into the FIFO. If x18 Input or x18 Output bus Width is selected,
(D/2 + 2) = the 258th word for the IDT72V223, 514th word for IDT72V233,
1,026th word for the IDT72V243, 2,050th word for the IDT72V253, 4,098th
word for the IDT72V263, 8,194th word for IDT72V273, 16,386th word for the
IDT72V283 and 32,770th word for the IDT72V293. If both x9 Input and x9
Output bus Widths are selected, (D/2 + 2) = the 514th word for the IDT72V223,
1,026th word for IDT72V233, 2,050th word for the IDT72V243, 4,098th word
for the IDT72V253, 8,194th word for the IDT72V263, 16,386th word for
IDT72V273, 32,770th word for the IDT72V283 and 65,538th word for the
IDT72V293. Continuing to write data into the FIFO will cause the PAF to go LOW.
Again, if no reads are performed, the PAF will go LOW after (D-m) writes to the
FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (513-m) writes
for the IDT72V223, (1,025-m) writes for the IDT72V233, (2,049-m) writes for
the IDT72V243, (4,097-m) writes for the IDT72V253, (8,193-m) writes for the
IDT72V263, (16,385-m) writes for the IDT72V273, (32,769-m) writes for the
IDT72V283 and (65,537-m) writes for the IDT72V293. If both x9 Input and x9
Output bus Widths are selected, (D-m) = (1,025-m) writes for the IDT72V223,
(2,049-m) writes for the IDT72V233, (4,097-m) writes for the IDT72V243,
(8,193-m) writes for the IDT72V253, (16,385-m) writes for the IDT72V263,

12

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II

IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9

512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

NARROW BUS FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

(32,769-m) writes for the IDT72V273, (65,537-m) writes for the IDT72V283
and (131,073-m) writes for the IDT72V293. The offset m is the full offset value.
The default setting for these values are stated in the footnote of Table 2.

When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 513
writes for the IDT72V223, 1,025 writes for the IDT72V233, 2,049 writes for the
IDT72V243, 4,097 writes for the IDT72V253, 8,193 writes for the IDT72V263,
16,385 writes for the IDT72V273, 32,769 writes for the IDT72V283 and 65,537
writes for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected,
D = 1,025 writes for the IDT72V223, 2,049 writes for the IDT72V233, 4,097
writes for the IDT72V243, 8,193 writes for the IDT72V253, 16,385 writes for
the IDT72V263, 32,769 writes for the IDT72V273, 65,537 writes for the
IDT72V283 and 131,073 writes for the IDT72V293, respectively. Note that the
additional word in FWFT mode is due to the capacity of the memory plus output
register.

If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n+1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.

When configured in FWFT mode, the OR flag output is triple register­buffered, and the IR flag output is double register-buffered.

Relevant timing diagrams for FWFT mode can be found in Figure 9, 10 and

12.

PROGRAMMING FLAG OFFSETS

Full and Empty Flag offset values are user programmable. The IDT72V223/
72V233/72V243/72V253/72V263/72V273/72V283/72V293 has internal reg­isters for these offsets. There are eight default offset values selectable during
Master Reset. These offset values are shown in Table 2. Offset values can also

be programmed into the FIFO in one of two ways; serial or parallel loading
method. The selection of the loading method is done using the LD (Load) pin.
During Master Reset, the state of the LD input determines whether serial or
parallel flag offset programming is enabled. A HIGH on LD during Master Reset
selects serial loading of offset values. A LOW on LD during Master Reset selects
parallel loading of offset values.

In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.

Figure 3, Programmable Flag Offset Programming Sequence, summaries
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.

The offset registers may be programmed (and reprogrammed) any time after
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.

SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION

The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293 can be configured during the Master Reset cycle with either synchro­nous or asynchronous timing for PAF and PAE flags by use of the PFM pin.

If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 18 for synchronous
PAF timing and Figure 19 for synchronous PAE timing.

If asynchronous PAF/PAE configuration is selected (PFM, LOW during

MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE

is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure
20 for asynchronous PAF timing and Figure 21 for asynchronous PAE timing.

TABLE 2  DEFAULT PROGRAMMABLE FLAG OFFSETS

IDT72V253
IDT72V223 IDT72V263
IDT72V233 IDT72V243 IDT72V273 IDT72V283 IDT72V293

Offsets n,m Offsets n,m Offsets n,m Offsets n,m Offsets n,m

All Other x9 to x9 All Other x9 to x9

LD FSEL0 FSEL1 All Modes Modes Mode All Modes Modes Mode All Modes

L L H 511 511 511 511 511 16,383 16,383
L H L 255 255 255 255 255 8,191 8,191
L H H 63 63 63 63 63 4,095 4,095
H L H 1 5 15 31 31 31 2,047 2,047
H L L 31 31 1,023 1,023 1,023 1,023 1,023
H H L 7 7 15 15 15 511 511
H H H 3 3 7 7 7 255 255
L L L 127 127 127 127 127 127 127
H X X Serial Programming Mode
L X X Parallel Programming Mode

NOTES:

1. n = empty offset for PAE.

2. m = full offset for PAF.

3. As well as selecting serial programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.

4. As well as selecting parallel programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.

(3)

(4)

13

TM

IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC II

NARROW BUS FIFO

512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9

TABLE 3  STATUS FLAGS FOR IDT STANDARD MODE

IW = OW = x9

IW ≠ OW or
IW = OW = x18

Number of
Words in

(2)

FIFO

IDT72V223

IDT72V223

257 to (512-(m+1)) 513 to (1,024-(m+1))

IDT72V233 IDT72V243

(1,024-m) to 1,023

IDT72V233

0

1 to n

(n+1) to 1,024

1,025 to (2,048-(m+1))

(2,048-m) to 2,047

2,048

IDT72V243

IDT72V253

000

1 to n1 to n 1 to n

(n+1) to 2,048(n+1) to 256 (n+1) to 512

2,049 to (4,096-(m+1))

(4,096-m) to 4,095(512-m) to 511

4,096512 1,024

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

FF PAF

HHHL

HHHL H

HHHH H

HHL H H

HLLHH

L

PAE

HF

LLHH

EF

L

IW = OW = x9

IW ≠ OW or
IW = OW = x18

Number of
Words in

(2)

FIFO

IDT72V253

IDT72V263

0

1 to n

(n+1) to 4,096

4,097 to (8,192-(m+1))

(8,192-m) to 8,191

8,192

IDT72V263

IDT72V273

00

1 to n 1 to n

(n+1) to 8,192 (n+1) to 16,384

8,193 to (16,384-(m+1)) 16,385 to (32,768-(m+1))

(16,384-m) to 16,383

16,384 32,768

NOTE:

1. See Table 2 for values for n, m.

TABLE 4  STATUS FLAGS FOR FWFT MODE

IW = OW = x9

IW ≠ OW or
IW = OW = x18

Number of
Words in

(2)

FIFO

IW = OW = x9

IW ≠ OW or
IW = OW = x18

Number of
Words in

(2)

FIFO

IDT72V223

258 to (513-(m+1)) 514 to (1,025-(m+1))

IDT72V253

IDT72V263

0

1 to n+1

(n+2) to 4,097

4,098 to (8,193-(m+1))

(8,193-m) to 8,192

8,193

NOTE:

1. See Table 2 for values for n, m.

2. Number of Words in FIFO = FIFO Depth + Output Register

IDT72V223

IDT72V233 IDT72V243

(1,025-m) to 1,024

IDT72V263

IDT72V273

00

1 to n+1 1 to n+1

(n+2) to 8,193 (n+2) to 16,385

8,194 to (16,385-(m+1)) 16,386 to (32,769-(m+1))

(16,385-m) to 16,384

16,385 32,769

IDT72V273

IDT72V283 IDT72V293

(32,768-m) to 32,767

32,769 to (65,536-(m+1)) 65,537 to (131,072-(m+1))

(65,536-m) to 65,535 (131,072-m) to 131,071

IDT72V233

0

1 to n+1

(n+2) to 1,025

1,026 to (2,049-(m+1))

(2,049-m) to 2,048

2,049

2,050 to (4,097-(m+1))

IDT72V273

IDT72V283 IDT72V293

(32,769-m) to 32,768

32,770 to (65,537-(m+1)) 65,538 to (131,073-(m+1))

(65,537-m) to 65,536 (131,073-m) to 131,072

IDT72V283 IDT72V293

00

1 to n

(n+1) to 32,768

65,536

1 to n

(n+1) to 65,536

131,072

IDT72V243

IDT72V253

000

1 to n+11 to n+1 1 to n+1

(n+2) to 2,049(n+2) to 257 (n+2) to 513

(4,097-m) to 4,096(513-m) to 512

4,097513 1,025

IR PAF

L HHL

L HHL L

L HHH L

LHLHL

LLLHL

H

PAE

HF

LLHL

IDT72V283 IDT72V293

00

1 to n+1

(n+2) to 32,769

65,537

1 to n+1

(n+2) to 65,537

131,073

FF PAF

HHHL

HHHL H

HHHH H

HHL H H

HLLHH

L

PAE

HF

LLHH

OR

H

IR PAF

L HHL

L HHL L

L HHH L

LHLHL

LLLHL

H

PAE

HF

LLHL

EF

L

OR

H

4666 drw05

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