Integrated Device Technology Inc IDT72V01L25J, IDT72V01L35J, IDT72V02L25J, IDT72V02L35J, IDT72V03L25J Datasheet

Integrated Device Technology, Inc.

3.3 VOLT CMOS
ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9

IDT72V01
IDT72V02
IDT72V03

IDT72V04

FEATURES:

• 3.3V family uses 70% less power than the 5 Volt 7201/
02/03/04 family

• 512 x 9 organization (72V01)

• 1024 x 9 organization (72V02)

• 2048 x 9 organization (72V03)

• 4096 X 9 organization (72V04)

• Functionally compatible with 720x family

• 25 ns access time

• Asynchronous and simultaneous read and write

• Fully expandable by both word depth and/or bit width

• Status Flags: Empty, Half-Full, Full

• Auto-retransmit capability

• Available in 32-pin PLCC and 28-pin SOIC Package (to
be determined)

• Industrial temperature range (-40

o

C to +85oC) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT72V01/72V02/72V03/72V04 are dual-port FIFO
memories that operate at a power supply voltage (Vcc)
between 3.0V and 3.6V. Their architecture, functional opera­tion and pin assignments are identical to those of the IDT7201/

7202/7203/7204. These devices load and empty data on a
first-in/first-out basis. They use Full and Empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.

The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (W) and Read (R) pins. The devices

have a maximum data access time as fast as 25 ns.

The devices utilize a 9-bit wide data array to allow for
control and parity bits at the user’s option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. They also feature a Retransmit (RT) capability
that allows for reset of the read pointer to its initial position
when RT is pulsed low to allow for retransmission from the
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.

The IDT72V01/72V02/72V03/72V04 is fabricated using
IDT’s high-speed CMOS technology. It has been designed for
those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications.

FUNCTIONAL BLOCK DIAGRAM

DATA INPUTS

0(D –D8)

W

R

XI

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.

COMMERCIAL TEMPERATURE RANGE DECEMBER 1996

1996 Integrated Device Technology, Inc. DSC-3033/6

WRITE

CONTROL

WRITE

POINTER

THREE­STATE
BUFFERS

READ

CONTROL

FLAG

LOGIC

EXPANSION

LOGIC

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

RAM

ARRAY

512x 9
1024 x 9
2048 x 9
4096 x 9

DATA OUTPUTS

0(Q –Q8)

EF
FF

XO/HF

5.08 1

READ

POINTER

RS

RESET

LOGIC

FL/RT

2679 drw 01

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS

W

D8

1
2

28

27
D3 D5326
D2 D6425
D1 D7524
D0

XI RS

FF EF

Q0

623
722
821

920
Q1 Q710 19
Q2 Q611 18
Q3 Q512 17
Q8 Q413 16

GND

14 15

SMALL OUTLINE PACKAGE TO BE DETERMINED

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Com’l. Unit

V

TERM Terminal Voltage –0.5 to +7.0 V

with Respect
to GND

T

A Operating 0 to +70 °C

Temperature

T

BIAS Temperature –55 to +125 °C

Under Bias

T

STG Storage –55 to +125 °C

Temperature

I

OUT DC Output 50 mA

Current

NOTE: 2679 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.

VCC
D4

FL/RT

XO/HF

R

2679 drw 02a

(1)

INDEX

D2 5

1 6

D

0 7

D

XI

FF

0 10

Q

1 11

Q

NC 12

2 13

Q

8

3

D

D

WNCV

3 2132 31 30

4

8

J32-1

9

CC

4

5

D

D

29
28
27
26
25
24
23
22
21

D6
D7
NC

FL/RT
RS
EF
XO/HF

7

Q
Q6

14 15 16 17 18 19 20

Q3Q

8

GND

NC

4Q5

R

Q

2679 drw 02b

PLCC

TOP VIEW

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Rating Min. Typ. Max. Unit

CC Supply Voltage 3.0 3.3 3.6 V

V
GND Supply Voltage 0 0 0 V

(1)

IH

V

IL

V

NOTE: 2679 tbl 03

1. VIH = 2.6V for XI input (commercial).

2. 1.5V undershoots are allowed for 10ns once per cycle.

Input High Voltage 2.0 — VCC+0.5 V

(2)

Input Low Voltage — — 0.8 V

CAPACITANCE (TA = +25°C, f = 1.0 MHz)

Symbol Parameter

C

IN Input Capacitance VIN = 0V 8 pF
OUT Output Capacitance VOUT = 0V 8 pF

C

NOTE: 2679 tbl 02

1. This parameter is sampled and not 100% tested.

(1)

Condition Max. Unit

5.08 2

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 3.3 V ± 0.3V, TA = 0°C to +70°C)

IDT72V01/72V02/ IDT72V01/72V02/

72V03/72V04 72V03/72V04

Commercial Commercial

t

A = 25 ns tA = 35 ns

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit

(1)

LI

I

(2)

LO

I

OH Output Logic “1” Voltage IOH = –2mA 2.4 — — 2.4 — — V

V

OL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 V

V

(3,4)

CC1

I

(3)

CC2

I

CC3(L)

I

NOTES: 2679 tbl 05

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2.R ≥ V

CC measurements are made with outputs open (only capacitive loading).

3. I

4. Tested at f = 20MHz.

Input Leakage Current (Any Input) –1 — 1 –1 — 1 µA
Output Leakage Current –10 — 10 –10 — 10 µA

Active Power Supply Current — 35 50 — 35 50 mA
Standby Current (R=W=RS=FL/RT=VIH)—58—58mA

(3)

Power Down Current (All Input = VCC - 0.2V) — — 0.3 — — 0.3 mA

IH, 0.4 ≤ VOUT ≤ VCC.

5.08 3

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 3.3V±0.3V, TA = 0°C to +70°C)

Commercial Commercial
72V01L25/72V02L25 72V01L35/72V02L35
72V03L25/72V04L25 72V03L35/72V04L35

Symbol Parameter Min. Max. Min. Max. Unit

S Shift Frequency — 28.5 — 22.2 MHz

f

RC Read Cycle Time 35 — 45 — ns

t
t

A Access Time — 25 — 35 ns
RR Read Recovery Time 10 — 10 — ns

t

RPW Read Pulse Width

t
t

RLZ Read Pulse Low to Data Bus at Low Z
WLZ Write Pulse High to Data Bus at Low Z

t

DV Data Valid from Read Pulse High 5 — 5 — ns

t
t

RHZ Read Pulse High to Data Bus at High Z
WC Write Cycle Time 35 — 45 — ns

t

WPW Write Pulse Width

t
t

WR Write Recovery Time 10 — 10 — ns

DS Data Set-up Time 15 — 18 — ns

t

DH Data Hold Time 0 — 0 — ns

t

RSC Reset Cycle Time 35 — 45 — ns

t
t

RS Reset Pulse Width

RSS Reset Set-up Time

t

RSR Reset Recovery Time 10 — 10 — ns

t
t

RTC Retransmit Cycle Time 35 — 45 — ns

RT Retransmit Pulse Width

t

RTS Retransmit Set-up Time

t
t

RTR Retransmit Recovery Time 10 — 10 — ns
EFL Reset to Empty Flag Low — 35 — 45 ns

t

HFH,FFH Reset to Half-Full and Full Flag High — 35 — 45 ns

t
t

RTF Retransmit Low to Flags Valid — 35 — 45 ns
REF Read Low to Empty Flag Low — 25 — 30 ns

t

RFF Read High to Full Flag High — 25 — 30 ns

t

RPE Read Pulse Width after

t
t

WEF Write High to Empty Flag High — 25 — 30 ns
WFF Write Low to Full Flag Low — 25 — 30 ns

t

WHF Write Low to Half-Full Flag Low — 35 — 45 ns

t
t

RHF Read High to Half-Full Flag High — 35 — 45 ns
WPF Write Pulse Width after

t

XOL Read/Write to

t
t

XOH Read/Write to

XI

t

XIR

t
t

XIS

NOTES: 2679 tbl 06

1. Timings referenced as in AC Test Conditions. 3. Values guaranteed by design, not currently tested.

2. Pulse widths less than minimum value are not allowed. 4. Only applies to read data flow-through mode.

XI

Pulse Width

XI

Recovery Time 10 — 10 — ns

XI

Set-up Time 10 — 10 — ns

(2)

(3)

(3,4)

(3)

(2)

(2)

(3)

(2)

(3)

EF

High 25 — 35 — ns

FF

High 25 — 35 — ns

XO

Low — 25 — 35 ns

XO

High — 25 — 35 ns

(2)

25 — 35 — ns

5—5—ns
5—10—ns

— 18 — 20 ns

25 — 35 — ns

25 — 35 — ns
25 — 35 — ns

25 — 35 — ns
25 — 35 — ns

25 — 35 — ns

5.08 4