IDT IDT72T7285, IDT72T7295, IDT72T72105, IDT72T72115 User Manual

查询IDT72T72105供应商

2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS

16,384 x 72, 32,768 x 72,
65,536 x 72, 131,072 x 72

FEATURES:

••

• Choose among the following memory organizations:

••

IDT72T7285
IDT72T7295
IDT72T72105
IDT72T72115

••

Up to 225 MHz Operation of Clocks

•

••

••

• User selectable HSTL/LVTTL Input and/or Output

••

••

• Read Enable & Read Clock Echo outputs aid high speed operation

••

••

•

User selectable Asynchronous read and/or write port timing

••

••

•

2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage

••

••

•

3.3V Input tolerant

••

••

Mark & Retransmit, resets read pointer to user marked position

•

••

••

• Write Chip Select (WCS) input disables Write Port HSTL inputs

••

••

• Read Chip Select (RCS) synchronous to RCLK

••

••

• Programmable Almost-Empty and Almost-Full flags, each flag can

••

default to one of eight preselected offsets

••

• Program programmable flags by either serial or parallel means

••

••

• Selectable synchronous/asynchronous timing modes for Almost-

••

Empty and Almost-Full flags

••

• Separate SCLK input for Serial programming of flag offsets

••



 16,384 x 72




 32,768 x 72




 65,536 x 72




 131,072 x 72



IDT72T7285, IDT72T7295,

IDT72T72105, IDT72T72115

••

• User selectable input and output port bus-sizing

••

- x72 in to x72 out

- x72 in to x36 out

- x72 in to x18 out

- x36 in to x72 out

- x18 in to x72 out

••

• Big-Endian/Little-Endian user selectable byte representation

••

••

•

Auto power down minimizes standby power consumption

••

••

•

Master Reset clears entire FIFO

••

••

•

Partial Reset clears data, but retains programmable settings

••

••

Empty, Full and Half-Full flags signal FIFO status

•

••

••

• Select IDT Standard timing (using EF and FF flags) or First Word

••

Fall Through timing (using OR and IR flags)

••

• Output enable puts data outputs into high impedance state

••

••

• JTAG port, provided for Boundary Scan function

••

••

• Available in 324-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)

••

••

• Easily expandable in depth and width

••

••

• Independent Read and Write Clocks (permit reading and writing

••

simultaneously)

••

• High-performance submicron CMOS technology

••

••

• Industrial temperature range (–40

••

°°

°C to +85

°°

°°

°C) is available

°°

FUNCTIONAL BLOCK DIAGRAM

WEN

WCLK/WR

WCS

ASYW

BE

IP

BM

IW

OW

MRS

PRS

TCK

TRST

TMS
TDO

TDI

Vref

WHSTL

RHSTL
SHSTL

WRITE CONTROL

LOGIC

WRITE POINTER

CONTROL

LOGIC

BUS

CONFIGURATION

RESET

LOGIC

JTAG CONTROL

(BOUNDARY SCAN)

HSTL I/0

CONTROL

OE

D0 -D

n

(x72, x36 or x18)

INPUT REGISTER

RAM ARRAY

16,384 x 72
32,768 x 72
65,536 x 72

131,072 x 72

OUTPUT REGISTER

Q0 -Qn (x72, x36 or x18)

LD

OFFSET REGISTER

FLAG

LOGIC

READ POINTER

READ

CONTROL

LOGIC

EREN

ERCLK

SEN

SCLK

RT

MARK

ASYR

RCLK/RD

REN
RCS

5994 drw01

FF/IR
PAF
EF/OR
PAE
HF

FWFT/SI
PFM
FSEL0
FSEL1

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

1



2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

SEPTEMBER 2003

DSC-5994/12

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

PIN CONFIGURATION

A1 BALL PAD CORNER



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

A

V

B

D59

C

D57

D

E

D51

F

D48

G

D45

H

D44

J

D41

K

D36

L

D33

M

D30

N

D27

P

D24

R

D21

T

D19 D20 D13

U

D18

V

V

PRS

CC

D60

D61

D58 D62 D70

D55

D56

D53

D52

D50

D49

D47

D46

SEN

SCLK

D43

D42

D39

D40

D38

D37

D35

D34

D32

D31

D29

D28

D26

D25 Q27

D22

D23

D64

D65 D71D68

V

CC

V

CC

WHSTL

ASYW

VREF

IW

V

CC

V

CC

V

CC

V

CC

V

CC

D66

D67

V

V

V

V

V

V

V

V

V

CC

CC

CC

CC

CC

CC

CC

CC

V

CC

V

CC

CC

D5D10

D14D17

CC

D16 D15

D9D12

WCLK

D69

WEN

WCS

GND

MRS

GND

GND Q68MARK Q71

SHSTLFWFT/SI FS0OW IPFS1BEGND PFMBM

V

CC

V

CC

V

CC

CC

CC

CC

CC

CC

V

CC

V

CC

V

CC

V

CC

D4 TMS

D6

V

GNDV

GNDV

GNDV

GNDV

GNDV

GND

V

V

V

D1

D2

D3

CC

CC

CC

CC

V

CC

V

CC

GND

GND

GND

GND

GND GND

GND

GND

GND

V

CC

CC

GND

V

CC

TRST

TCK

D0

GND

GND

GNDV

TDO

TDI

FF

PAF

EREN

EF

PAELD HF

RCLKD63

REN

OE

RCS

RT

RHSTL

V

DDQ

GNDGND V

V

GNDGND V

GND

GND

GND

GND

GND GNDGND V

GND V

GND V

GND V

DDQ

V

DDQ

DDQ

DDQ

V

DDQ

GNDGND GNDGND GND V

GND

GND

GND

GND

DDQVDDQ

V

DDQ

V

DDQ

V

DDQ

GND V

V

DDQ

GND

V

DDQ

GND

V

DDQ

GND

V

DDQ

V

DDQ

V

DDQ

V

DDQ

DDQ

V

DDQ

DDQ

Q5D11 D8D7 GND Q6Q1 Q9 Q12

Q69 Q66

ASYR

V

DDQ

V

DDQ

DDQ

DDQ

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQVDDQ

Q64

Q65

Q67Q70

Q58

Q55D54

Q52

V

DDQ

Q49

V

DDQ

Q46

V

DDQ

V

DDQ

Q43

DDQ

Q40

V

V

DDQ

Q39

V

DDQ

Q36

V

DDQ

Q33

V

DDQ

Q30

V

DDQ

Q24

Q14GND Q0 Q2 Q11Q8Q3

Q15

Q16GND ERCLK Q4 Q13Q10Q7

Q61

Q59

Q56

Q53

Q50

Q47

Q44

Q41

Q38

Q35

Q32

Q29

Q26

Q23

Q18

Q17

V

V

Q62

Q60

Q57

Q54

Q51

Q48

Q45

Q42

Q37

Q34

Q31

Q28

Q25

Q22

Q20Q21

Q19

DDQ

DDQ

Q63

12 345678910111213141516

PBGA: 1mm pitch, 19mm x 19mm (BB324-1, order code: BB)

TOP VIEW

2

17 18

5994 drw02

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION:

The IDT72T7285/72T7295/72T72105/72T72115 are exceptionally deep,
extremely high speed, CMOS First-In-First-Out (FIFO) memories with clocked
read and write controls and a flexible Bus-Matching x72/x36/x18 data flow.
These FIFOs offer several key user benefits:

• Flexible x72/x36/x18 Bus-Matching on both read and write ports

• A user selectable MARK location for retransmit

• User selectable I/O structure for HSTL or LVTTL

• Asynchronous/Synchronous translation on the read or write ports

• The first word data latency period, from the time the first word is written to an

empty FIFO to the time it can be read, is fixed and short.

• High density offerings up to 9 Mbit

Bus-Matching TeraSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.

Each FIFO has a data input port (D
which can assume either a 72-bit, 36-bit or a 18-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus­Matching (BM) pin during the Master Reset cycle.

The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).

The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, also the RCS should be
tied LOW and the OE input used to provide three-state control of the outputs, Qn.

The output port can be selected for either 2.5V LVTTL or HSTL operation,
this operation is selected by the state of the RHSTL input during a master reset.

An Output Enable (OE) input is provided for three-state control of the outputs.
A Read Chip Select (RCS) input is also provided, the RCS input is synchronized
to the read clock, and also provides three-state control of the Qn data outputs.
When RCS is disabled, the data outputs will be high impedance. During
Asynchronous operation of the output port, RCS should be enabled, held LOW.

Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the FIFO that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect to EREN and ERCLK, this is very useful when data is being read at
high speed. The ERCLK and EREN outputs are non-functional when the Read
port is setup for Asynchronous mode.

The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.

There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read

n) and a data output port (Qn), both of

operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.

For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that PAE can be set to switch at a predefined number of locations
from the empty boundary and the PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and LD pins.

For serial programming, SEN together with LD on each rising edge of
SCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via D

n. REN together with LD on each rising edge

of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.

During Master Reset (MRS) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.

The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect. PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.

It is also possible to select the timing mode of the PAE (Programmable Almost­Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.

If asynchronous PAE/PAF configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW­to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW­to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.

If synchronous PAE/PAF configuration is selected , the PAE is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during Master Reset by the state of the Programmable Flag
Mode (PFM) pin.

This device includes a Retransmit from Mark feature that utilizes two control
inputs, MARK and , RT (Retransmit). If the MARK input is enabled with respect
to the RCLK, the memory location being read at that point will be marked. Any
subsequent retransmit operation, RT goes LOW, will reset the read pointer to
this ‘marked’ location.

3

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION (CONTINUED)

The device can be configured with different input and output bus widths as

shown in Table 1.

A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x36/x18) and read
out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected,
then the most significant byte (word) of the long word written into the FIFO will
be read out of the FIFO first, followed by the least significant byte. If Little-Endian
format is selected, then the least significant byte of the long word written into the
FIFO will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 5 for Bus-Matching Byte Arrangement.

The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8 and D17 are assumed to be valid bits. IP mode
is selected during Master Reset by the state of the IP input pin.

If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.

Both an Asynchronous Output Enable pin (OE) and Synchronous Read
Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip
Select is synchronized to the RCLK. Both the output enable and read chip select
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.

A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.

The TeraSync FIFO has the capability of operating its ports (write and/or
read) in either LVTTL or HSTL mode, each ports selection independent of the
other. The write port selection is made via WHSTL and the read port selection
via RHSTL. An additional input SHSTL is also provided, this allows the user
to select HSTL operation for other pins on the device (not associated with the
write or read ports).

The IDT72T7285/72T7295/72T72105/72T72115 are fabricated using
IDT’s high speed submicron CMOS technology.

4

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PARTIAL RESET (PRS)

WRITE CLOCK (WCLK/WR)

WRITE ENABLE (WEN)

WRITE CHIP SELECT (WCS)

LOAD (LD)

SERIAL CLOCK (SCLK)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE ALMOST-FULL (PAF)

INPUT WIDTH (IW)

MASTER RESET (MRS)

READ CLOCK (RCLK/RD)
READ ENABLE (REN)

IDT
72T7285
72T7295

72T72105
72T72115

(x72, x36, x18) DATA OUT (Q0 - Qn)(x72, x36, x18) DATA IN (D0 - Dn)

RCLK ECHO, ERCLK

REN ECHO, EREN

MARK
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)

INTERSPERSED/
NON-INTERSPERSED PARITY (IP)

BUS-

OUTPUT WIDTH (OW)

MATCHING

(BM)

OUTPUT ENABLE (OE)

READ CHIP SELECT (RCS)

5994 drw03

Figure 1. Single Device Configuration Signal Flow Diagram

TABLE 1 — BUS-MATCHING CONFIGURATION MODES

BM I W OW Write Port Width Read Port Width

L L L x72 x72
H L L x72 x36
H L H x72 x18
H H L x36 x72
H H H x18 x72

NOTE:

1. Pin status during Master Reset.

5

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION

Symbol Name I/O TYPE Description

(1)

ASYR

ASYW

BE

BM

D

EF/OR Empty Flag/ HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.

ERCLK RCLK Echo HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.

EREN Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.

FF/IR Full Flag/ HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is

FSEL0

FSEL1

FWFT/ First Word Fall HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin

SI Through/Serial In INPUT functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been

HF Half-Full Flag HSTL-LVTTL HF indicates whether the FIFO memory is more or less than half-full.

IP

IW

LD Load HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,

MARK Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit

MRS Master Reset HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master

OE Output Enable HSTL-LVTTL OE provides Asynchronous three-state control of the data outputs, Q

OW

Asynchronous LVTTL A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port INPUT will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.

(1)

Asynchronous LVTTL A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
Write Port INPUT will select Asynchronous operation.

(1)

Big-Endian/ LVTTL During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
Little-Endian INPUT will select Little-Endian format.

(1)

Bus-Matching LVTTL BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size

INPUT configuration.

0–D71 Data Inputs HSTL-LVTTL Data inputs for a 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused input pins are in a don’t care

INPUT state.

Output Ready OUTPUT In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the

outputs.

OUTPUT

OUTPUT

Input Ready OUTPUT full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for

writing to the FIFO memory.

(1)

Flag Select Bit 0 LVTTL During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the

INPUT programmable flags PAE and PAF. There are up to eight possible settings available.

(1)

Flag Select Bit 1 LVTTL During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the

INPUT programmable flags PAE and PAF. There are up to eight possible settings available.

selected then the FIFO must be set-up in IDT Standard mode.

OUTPUT

(1)

Interspersed Parity LVTTL During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed

INPUT Parity mode.

(1)

Input Width LVTTL This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration.

INPUT

INPUT determines one of eight default offset values for the PAE and PAF flags, along with the method by which these

offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing
to and reading from the offset registers. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE OR
READ DATA TO/FROM THE FIFO MEMORY.

INPUT operation will reset the read pointer to this position.

INPUT Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,

Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings,
serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode,
interspersed parity, and synchronous versus asynchronous programmable flag timing modes.

n. During a Master or Partial Reset the

INPUT OE input is the only input that provide High-Impedance control of the data outputs.

(1)

Output Width LVTTL This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.

INPUT

6

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol Name I/O TYPE Description

PAE Programmable HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the

Almost-Empty Flag OUTPUT Empty Offset register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal

to offset n.

PAF Programmable HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in

Almost-Full Flag OUTPUT the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal

to m.

(1)

PFM

PRS Partial Reset HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,

0–Q71 Data Outputs HSTL-LVTTL Data outputs for an 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, any unused output pins should not

Q

RCLK/ Read Clock/ HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
RD Read Strobe INPUT reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded

RCS Read Chip Select HSTL-LVTTL RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During

REN Read Enable HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enables RCLK for reading data from the

RHSTL

RT Retransmit HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to

SCLK Serial Clock HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that

SEN Serial Enable HSTL-LVTTL SEN enables serial loading of programmable flag offsets.

SHSTL System HSTL LVTTL All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.

TCK

TDI

TDO

TMS

Programmable LVTTL During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
Flag Mode INPUT PFM will select Synchronous Programmable flag timing mode.

INPUT the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings

are all retained.

OUTPUT be connected. Outputs are not 3.3V tolerant regardless of the state of OE and RCS.

into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has
been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be
tied LOW.

INPUT a Master Reset or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance

regardless of RCS.

INPUT FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN

input should be tied LOW.

(1)

Read Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
Select INPUT required, this input must be tied HIGH. Otherwise it should be tied LOW.

INPUT HIGH in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode or

programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to
the ‘mark’ location.

INPUT SEN is enabled.

INPUT

Select INPUT

(2)

JTAG Clock HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations

INPUT of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and

outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.

(2)

JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Input INPUT test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register

and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.

(2)

JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Output OUTPUT test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID

Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and
SHIFT-IR controller states.

(2)

JTAG Mode HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
Select INPUT the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.

7

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol Name I/O TYPE Description

(2)

TRST

WEN Write Enable HSTL-LVTTL When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into

WCS Write Chip Select HSTL-LVTTL This pin disables the write port data inputs when the device write port is configured for HSTL mode. This

WCLK/ Write Clock/ HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
W R Write Strobe INPUT writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into

WHSTL

VCC +2.5v Supply I These are Vcc supply inputs and must be connected to the 2.5V supply rail.
GND Ground Pin I These are Ground pins and must be connected to the GND rail.
Vref Reference I This is a Voltage Reference input and must be connected to a voltage level determined from the table,

DDQ O/P Rail Voltage I This pin should be tied to the desired voltage rail for providing power to the output drivers.

V

JTAG Reset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically

INPUT reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.

If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper
FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.

INPUT the FIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the

WEN input should be tied LOW.

INPUT provides added power savings.

the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).

(1)

Write Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must
Select INPUT be tied HIGH. Otherwise it should be tied LOW.

Voltage “Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class

inputs. If HSTL class inputs are not being used, this pin should be tied LOW.

NOTES:

1. Inputs should not change state after Master Reset.

2. These pins are for the JTAG port. Please refer to pages 29-31 and Figures 6-8.

8

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Unit

TERM Terminal Voltage –0.5 to +3.6

V

with respect to GND

STG Storage Temperature –55 to +125 °C

T

OUT DC Output Current –50 to +50 mA

I

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. Compliant with JEDEC JESD8-5. V

CC terminal only.

(2)

V

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

(2,3)

IN

C

Input VIN = 0V 10
Capacitance

(1,2)

C

OUT

Output VOUT = 0V 10 pF
Capacitance

NOTES:

1. With output deselected, (OE ≥ V

2. Characterized values, not currently tested.

IN for Vref is 20pF.

3. C

(1)

Conditions Max. Unit

IH).

RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 2.375 2.5 2.625 V

V

GND Supply Voltage 0 0 0 V

IH Input High Voltage  LVTTL 1.7 — 3.45 V

V

 eHSTL V
 HSTL V

IL Input Low Voltage  LVTTL -0.3 — 0.7 V

V

 eHSTL -0.3 — V
 HSTL -0.3 — V

(1)

REF

V

Voltage Reference Input  eHSTL 0.8 0.9 1.0 V

 HSTL 0.68 0.75 0.9 V

A Operating Temperature Commercial 0 — 7 0 °C

T

A Operating Temperature Industrial -40 — 8 5 °C

T

NOTE:

1. V

REF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.

2. Outputs are not 3.3V tolerant.

REF+0.2 — VDDQ+0.3 V
REF+0.2 — VDDQ+0.3 V

REF-0.2 V
REF-0.2 V

(3)

pF

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)

Symbol Parameter Min. Max. Unit

I

LI Input Leakage Current –1 0 1 0 µA
LO Output Leakage Current –1 0 1 0 µA

I

(5)

V

OH

OL Output Logic “0” Voltage, IOL = 8 mA @V DDQ = 2.5V ± 0.125V (LVTTL) — 0.4V V

V

(1,2)

I

CC1

(1)

I

CC2

NOTES:

1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.

2. Typical I

3. Typical I

4. Total Power consumed: PT = (V

5. Outputs are not 3.3V tolerant.

Output Logic “1” Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) VDDQ -0.4 — V

OH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) VDDQ -0.4 — V

I

OH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL) VDDQ -0.4 — V

I

OL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) — 0.4V V

I

OL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL) — 0.4V V

I

Active VCC Current (VCC = 2.5V) I/O = LVTTL — 8 0 mA

I/O = HSTL — 130 m A
I/O = eHSTL — 130 mA

Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 20 mA

I/O = HSTL — 90 mA
I/O = eHSTL — 90 mA

CC1 calculation: for LVTTL I/O ICC1 (mA) = 2.24mA x fs, fs = WCLK frequency = RCLK frequency (in MHz)
DDQ calculation: With Data Outputs in High-Impedance: IDDQ (mA) = 0.15mA x fs

for HSTL or eHSTL I/O I
With Data Outputs in Low-Impedance: I

fs = WCLK frequency = RCLK frequency (in MHz), V

A = 25°C, CL = capacitive load (pf).

t

CC x ICC) + VDDQ x IDDQ).

CC1 (mA) = 55mA + (2.24mA x fs), fs = WCLK frequency = RCLK frequency (in MHz)

DDQ (mA) = (CL x VDDQ x fs x N)/2000

DDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, N = Number of outputs switching.

9

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

— SYNCHRONOUS TIMING

(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)

Commercial Com’l & Ind’l Commercial

IDT72T7285L4-4 IDT72T7285L5 IDT72T7285L6-7 IDT72T7285L10

IDT72T7295L4-4 IDT72T7295L5 IDT72T7295L6-7 IDT72T7295L10
IDT72T72105L4-4 IDT72T72105L5 IDT72T72105L6-7 IDT72T72105L10
IDT72T72115L4-4 IDT72T72115L5 IDT72T72115L6-7 IDT72T72115L10

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

fC Clock Cycle Frequency (Synchronous) — 22 5 — 200 — 1 50 100 MHz
tA Data Access Time 0.6 3.4 0.6 3.6 0.6 3.8 0.6 4.5 ns
tCLK Clock Cycle Time 4.44 — 5 — 6.7 — 10 — ns
tCLKH Clock High Time 2. 0 — 2.3 — 2. 8 — 4. 5 — ns
tCLKL Clock Low Time 2.0 — 2.3 — 2.8 — 4.5 — ns
tDS Data Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tDH Data Hold Time 0.5 — 0.5 — 0.5 — 0. 5 — ns
tENS Enable Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tENH Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tLDS Load Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tLDH Load Hold Time 0 .5 — 0.5 — 0.5 — 0.5 — ns
tWCSS WCS setup time 1. 2 — 1.5 — 2.0 — 3.0 — ns
tWCSH WCS hold time 0.5 — 0.5 — 0. 5 — 0.5 — ns
fS Clock Cycle Frequency (SCLK) — 10 — 10 — 10 — 10 M Hz
tSCLK Serial Clock Cycle 100 — 100 — 100 — 100 — ns
tSCKH Serial Clock High 4 5 — 45 — 45 — 4 5 — ns
tSCKL Serial Clock Low 45 — 45 — 45 — 45 — ns
tSDS Serial Data In Setup 1 5 — 15 — 15 — 15 — ns
tSDH Serial Data In Hold 5 — 5 — 5 — 5 — ns
tSENS Serial Enable Setup 5 — 5 — 5 — 5 — ns
tSENH Serial Enable Hold 5 — 5 — 5 — 5 — ns
tRS Reset Pulse Width
tRSS Reset Setup Time 15 — 15 — 15 — 15 — ns
tHRSS HSTL Reset Setup Time 4 — 4 — 4 — 4 — µs
tRSR Reset Recovery Time 1 0 — 10 — 1 0 — 1 0 — ns
tRSF Reset to Flag and Output Time — 10 — 12 — 15 — 15 ns
tWFF Write Clock to FF or IR — 3.4 — 3.6 — 3.8 — 4.5 ns
tREF Read Clock to EF or OR — 3.4 — 3.6 — 3.8 — 4.5 ns
tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 3.4 — 3.6 — 3.8 — 4.5 ns
tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 3.4 — 3.6 — 3.8 — 4.5 ns
tERCLK RCLK to Echo RCLK output — 3.8 — 4 — 4. 3 — 5 ns
tCLKEN RCLK to Echo REN output — 3.4 — 3.6 — 3.8 — 4.5 ns
tRCSLZ RCLK to Active from High-Z
tRCSHZ RCLK to High-Z
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 3.5— 4 —5 —7 —ns

SKEW2 Skew time between RCLK and WCLK for PAE and PAF 4—5—6 —8—ns

t

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

4. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.

(2)

(3)

(3)

30 — 30 — 30 — 30 — ns

— 3.4 — 3.6 — 3.8 — 4.5 ns
— 3.4 — 3.6 — 3.8 — 4.5 ns

10

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS — ASYNCHRONOUS TIMING

(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)

Commercial Com’l & Ind’l Commercial

IDT72T7285L4-4 IDT72T7285L5 IDT72T7285L6-7 IDT72T7285L10

IDT72T7295L4-4 IDT72T7295L5 IDT72T7295L6-7 IDT72T7295L10
IDT72T72105L4-4 IDT72T72105L5 IDT72T72105L6-7 IDT72T72105L10
IDT72T72115L4-4 IDT72T72115L5 IDT72T72115L6-7 IDT72T72115L10

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

fA Cycle Frequency (Asynchronous) — 10 0 — 83 — 66 — 50 MHz
tAA Data Access Time 0.6 8 0.6 10 0.6 1 2 0.6 14 ns
tCYC Cycle Time 1 0 — 12 — 1 5 — 2 0 — ns
tCYH Cycle HIGH Time 4.5 — 5 — 7 — 8 — ns
tCYL Cycle LOW Time 4.5 — 5 — 7 — 8 — ns
tRPE Read Pulse after EF HIGH 8 — 10 — 12 — 1 4 — ns
tFFA Clock to Asynchronous FF —8—10—12—14ns
tEFA Clock to Asynchronous EF —8—10—12—14ns
tPAFA Clock to Asynchronous Programmable Almost-Full Flag — 8 — 1 0 — 12 — 14 ns
tPAEA Clock to Asynchronous Programmable Almost-Empty Flag — 8 — 10 — 1 2 — 14 ns
tOLZ Output Enable to Output in Low Z
tOE Output Enable to Output Valid — 3.4 — 3.6 — 3.8 — 4.5 ns
tOHZ Output Enable to Output in High Z

HF Clock to HF —8—10—12—14ns

t

(1)

(1)

0—0—0— 0—ns

— 3.4 — 3.6 — 3.8 — 4.5 ns

NOTES:

1. Values guaranteed by design, not currently tested.

2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.

11

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync

5994 drw04a

6

5

4

3

2

1

20 30 50 80 100 200

Capacitance (pF)

t

CD

(Typical, ns)

16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

HSTL

1.5V AC TEST CONDITIONS

Input Pulse Levels 0.25 to 1.25V
Input Rise/Fall Times 0.4ns
Input Timing Reference Levels 0.75
Output Reference Levels V

NOTE:

DDQ = 1.5V±.

1. V

DDQ/2

EXTENDED HSTL

1.8V AC TEST CONDITIONS

Input Pulse Levels 0.4 to 1.4V
Input Rise/Fall Times 0.4ns
Input Timing Reference Levels 0.9
Output Reference Levels V

DDQ/2

AC TEST LOADS

I/O

Figure 2a. AC Test Load

Z0 = 50

V

DDQ

/2

50

Ω

Ω

5994 drw04

NOTE:

DDQ = 1.8V±.

1. V

2.5V LVTTL

2.5V AC TEST CONDITIONS

Input Pulse Levels GND to 2.5V
Input Rise/Fall Times 1ns
Input Timing Reference Levels V
Output Reference Levels V

NOTE:

1. For LVTTL V

CC = VDDQ.

DDQ/2

Figure 2b. Lumped Capacitive Load, Typical Derating

CC/2

12

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync



 72-BIT FIFO



16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

OUTPUT ENABLE & DISABLE TIMING

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

NOTES:

1. REN is HIGH.

2. RCS is LOW.

Output

Normally

LOW

Output

Normally

HIGH

V

V

OE

CC

2

CC

2

Output

Enable

t

OE & tOLZ

100mV

100mV

Output

Disable

100mV

t

OHZ

100mV

5994 drw04b

V

IH

VIL

V

CC

2

V

OL

VOH

CC

V

2

READ CHIP SELECT ENABLE & DISABLE TIMING

t

100mV

100mV

ENH

t

RCSLZ

NOTES:

1. REN is HIGH.

2. OE is LOW.

Output

Normally

LOW

Output

Normally

HIGH

RCS

RCLK

V

V

t

ENS

CC

2

CC

2

t

100mV

100mV

RCSHZ

5994 drw04c

V

IH

VIL

V

CC

2

V

OL

VOH

CC

V

2

13

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE

The IDT72T7285/72T7295/72T72105/72T72115 support two different
timing modes of operation: IDT Standard mode or First Word Fall Through
(FWFT) mode. The selection of which mode will operate is determined during
Master Reset, by the state of the FWFT/SI input.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO. It also uses the Full Flag function (FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode, the
first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.

Various signals, both input and output signals operate differently depending

on which timing mode is in effect.

IDT STANDARD MODE

In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.

If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
the 8,193rd word for IDT72T7285, 16,385th word for IDT72T7295, 32,769th
word for IDT72T72105 and 65,537th word for IDT72T72115, respectively was
written into the FIFO. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are
performed, the PAF will go LOW after (16,384-m) writes for the IDT72T7285,
(32,768-m) writes for the IDT72T7295, (65,536-m) writes for the IDT72T72105
and (131,072-m) writes for the IDT72T72115. The offset “m” is the full offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.

When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. D = 16,384 writes for the IDT72T7285, 32,768 writes for the
IDT72T7295, 65,536 writes for the IDT72T72105 and 131,072 writes for the
IDT72T72115, respectively.

If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.

When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs.

Relevant timing diagrams for IDT Standard mode can be found in Figure
11, 12, 13 and 18.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of
Table 2. This parameter is also user programmable. See section on Program­mable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 8,194th
word for the IDT72T7285, 16,386th word for the IDT72T7295, 32,770th word
for the IDT72T72105 and 65,538th word for the IDT72T72115, respectively
was written into the FIFO. Continuing to write data into the FIFO will cause the
PAF to go LOW. Again, if no reads are performed, the PAF will go LOW
after (16,385-m) writes for the IDT72T7285, (32,769-m) writes for the
IDT72T7295, (65,537-m) writes for the IDT72T72105 and (131,073-m) writes
for the IDT72T72115, where m is the full offset value. The default setting for
these values are stated in the footnote of Table 2.

When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. D = 16,385 writes for the IDT72T7285, 32,769 writes for
the IDT72T7295, 65,537 writes for the IDT72T72105 and 131,073 writes for
the IDT72T72115, respectively. Note that the additional word in FWFT mode
is due to the capacity of the memory plus output register.

If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.

When configured in FWFT mode, the OR flag output is triple register­buffered, and the IR flag output is double register-buffered.

Relevant timing diagrams for FWFT mode can be found in Figure 14, 15,
16 and 19.

14

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72



 72-BIT FIFO



COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS

IDT72T7285,72T7295,72T72105,72T72115

*LD FSEL1 FSEL0 Offsets n,m

H L L 1,023

LH L511
L L H 255
L L L 127

LHH63
HH L31
HLH15
HH H7

*LD FSEL1 FSEL0 Program Mode

H X X Serial

L X X Parallel

*THIS PIN MUST BE HIGH AFTER MASTER RESET T O WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.

NOTES:

1. n = empty offset for PAE.

2. m = full offset for PAF.

3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.

4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.

(3)

(4)

PROGRAMMING FLAG OFFSETS

Full and Empty Flag offset values are user programmable. The IDT72T7285/
72T7295/72T72105/72T72115 have internal registers for these offsets. There
are eight default offset values selectable during Master Reset. These offset
values are shown in Table 2. Offset values can also be programmed into the
FIFO in one of two ways; serial or parallel loading method. The selection of the
loading method is done using the LD (Load) pin. During Master Reset, the state
of the LD input determines whether serial or parallel flag offset programming is
enabled. A HIGH on LD during Master Reset selects serial loading of offset
values. A LOW on LD during Master Reset selects parallel loading of offset
values.

In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.

Figure 3, Programmable Flag Offset Programming Sequence, summaries
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.

The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming has
been selected. Valid programming ranges are from 0 to D-1.

SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION

The IDT72T7285/72T7295/72T72105/72T72115 can be configured during
the Master Reset cycle with either synchronous or asynchronous timing for PAF
and PAE flags by use of the PFM pin.

If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous
PAF timing and Figure 24 for synchronous PAE timing.

If asynchronous PAF/PAE configuration is selected (PFM, LOW during

MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE

is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see
Figure 25 for asynchronous PAF timing and Figure 26 for asynchronous PAE
timing.

15

IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync



 72-BIT FIFO



16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72

TABLE 3  STATUS FLAGS FOR IDT STANDARD MODE

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T7285 IDT72T7295

0

(1)

1 to n

(n+1) to 16,384

32,768

Number of
Words in
FIFO

0

(1)

1 to n

(n+1) to 8,192

8,193 to (16,384-(m+1))

(16,384-m) to 16,383

16,384

16,385 to (32,768-(m+1))

(32,768-m) to 32,767

NOTE:

1. See table 2 for values for n, m.

TABLE 4  STATUS FLAGS FOR FWFT MODE

IDT72T7285 IDT72T7295

00 0

1 to n+1

(n+2) to 16,385

32,769 65,537 131,073

Number of
Words in
FIFO

1 to n+1

(n+2) to 8,193

8,194 to (16,385-(m+1))

(16,385-m) to 16,384

16,385

NOTE:

1. See table 2 for values for n, m.

0

16,386 to (32,769-(m+1)) 32,770 to (65,537-(m+1))

(32,769-m) to 32,768

IDT72T72105

0

(1)

1 to n

(n+1) to 32,768

32,769 to (65,536-(m+1))

(65,536-m) to 65,535

65,536

IDT72T72115

0

(1)

1 to n

(n+1) to 65,536

65,537 to (131,072-(m+1))

(131,072-m) to 131,071

131,072

IDT72T72105 IDT72T72115

1 to n+1

(n+2) to 32,769 (n+2) to 65,537

(65,537-m) to 65,536 (131,073-m) to 131,072

1 to n+1

65,538 to (131,073-(m+1))

FF PAF

HH

HH

HH

HHL HH

L

H

LL

IR PAF

LH

LH

LHHHL

LHLHL

L

L

HL

PAE EF

HF

HL L

HL

H

LHH

LHH

HF

HL H

HL

LH L

LH L

H

HH

PAE OR

L

5994 drw05

16