IDT IDT72T1845, IDT72T1855, IDT72T1865, IDT72T1875, IDT72T1885 User Manual

...

查询IDT72T18105L4-4BB供应商

2.5 VOLT HIGH-SPEED TeraSync™ FIFO 18-BIT/9-BIT CONFIGURATIONS 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9, 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9

FEATURES:

••

Choose among the following memory organizations:

•

••

IDT72T1845 IDT72T1855 IDT72T1865 IDT72T1875 IDT72T1885 IDT72T1895 IDT72T18105 IDT72T18115 IDT72T18125

••

•

Up to 225 MHz Operation of Clocks

••

User selectable HSTL/LVTTL Input and/or Output

•

••

• Read Enable & Read Clock Echo outputs aid high speed operation

••

User selectable Asynchronous read and/or write port timing

•

••

• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage

••

• 3.3V Input tolerant

••

• Mark & Retransmit, resets read pointer to user marked position

••

• Write Chip Select (WCS) input enables/disables Write operations

••

• Read Chip Select (RCS) synchronous to RCLK

••

• Programmable Almost-Empty and Almost-Full flags, each flag can

••

default to one of eight preselected offsets

••

• Program programmable flags by either serial or parallel means

••

• Selectable synchronous/asynchronous timing modes for Almost-

••



 2,048 x 18/4,096 x 9

 

 4,096 x 18/8,192 x 9

 

 8,192 x 18/16,384 x 9

 

 16,384 x 18/32,768 x 9

 

 32,768 x 18/65,536 x 9

 

 65,536 x 18/131,072 x 9

 

 131,072 x 18/262,144 x 9

 

 262,144 x 18/524,288 x 9

 

 524,288 x 18/1,048,576 x 9



IDT72T1845, IDT72T1855 IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895

IDT72T18105, IDT72T18115

IDT72T18125

Empty and Almost-Full flags

••

•

Separate SCLK input for Serial programming of flag offsets

••

•

User selectable input and output port bus-sizing

••

- x9 in to x9 out

- x9 in to x18 out

- x18 in to x9 out

- x18 in to x18 out

••

• Big-Endian/Little-Endian user selectable byte representation

••

• Auto power down minimizes standby power consumption

••

• Master Reset clears entire FIFO

••

•

Partial Reset clears data, but retains programmable settings

••

• Empty, Full and Half-Full flags signal FIFO status

••

•

Select IDT Standard timing (using EF and FF flags) or First Word

••

Fall Through timing (using OR and IR flags)

••

•

Output enable puts data outputs into high impedance state

••

• JTAG port, provided for Boundary Scan function

••

• Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm)

••

PlasticBall Grid Array (PBGA)

••

• Easily expandable in depth and width

••

• Independent Read and Write Clocks (permit reading and writing

••

simultaneously)

••

• High-performance submicron CMOS technology

••

• Industrial temperature range (–40

••

°°

°C to +85

°°

°C) is available

°°

FUNCTIONAL BLOCK DIAGRAM

D0 -D

(x18 or x9)

WEN

WCLK/WR

WCS

INPUT REGISTER

ASYW

MRS

PRS

TCK

TRST

TMS TDO

TDI

Vref

WHSTL

RHSTL SHSTL

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.

WRITE CONTROL

LOGIC

WRITE POINTER

CONTROL

LOGIC

BUS

CONFIGURATION

RESET LOGIC

JTAG CONTROL

(BOUNDARY SCAN)

HSTL I/0

CONTROL

RAM ARRAY 2,048 x 18 or 4,096 x 9 4,096 x 18 or 8,192 x 9

8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9 32,768 x 18 or 65,536 x 9

65,536 x 18 or 131,072 x 9 131,072 x 18 or 262,144 x 9 262,144 x 18 or 524,288 x 9

524,288 x 18 or 1,048,576 x 9

OUTPUT REGISTER

Q0 -Qn (x18 or x9)

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES



OFFSET REGISTER

READ POINTER

EREN

FLAG

LOGIC

READ

CONTROL

LOGIC

ERCLK

SEN

SCLK

FF/IR PAF EF/OR PAE HF

FWFT/SI PFM FSEL0 FSEL1

MARK

ASYR

RCLK/RD

REN RCS

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SEPTEMBER 2003

DSC-5909/16

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

PIN CONFIGURATIONS

A1 BALL PAD CORNER

WCS PRS LD

WCLK MRS FWFT/SI PAF

FF/IR

OW HF BE

FSEL0

SHSTL

FSEL1 DNC

ASYR

RHSTL PAE

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PFM EREN

EF/OR

MARK

RCLK

WHSTL

WEN

ASYW

SEN V

SCLK

VREF

D17

D15 D16 V

D13 D14 V

D11 D12 V

D9 D10

D7 D3 D1

D6 D4 D2 D0 TMS TD0 Q0 Q2 Q4 Q6 Q7

DDQ

GND V

GND

DDQ

GND GND V

GND GND GND GND

DDQ

TRST

GND GND V

TCK TDI ERCLK Q1 Q3 Q5 Q8

DDQ

GND

DDQVDDQ

DDQ

REN

RCS OE

Q14

DDQ

Q17

Q16

Q13

Q12 Q11

Q10 Q9

Q15

123456789101112

NOTE:

1. DNC - Do Not Connect.

5909 drw02

IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895 Only

PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)

TOP VIEW

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

2Kx18/4Kx9, 4Kx18/

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

PIN CONFIGURATIONS (CONTINUED)

A1 BALL PAD CORNER

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

CCVCC

DNC

DNC DNC DNC

SCLK

SEN

DNC DNC

WCLK

WEN

WCS

SHSTLFWFT/SI FS0

PRS

MRS

CCVCC

GND

PAF

RCLKV

MARK V

PAELD HF

IPFS1

EREN

WHSTL

ASYW

VREF

GND

GND GND

GND

REN

RCS

RHSTL

DDQVDDQ

DDQ

ASYR

DDQ

PFMDNC

GND

DNC DNC DNC

DDQ

DNC DNC

DDQ

DNC DNC DNC

DNC DNC

DNC

D16 D15

12 345678910111213141516

NOTE:

1. DNC - Do Not Connect.

D13

D14D17

GND

GND GNDGND

D5D10 D1 Q14GND Q0 Q2

D9D12

GND

TMS

TRST

TDO

TDI

TCK

GND

IDT72T18105/72T18115/72T18125 Only

PBGA: 1mm pitch, 19mm x 19mm (BB240-1, order code: BB)

TOP VIEW

GND GND

GND

ERCLK Q4 Q13Q10Q7

GND

Q5D11 D8D7 GND Q6Q1 Q9 Q12

GND

DNC DNC DNC

GND

DNC DNC DNC

GND

DNC DNC DNC

Q11Q8Q3

Q15

Q16GND

DNC DNC

DDQ

Q17

17 18

5909 drw02a

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION:

The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/ 72T18105/72T18115/72T18125 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. These FIFOs offer several key user benefits:

• Flexible x18/x9 Bus-Matching on both read and write ports

• A user selectable MARK location for retransmit

• User selectable I/O structure for HSTL or LVTTL

• Asynchronous/Synchronous translation on the read or write ports

• The first word data latency period, from the time the first word is written to an

empty FIFO to the time it can be read, is fixed and short.

• High density offerings up to 9 Mbit

Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.

Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW) and Output Width (OW) pin during the Master Reset cycle.

The input port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW).

The output port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. During Asynchronous operation only the RD input is used to read data from the FIFO. Data is read on a rising edge of RD, the REN input should be tied to its active state, LOW. When Asynchronous operation is selected on the output port the FIFO must be configured for Standard IDT mode, also the RCS should be tied LOW and the OE input used to provide three-state control of the outputs, Qn.

The output port can be selected for either 2.5V LVTTL or HSTL operation, this operation is selected by the state of the RHSTL input during a master reset.

An Output Enable (OE) input is provided for three-state control of the outputs. A Read Chip Select (RCS) input is also provided, the RCS input is synchronized to the read clock, and also provides three-state control of the Qn data outputs. When RCS is disabled, the data outputs will be high impedance. During Asynchronous operation of the output port, RCS should be enabled, held LOW.

Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are provided. These are outputs from the read port of the FIFO that are required for high speed data communication, to provide tighter synchronization between the data being transmitted from the Qn outputs and the data being received by the input device. Data read from the read port is available on the output bus with respect to EREN and ERCLK, this is very useful when data is being read at high speed. The ERCLK and EREN outputs are non-functional when the Read port is setup for Asynchronous mode.

The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other.

There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read

operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use.

For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial. Eight default offset settings are also provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and the PAF threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins.

For serial programming, SEN together with LD on each rising edge of SCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WEN together with LD on each rising edge of WCLK, are used to load the offset registers via D

n. REN together with LD on each rising edge

of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected.

During Master Reset (MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode.

The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programming method, and default or programmed offset settings existing before Partial Reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable.

It is also possible to select the timing mode of the PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAE and PAF flags.

If asynchronous PAE/PAF configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOWto-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOWto-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.

If synchronous PAE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during Master Reset by the state of the Programmable Flag Mode (PFM) pin.

This device includes a Retransmit from Mark feature that utilizes two control inputs, MARK and , RT (Retransmit). If the MARK input is enabled with respect to the RCLK, the memory location being read at that point will be marked. Any subsequent retransmit operation, RT goes LOW, will reset the read pointer to this ‘marked’ location.

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

The device can be configured with different input and output bus widths as

shown in Table 1.

A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x18) and read out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then the most significant byte (word) of the long word written into the FIFO will be read out of the FIFO first, followed by the least significant byte. If Little-Endian format is selected, then the least significant byte of the long word written into the FIFO will be read out first, followed by the most significant byte. The mode desired is configured during master reset by the state of the Big-Endian (BE) pin.

The Interspersed/Non-Interspersed Parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D

0-Dn) when

programming the flag offsets. If Interspersed Parity mode is selected, then the FIFO will assume that the parity bit is located in bit positions D

8 during the parallel

programming of the flag offsets. If Non-Interspersed Parity mode is selected, then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during Master Reset by the state of the IP input pin. This mode is relevant only when the input width is set to x18 mode.

If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply

current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state.

Both an Asynchronous Output Enable pin (OE) and Synchronous Read Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip Select is synchronized to the RCLK. Both the output enable and read chip select control the output buffer of the FIFO, causing the buffer to be either HIGH impedance or LOW impedance.

A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and Boundary Scan Architecture.

The TeraSync FIFO has the capability of operating its ports (write and/or read) in either LVTTL or HSTL mode, each ports selection independent of the other. The write port selection is made via WHSTL and the read port selection via RHSTL. An additional input SHSTL is also provided, this allows the user to select HSTL operation for other pins on the device (not associated with the write or read ports).

The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/ 72T18105/72T18115/72T18125 are fabricated using IDT’s high speed submicron CMOS technology.

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PARTIAL RESET (PRS)

WRITE CLOCK (WCLK/WR)

WRITE ENABLE (WEN)

WRITE CHIP SELECT (WCS)

LOAD (LD)

SERIAL CLOCK (SCLK)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE ALMOST-FULL (PAF)

INPUT WIDTH (IW)

MASTER RESET (MRS)

READ CLOCK (RCLK/RD) READ ENABLE (REN)

OUTPUT ENABLE (OE)

IDT 72T1845 72T1855 72T1865 72T1875 72T1885 72T1895

72T18105 72T18115 72T18125

READ CHIP SELECT (RCS)

(x18, x9) DATA OUT (Q0 - Qn)(x18, x9) DATA IN (D0 - Dn)

RCLK ECHO, ERCLK REN ECHO, EREN

MARK

RETRANSMIT (RT)

EMPTY FLAG/OUTPUT READY (EF/OR) PROGRAMMABLE ALMOST-EMPTY (PAE) HALF-FULL FLAG (HF) BIG-ENDIAN/LITTLE-ENDIAN (BE)

INTERSPERSED/ NON-INTERSPERSED PARITY (IP)

OUTPUT WIDTH (OW)

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Figure 1. Single Device Configuration Signal Flow Diagram

TABLE 1 — BUS-MATCHING CONFIGURATION MODES

I W OW Write Port Width Read Port Width

L L x18 x18

L H x18 x9 H L x9 x18 H H x9 x9

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION

Symbol Name I/O TYPE Description

(1)

ASYR

ASYW

EF/OR Empty Flag/ HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.

ERCLK RCLK Echo HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.

EREN Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.

FF/IR Full Flag/ HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is

FSEL0

FSEL1

FWFT/ First Word Fall HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin

SI Through/Serial In INPUT functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been

HF Half-Full Flag HSTL-LVTTL HF indicates whether the FIFO memory is more or less than half-full. IP IW LD Load HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,

MARK Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit

MRS Master Reset HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master

OE Output Enable HSTL-LVTTL OE provides Asynchronous three-state control of the data outputs, Q

PAE Programmable HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty

PAF Programmable HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in

PFM

Asynchronous LVTTL A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW Read Port INPUT will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.

(1)

Asynchronous LVTTL A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW Write Port INPUT will select Asynchronous operation.

(1)

Big-Endian/ LVTTL During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset Little-Endian INPUT will select Little-Endian format.

0–D17 Data Inputs HSTL-LVTTL Data inputs for an 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins should be tied to GND.

INPUT

Output Ready OUTPUT In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the

outputs.

OUTPUT

Input Ready OUTPUT full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for

writing to the FIFO memory.

(1)

Flag Select Bit 0 LVTTL During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the

INPUT programmable flags PAE and PAF. There are up to eight possible settings available.

(1)

Flag Select Bit 1 LVTTL During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the

INPUT programmable flags PAE and PAF. There are up to eight possible settings available.

selected then the FIFO must be setup in IDT Standard mode.

OUTPUT

(1)

Interspersed Parity LVTTL During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed

INPUT Parity mode.

(1)

Input Width LVTTL This pin, along with OW, selects the bus width of the write port. See Table 1 for bus size configuration.

INPUT

INPUT determines one of eight default offset values for the PAE and PAF flags, along with the method by which these

offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the offset registers. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO MEMORY.

INPUT operation will reset the read pointer to this position.

INPUT Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,

Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.

n. During a Master or Partial Reset the

INPUT OE input is the only input that provide High-Impedance control of the data outputs.

(1)

Output Width LVTTL This pin, along with IW, selects the bus width of the read port. See Table 1 for bus size configuration.

INPUT

Almost-Empty Flag OUTPUT Offset register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.

Almost-Full Flag OUTPUT the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal

to m.

(1)

Programmable LVTTL During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on Flag Mode INPUT PFM will select Synchronous Programmable flag timing mode.

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol Name I/O TYPE Description

PRS Partial Reset HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,

INPUT the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings

are all retained.

0–Q17 Data Outputs HSTL-LVTTL Data outputs for an 18- or 9-bit bus. When in 9-bit mode, any unused output pins should not be connected.

OUTPUT Outputs are not 5V tolerant regardless of the state of OE and RCS.

RCLK/ Read Clock/ HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK RD Read Strobe INPUT reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded

into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.

RCS Read Chip Select HSTL-LVTTL RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During

INPUT a Master or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance

regardless of RCS.

REN Read Enable HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enables RCLK for reading data from the

INPUT FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN

input should be tied LOW.

(1)

RHSTL RT Retransmit HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH

SCLK Serial Clock HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that

SEN Serial Enable HSTL-LVTTL SEN enables serial loading of programmable flag offsets.

SHSTL System HSTL LVTTL All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.

TCK

TDI

TDO

TMS

TRST

WEN Write Enable HSTL-LVTTL When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into

WCS Write Chip Select HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.

WCLK/ Write Clock/ HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK W R Write Strobe INPUT writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into

Read Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are Select INPUT required, this input must be tied HIGH. Otherwise it should be tied LOW.

INPUT in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode or programmable

flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to the ‘mark’ location.

INPUT SEN is enabled.

INPUT

Select INPUT

(2)

JTAG Clock HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations

INPUT of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and

outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.

(2)

JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test Input INPUT data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass

(2)

JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test Output OUTPUT data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register

and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states.

(2)

JTAG Mode HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the Select INPUT the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.

(2)

JTAG Reset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically

INPUT reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.

If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.

INPUT the FIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the

WEN input should be tied LOW.

INPUT

the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol Name I/O TYPE Description

(1)

WHSTL VCC +2.5V Supply I These are VCC supply inputs and must be connected to the 2.5V supply rail.

GND Ground Pin I These are Ground pins and must be connected to the GND rail. Vref Reference I This is a Voltage Reference input and must be connected to a voltage level determined from the table,

DDQ O/P Rail Voltage I This pin should be tied to the desired voltage rail for providing power to the output drivers.

NOTES:

1. Inputs should not change state after Master Reset.

2. These pins are for the JTAG port. Please refer to pages 29-32 and Figures 6-8.

Write Port HSTL LVTTL This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must Select INPUT be tied HIGH. Otherwise it should be tied LOW.

Voltage “Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class

inputs. If HSTL class inputs are not being used, this pin should be tied LOW.

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Commercial Unit

TERM Terminal Voltage –0.5 to +3.6

with respect to GND

STG Storage Temperature –55 to +125 °C

OUT DC Output Current –50 to +50 mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Compliant with JEDEC JESD8-5. V

CC terminal only.

(2)

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

(2,3)

Capacitance

(1,2)

OUT

Capacitance

NOTES:

1. With output deselected, (OE ≥ V

2. Characterized values, not currently tested.

IN for Vref is 20pF.

3. C

(1)

Conditions Max. Unit

Input VIN = 0V 10

Output VOUT = 0V 10 pF

IH).

RECOMMENDED DC OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

CC Supply Voltage 2.375 2.5 2.625 V

GND Supply Voltage 0 0 0 V

IH Input High Voltage  LVTTL 1.7 — 3.45 V

 eHSTL V  HSTL V

IL Input Low Voltage  LVTTL -0.3 — 0.7 V

 eHSTL -0.3 — V  HSTL -0.3 — V

(1)

REF

Voltage Reference Input  eHSTL 0.8 0.9 1.0 V

 HSTL 0.68 0.75 0.9 V

A Operating Temperature Commercial 0 — 70 °C

A Operating Temperature Industrial -40 — 85 °C

NOTE:

1. V

REF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.

2. Outputs are not 3.3V tolerant.

REF+0.2 — VDDQ+0.3 V REF+0.2 — VDDQ+0.3 V

REF-0.2 V REF-0.2 V

(3)

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)

Symbol Parameter Min. Max. Unit

LI Input Leakage Current –1 0 10 µA

ILO Output Leakage Current –1 0 10 µA

(5)

OL Output Logic “0” Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) — 0.4V V

(1,2)

ICC1

(1)

CC2

(1,2)

ICC1

(1)

CC2

NOTES:

1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.

2. For the IDT72T18105/72T18115/72T18125, typical I

For the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895, typical I

3. For all devices, typical I

4. Total Power consumed: PT = (V

5. Outputs are not 3.3V tolerant.

Output Logic “1” Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) VDDQ -0.4 — V

OH = –8 mA @V DDQ = 1.8V ± 0.1V (eHSTL) VDDQ -0.4 — V

I IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL) VDDQ -0.4 — V

OL = 8 mA @V DDQ = 1.8V ± 0.1V (eHSTL) — 0.4V V

I IOL = 8 mA @V DDQ = 1.5V ± 0.1V (HSTL) — 0.4V V

IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895

Active VCC Current (VCC = 2.5V) I/O = LVTTL — 40 mA

I/O = HSTL — 60 m A I/O = eHSTL — 60 mA

Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 10 mA

I/O = HSTL — 50 m A I/O = eHSTL — 50 mA

IDT72T18105/72T18115/72T18125

Active VCC Current (VCC = 2.5V) I/O = LVTTL — 50 mA

I/O = HSTL — 70 m A I/O = eHSTL — 70 mA

Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 20 mA

I/O = HSTL — 60 m A I/O = eHSTL — 60 mA

CC1 calculation (with data outputs in Low-Impedance):

for LVTTL I/O ICC1 (mA) = 1.0 x fs, fs = WCLK = RCLK frequency (in MHz) for HSTL or eHSTL I/O I

for LVTTL I/O ICC1 (mA) = 0.7mA x fs, fs = WCLK = RCLK frequency (in MHz) for HSTL or eHSTL I/O I

DDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz)

with data outputs in Low-Impedance: I fs = WCLK = RCLK frequency (in MHz), V N= Number of outputs switching.

CC x ICC) + VDDQ x IDDQ).

CC1 (mA) = 30 + (1.0 x fs), fs = WCLK = RCLK frequency (in MHz)

CC1 calculation (with data outputs in Low-Impedance):

CC1 (mA) = 30 + (0.7 x fs), fs = WCLK = RCLK frequency (in MHz).

DDQ (mA) = (CL x VDDQ x fs x N)/2000

DDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25°C,

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

 SYNCHRONOUS TIMING

(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)

Commercial Com’l & Ind’l

IDT72T1845L4-4 IDT72T1845L5 IDT72T1845L6-7 IDT72T1845L10 IDT72T1855L4-4 IDT72T1855L5 IDT72T1855L6-7 IDT72T1855L10 IDT72T1865L4-4 IDT72T1865L5 IDT72T1865L6-7 IDT72T1865L10 IDT72T1875L4-4 IDT72T1875L5 IDT72T1875L6-7 IDT72T1875L10 IDT72T1885L4-4 IDT72T1885L5 IDT72T1885L6-7 IDT72T1885L10

IDT72T1895L4-4 IDT72T1895L5 IDT72T1895L6-7 IDT72T1895L10 IDT72T18105L4-4 IDT72T18105L5 IDT72T18105L6-7 IDT72T18105L10 IDT72T18115L4-4 IDT72T18115L5 IDT72T18115L6-7 IDT72T18115L10 IDT72T18125L4-4 IDT72T18125L5 IDT72T18125L6-7 IDT72T18125L10

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

fC Clock Cycle Frequency (Synchronous) — 22 5 — 200 — 150 — 100 MHz tA Data Access Time 0.6 3.4 0.6 3.6 0.6 3.8 0.6 4.5 ns tCLK Clock Cycle Time 4.44 — 5 — 6.7 — 10 — ns tCLKH Clock High Time 2.0 — 2. 3 — 2.8 — 4.5 — ns tCLKL Clock Low Time 2.0 — 2. 3 — 2.8 — 4.5 — ns tDS Data Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns tDH Data Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tENS Enable Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns tENH Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tLDS Load Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns tLDH Load Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns tWCSS WCS setup time 1.2 — 1.5 — 2.0 — 3.0 — ns tWCSH WCS hold time 0.5 — 0.5 — 0. 5 — 0. 5 — ns fS Clock Cycle Frequency (SCLK) — 10 — 10 — 10 — 10 M Hz tSCLK Serial Clock Cycle 100 — 100 — 100 — 100 — ns tSCKH Serial Clock High 45 — 45 — 4 5 — 45 — ns tSCKL Serial Clock Low 45 — 45 — 4 5 — 4 5 — ns tSDS Serial Data In Setup 1 5 — 15 — 1 5 — 15 — ns tSDH Serial Data In Hold 5 — 5 — 5 — 5 — ns tSENS Serial Enable Setup 5 — 5 — 5 — 5 — ns tSENH Serial Enable Hold 5 — 5 — 5 — 5 — ns tRS Reset Pulse Width

(3)

30 — 30 — 30 — 30 — ns tRSS Reset Setup Time 15 — 15 — 15 — 15 — ns tHRSS HSTL Reset Setup Time 4 — 4 — 4 — 4 — µs tRSR Reset Recovery Time 10 — 1 0 — 1 0 — 10 — ns tRSF Reset to Flag and Output Time — 1 0 — 12 — 15 — 15 ns tWFF Write Clock to FF or IR — 3.4 — 3.6 — 3.8 — 4.5 ns tREF Read Clock to EF or OR — 3.4 — 3.6 — 3.8 — 4.5 ns tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 3.4 — 3.6 — 3.8 — 4.5 ns tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 3.4 — 3. 6 — 3. 8 — 4.5 ns tERCLK RCLK to Echo RCLK output — 3.8 — 4 — 4 .3 — 5 ns tCLKEN RCLK to Echo REN output — 3.4 — 3.6 — 3.8 — 4.5 ns tRCSLZ RCLK to Active from High-Z tRCSHZ RCLK to High-Z

(4)

— 3.4 — 3.6 — 3.8 — 4.5 ns

— 3.4 — 3.6 — 3.8 — 4.5 ns tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 3.5—4—5—7—ns

SKEW2 Skew time between RCLK and WCLK for PAE and PAF 4—5—6—8—ns

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

(2)

Commercial Commercial

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS  ASYNCHRONOUS TIMING

(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)

Commercial Com’l & Ind’l

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

fA Cycle Frequency (Asynchronous) — 100 — 83 — 66 — 50 MHz tAA Data Access Time 0.6 8 0.6 10 0 .6 12 0.6 1 4 ns tCYC Cycle Time 1 0 — 12 — 1 5 — 2 0 — ns tCYH Cycle HIGH Time 4.5 — 5 — 7 — 8 — ns tCYL Cycle LOW Time 4.5 — 5 — 7 — 8 — ns tRPE Read Pulse after EF HIGH 8 — 10 — 12 — 14 — ns tFFA Clock to Asynchronous FF —8—10—12—14ns tEFA Clock to Asynchronous EF —8—10—12—14ns tPAFA Clock to Asynchronous Programmable Almost-Full Flag — 8 — 10 — 12 — 1 4 ns tPAEA Clock to Asynchronous Programmable Almost-Empty Flag — 8 — 1 0 — 12 — 14 ns tOLZ Output Enable to Output in Low Z

(3)

0—0—0—0—ns tOE Output Enable to Output Valid — 3.4 — 3.6 — 3.8 — 4.5 ns tOHZ Output Enable to Output in High Z

HF Clock to HF —8—10—12—14ns

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.

3. Values guaranteed by design, not currently tested.

(3)

— 3.4 — 3.6 — 3.8 — 4.5 ns

(2)

Commercial Commercial

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

)

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

HSTL

1.5V AC TEST CONDITIONS

Input Pulse Levels 0.25 to 1.25V Input Rise/Fall Times 0.4ns Input Timing Reference Levels 0.75 Output Reference Levels V

NOTE:

DDQ = 1.5V±.

1. V

DDQ/2

EXTENDED HSTL

1.8V AC TEST CONDITIONS

Input Pulse Levels 0.4 to 1.4V Input Rise/Fall Times 0.4ns Input Timing Reference Levels 0.9 Output Reference Levels V

NOTE:

DDQ = 1.8V±.

1. V

DDQ/2

I/O

(Typical, ns)

AC TEST LOADS

VDDQ/2

50Ω

Z0 = 50Ω

5909 drw04

Figure 2a. AC Test Load

20 30 50 80 100 200

Capacitance (pF

5909 drw04a

2.5V LVTTL

2.5V AC TEST CONDITIONS

Input Pulse Levels GND to 2.5V Input Rise/Fall Times 1ns Input Timing Reference Levels V Output Reference Levels V

NOTE:

1. For LVTTL V

CC = VDDQ.

DDQ/2

Figure 2b. Lumped Capacitive Load, Typical Derating

CC/2

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

OUTPUT ENABLE & DISABLE TIMING

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Output

Normally

LOW

Output

Normally

HIGH

NOTES:

1. REN is HIGH.

2. RCS is LOW.

Output

Enable

OE & tOLZ

100mV

Output

Disable

100mV

OHZ

100mV

5909 drw04b

VIL

VOH

READ CHIP SELECT ENABLE & DISABLE TIMING

100mV

ENH

RCSLZ

100mV

RCSHZ

RCS

RCLK

Output

LOW

HIGH

Normally

Output

Normally

NOTES:

1. REN is HIGH.

2. OE is LOW.

ENS

5909 drw04c

VIL

VOH

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE

The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/ 72T18105/72T18115/72T18125 support two different timing modes of operation: IDT Standard mode or First Word Fall Through (FWFT) mode. The selection of which mode will operate is determined during Master Reset, by the state of the FWFT/SI input.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO. It also uses the Full Flag function (FF) to indicate whether or not the FIFO has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate whether or not the FIFO has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK.

Various signals, both input and output signals operate differently depending

on which timing mode is in effect.

IDT STANDARD MODE

In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN) must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of the Write Clock (WCLK). After the first write is performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read operations were taking place, the Half-Full flag (HF) would toggle to LOW once (D/2 + 1) words were written into the FIFO. If x18 Input or x18 Output bus Width is selected, (D/2 + 1) = the 1,025th word for the IDT72T1845, 2,049th word for IDT72T1855, 4,097th word for the IDT72T1865, 8,193rd word for the IDT72T1875, 16,385th word for the IDT72T1885, 32,769th word for the IDT72T1895, 65,537th word for the IDT72T18105, 131,073rd word for the IDT72T18115 and 262,145th word for the IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, (D/2 + 1) = the 2,049th word for the IDT72T1845, 4,097th word for IDT72T1855, 8,193rd word for the IDT72T1865, 16,385th word for the IDT72T1875, 32,769th word for the IDT72T1885, 65,537th word for the IDT72T1895, 131,073rd word for the IDT72T18105, 262,145th word for the IDT72T18115 and 524,289th word for the IDT72T18125. Continuing to write data into the FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (2,048-m) writes for the IDT72T1845, (4,096-m) writes for the IDT72T1855, (8,192-m) writes for the IDT72T1865, (16,384-m) writes for the IDT72T1875, (32,768-m) writes for the IDT72T1885, (65,536-m) writes for the IDT72T1895, (131,072-m) writes for the IDT72T18105, (262,144-m) writes for the IDT72T18115 and (524,288-m) writes for the IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, (D-m) = (4,096-m) writes for the

IDT72T1845, (8,192-m) writes for the IDT72T1855, (16,384-m) writes for the IDT72T1865, (32,768-m) writes for the IDT72T1875, (65,536-m) writes for the IDT72T1885, (131,072-m) writes for the IDT72T1895, (262,144-m) writes for the IDT72T18105, (524,288-m) writes for the IDT72T18115 and (1,048,576-m) writes for the IDT72T18125. The offset “m” is the full offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading.

When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write operations. If no reads are performed after a reset, FF will go LOW after D writes to the FIFO. If the x18 Input or x18 Output bus Width is selected, D = 2,048 writes for the IDT72T1845, 4,096 writes for the IDT72T1855, 8,192 writes for the IDT72T1865, 16,384 writes for the IDT72T1875, 32,768 writes for the IDT72T1885, 65,536 writes for the IDT72T1895, 131,072 writes for the IDT72T18105, 262,144 writes for the IDT72T18115 and 524,288 writes for the IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, D = 4,096 writes for the IDT72T1845, 8,192 writes for the IDT72T1855, 16,384 writes for the IDT72T1865, 32,768 writes for the IDT72T1875, 65,536 writes for the IDT72T1885, 131,072 writes for the IDT72T1895, 262,144 writes for the IDT72T18105, 524,288 writes for the IDT72T18115 and 1,048,576 writes for the IDT72T18125, respectively.

If the FIFO is full, the first read operation will cause FF to go HIGH. Subsequent read operations will cause PAF and HF to go HIGH at the conditions described in Table 3. If further read operations occur, without write operations, PAE will go LOW when there are n words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, the EF will go LOW inhibiting further read operations. REN is ignored when the FIFO is empty.

When configured in IDT Standard mode, the EF and FF outputs are double register-buffered outputs.

Relevant timing diagrams for IDT Standard mode can be found in Figure 11, 12, 13 and 18.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of WCLK. After the first write is performed, the Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading.

If one continued to write data into the FIFO, and we assumed no read operations were taking place, the HF would toggle to LOW once the (D/2 + 2) words were written into the FIFO. If x18 Input or x18 Output bus Width is selected, (D/2 + 2) = the 1,026th word for the IDT72T1845, 2,050th word for IDT72T1855, 4,098th word for the IDT72T1865, 8,194th word for the IDT72T1875, 16,386th word for the IDT72T1885, 32,770th word for the IDT72T1895, 65,538th word for the IDT72T18105, 131,074th word for the IDT72T18115 and 262,146th word for the IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, (D/2 + 2) = the 2,050th word for the IDT72T1845, 4,098th word for IDT72T1855, 8,194th word for the IDT72T1865, 16,386th word for the IDT72T1875, 32,770th word for the IDT72T1885, 65,538th word for the IDT72T1895, 131,074th word for the IDT72T18105, 262,146th word for the IDT72T18115 and 524,290th word for the IDT72T18125. Continuing to write data into the FIFO will cause the PAF to go LOW. Again, if no reads are performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (2,049-m) writes for the IDT72T1845,

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO

8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

2Kx18/4Kx9, 4Kx18/

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

(4,097-m) writes for the IDT72T1855, (8,193-m) writes for the IDT72T1865, (16,385-m) writes for the IDT72T1875, (32,769-m) writes for the IDT72T1885, (65,536-m) writes for the IDT72T1895, (131,073-m) writes for the IDT72T18105, (262,145-m) writes for the IDT72T18115 and (524,289-m) writes for the IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, (D-m) = (4,097-m) writes for the IDT72T1845, (8,193-m) writes for the IDT72T1855, (16,385-m) writes for the IDT72T1865, (32,769-m) writes for the IDT72T1875, (65,537-m) writes for the IDT72T1885, (131,073-m) writes for the IDT72T1895, (262,145-m) writes for the IDT72T18105, (524,289-m) writes for the IDT72T18115 and (1,048,577-m) writes for the IDT72T18125. The offset m is the full offset value. The default setting for these values are stated in the footnote of Table 2.

When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations. If no reads are performed after a reset, IR will go HIGH after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 2,049 writes for the IDT72T1845, 4,097 writes for the IDT72T1855, 8,193 writes for the IDT72T1865, 16,385 writes for the IDT72T1875, 32,769 writes for the IDT72T1885, 65,536 writes for the IDT72T1895, 131,073 writes for the IDT72T18105, 262,145 writes for the IDT72T18115 and 524,289 writes for the

TABLE 2 — DEFAULT PROGRAMMABLE FLAG OFFSETS

IDT72T1845

Offsets n,m

All Other x9 to x9

*LD FSEL1 FSEL0 Modes Mode

LHL 511 511 L L H 255 255 L L L 127 127 LHH 63 63 H L L 31 1,023 HHL 15 31 HLH 7 15 HHH 3 7

IDT72T1855, 72T1865, 72T1875, 72T1885,

72T1895, 72T18105, 72T18115, 72T18125

*LD FSEL1 FSEL0 Offsets n,m

H L L 1,023 LHL 511 L L H 255 LLL 127 LHH 63 HHL 31 HLH 15 HHH 7

*LD FSEL1 FSEL0 Program Mode

H X X Serial L X X Parallel

*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE OR READ DATA T O/FROM THE FIFO MEMORY.

NOTES:

1. n = empty offset for PAE.

2. m = full offset for PAF.

3. As well as selecting serial programming mode, one of the default values will also

be loaded depending on the state of FSEL0 & FSEL1.

4. As well as selecting parallel programming mode, one of the default values will

also be loaded depending on the state of FSEL0 & FSEL1.

(3)

(4)

IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, D = 4,097 writes for the IDT72T1845, 8,193 writes for the IDT72T1855, 16,385 writes for the IDT72T1865, 32,769 writes for the IDT72T1875, 65,537 writes for the IDT72T1885, 131,073 writes for the IDT72T1895, 262,145 writes for the IDT72T18105, 524,289 writes for the IDT72T18115 and 1,048,577 writes for the IDT72T18125, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register.

If the FIFO is full, the first read operation will cause the IR flag to go LOW. Subsequent read operations will cause the PAF and HF to go HIGH at the conditions described in Table 4. If further read operations occur, without write operations, the PAE will go LOW when there are n + 1 words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, OR will go HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.

When configured in FWFT mode, the OR flag output is triple registerbuffered, and the IR flag output is double register-buffered.

Relevant timing diagrams for FWFT mode can be found in Figure 14, 15, 16 and 19.

PROGRAMMING FLAG OFFSETS

Full and Empty Flag offset values are user programmable. The IDT72T1845/ 72T1855/72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/ 72T18125 have internal registers for these offsets. There are eight default offset values selectable during Master Reset. These offset values are shown in Table

2. Offset values can also be programmed into the FIFO in one of two ways; serial or parallel loading method. The selection of the loading method is done using the LD (Load) pin. During Master Reset, the state of the LD input determines whether serial or parallel flag offset programming is enabled. A HIGH on LD during Master Reset selects serial loading of offset values. A LOW on LD during Master Reset selects parallel loading of offset values.

In addition to loading offset values into the FIFO, it is also possible to read the current offset values. Offset values can be read via the parallel output port Q0-Qn, regardless of the programming mode selected (serial or parallel). It is not possible to read the offset values in serial fashion.

Figure 3, Programmable Flag Offset Programming Sequence, summaries the control pins and sequence for both serial and parallel programming modes. For a more detailed description, see discussion that follows.

The offset registers may be programmed (and reprogrammed) any time after Master Reset, regardless of whether serial or parallel programming has been selected. Valid programming ranges are from 0 to D-1.

SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION

The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/ 72T18105/72T18115/72T18125 can be configured during the Master Reset cycle with either synchronous or asynchronous timing for PAF and PAE flags by use of the PFM pin.

If synchronous PAF/PAE configuration is selected (PFM, HIGH during MRS), the PAF is asserted and updated on the rising edge of WCLK only and not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous PAF timing and Figure 24 for synchronous PAE timing.

If asynchronous PAF/PAE configuration is selected (PFM, LOW during

MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE

is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure 25 for asynchronous PAF timing and Figure 26 for asynchronous PAE timing.

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IDT IDT72T1845, IDT72T1855, IDT72T1865, IDT72T1875, IDT72T1885 User Manual

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