Integrated Device Technology Inc IDT72831L20PF, IDT72831L25PF, IDT72831L35PF, IDT72841L12PF, IDT72841L15PF Datasheet

Integrated Device Technology, Inc.

DUAL CMOS SyncFIFO

IDT72801
IDT72811
IDT72821
IDT72831
IDT72841

FEATURES:

• The 72801 is equivalent to two 72201 256 x 9 FIFOs

• The 72811 is equivalent to two 72211 512 x 9 FIFOs

• The 72821 is equivalent to two 72221 1024 x 9 FIFOs

• The 72831 is equivalent to two 72231 2048 x 9 FIFOs

• The 72841 is equivalent to two 72241 4096 x 9 FIFOs

• Offers optimal combination of large capacity, high speed,
design flexibility and small footprint

• Ideal for prioritization, bidirectional, and width expansion
applications

• 15 ns read/write cycle time FOR THE 72801/72811

• 20 ns read/write cycle time FOR THE 72821/72831/72841

• Separate control lines and data lines for each FIFO

• Separate empty, full, programmable almost-empty and
almost-full flags for each FIFO

• Enable puts output data lines in high-impedance state

• Space-saving 64-pin Thin Quad Flat Pack (TQFP)

• Industrial temperature range (-40

O

C to +85OC) is avail-

able, tested to military electrical specifications

DESCRIPTION:

72801/72811/72821/72831/72841 are dual synchronous

PIN CONFIGURATION

OEA

FFA

EFA

QA0

RENA2RCLKA

(clocked) FIFOs. The device is functionally equivalent to two
72201/72211/72221/72231/72241 FIFOs in a single package
with all associated control, data, and flag lines assigned to
separate pins.

Each of the two FIFOs (designated FIFO A and FIFO B)
contained in the 72801/72811/72821/72831/72841 has a 9­bit input data port (DA0 - DA8), DB0 - DB8) and a 9-bit output
data port (QA0 - QA8, QB0 - QB8). Each input port is
controlled by a free-running clock(WCLKA, WCLKB), and two
write enable pins (

WENA1

, WENA2,

WENB1

, WENB2). Data
is written into each of the two arrays on every rising clock edge
of the write clock (WCLKA WCLKB) when the appropriate
write enable pins are asserted.

The output port of each FIFO bank is controlled by its
associated clock pin (RCLKA, RCLKB) and two read enable
pins (

RENA1, RENA2, RENB1, RENB2

). The read clock can
be tied to the write clock for single clock operation or the two
clocks can run asynchronous of one another for dual clock
operation. An output enable pin (

OEA, OEB

) is provided on the

read port of each FIFO for three-state output control .

Each of the two FIFOs has two fixed flags, empty (
and full (
(

PAEA, PAEB

1

8

GND

RENA

QB

QB7

QB6

QB5

FFA, FFB

). Two programmable flags, almost-empty

) and almost-full (

QB4

QB3

QB2

QB1

PAFA, PAFB

), are provided for

EFA, EFB

)

QA1
QA2
QA3
QA4
QA5
QA6
QA7
QA8

WENA2/

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

VCC

LDA

WCLKA

WENA

RSA

DA
DA7
DA6

1

8

646362616059585756555453525150

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

171819202122232425262728293031

DA5

DA4

DA3

DA2

PN64-1

TQFP,

TOP VIEW

DA0

DA1

PAFA

PAEA

1

LDB

2/

WENB

WCLKB

WENB

RSB

8

DB

49

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

32

DB7

DB6

DB5

QB0

FFB
EFB
OEB
RENB

RCLKB

RENB

GND

CC

V

PAEB
PAFB

DB
DB1
DB2
DB3
DB4

3034 drw 01

2

1

0

COMMERCIAL TEMPERATURE RANGE NOVEMBER 1996

1996 Integrated Device Technology, Inc DSC-3034/1

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

5.15 1

72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

each FIFO bank to improve memory utilization. If not pro­grammed, the programmable flags default to empty+7 for

PAEA

and

PAEB

, and full-7 for

PAFA

and

PAFB

.

The 72801/72811/72821/72831/72841 architecture lends

itself to many flexible configurations such as:

• 2-level priority data buffering

• Bidirectional operation

• Width expansion

• Depth expansion
This FIFO is fabricated using IDTs high-performance sub-

micron CMOS technology.

FUNCTIONAL BLOCK DIAGRAM

WCLKA

WENA2

0

- DA

8

DA

WCLKB

WENB2

COMMERCIAL TEMPERATURE

0

- DB

8

DB

WRITE CONTROL

LOGIC

WRITE POINTER

RESET LOGIC

INPUT REGISTER

RAM ARRAY

256 x 9,
512 x 9, 1024 x 9,
2048 x 9, 4096 x 9

OUTPUT REGISTER

QA0 - QA

8

OFFSET REGISTER

FLAG

LOGIC

READ POINTER

READ CONTROL

LOGIC

RCLKA

WRITE CONTROL

LOGIC

WRITE POINTER

RESET LOGIC

INPUT REGISTER

RAM ARRAY

256 x 9,
512 x 9, 1024 x 9,
2048 x 9, 4096 x 9

OUTPUT REGISTER

QB0 - QB

8

OFFSET REGISTER

FLAG

LOGIC

READ POINTER

READ CONTROL

LOGIC

RCLKB

3034 drw 01A

5.15 2

72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

COMMERCIAL TEMPERATURE

PIN DESCRIPTIONS

The 72801/72811/72821/72831/72841s two FIFOs, referred
to as FIFO A and FIFO B, are identical in every respect. The
following description defines the input and output signals for

Symbol Name I/O Description

DA0-DA8 A Data Inputs I 9-bit data inputs to RAM array A.
D

B0-DB8 B Data Inputs I 9-bit data inputs to RAM array B.

RSA, RSB

WCLKA Write Clock I Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the
WCLKB write enable(s) are asserted.

WENA1
WENB1

WENA2/
WENB2/

Q
Q

LDA
LDB

A0-QA8 A Data Outputs O 9-bit data outputs from RAM array A.
B0-QB8 B Data Outputs O 9-bit data outputs from RAM array B.

RCLKA Read Clock I Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when
RCLKB (

RENA1
RENB1

RENA2
RENB2

OEA
OEB

EFA
EFB

PAEA
PAEB

PAFA
PAFB

FFA
FFB

V

CC Power +5V power supply pin.

GND Ground 0V ground pin.

Reset I When

RSA (RSB

) is set LOW, the associated internal read and write pointers of array A (B) are
set to the first location;
go LOW. After power-up, a reset of both FIFOs A and B is required before an initial WRITE.

Write Enable 1 I If FIFO A (B) is configured to have programmable flags,

enable pin that can be used. When
FIFO on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to
have two write enables,
to write data into the FIFO. Data will not be written into the FIFO if

Write Enable 2/ I FIFO A (B) is configured at reset to have either two write enables or programmable flags. If

Load

LDA (LDB

(WENB2/

) is HIGH at reset, this pin operates as a second write enable. If WENA2/

LDB

) is LOW at reset this pin operates as a control to load and read the program

mable flag offsets for its respective array. If the FIFO is configured to have two write enables,

WENA1 (WENB1

) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO
A (B). Data will not be written into FIFO A (B) if
have programmable flags,
offsets.

RENB1

) and

RENA2 (RENB2

Read Enable 1 I When

RENA1 (RENB1

LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if
(

EFB

) is LOW.

Read Enable 2 I When

RENA1 (RENB1

every LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if
the

EFA

(EFB) is LOW.

Output Enable I When

Empty Flag O When

OEA (OEB

outputs D

A0-DA8 (DB0-DB8) will be in a high-impedance state.

EFA (EFB

inhibited. When

) is LOW, outputs D

) is LOW, FIFO A (B) is empty and further data reads from the output are

EFA (EFB

RCLKA (RCLKB).

Programmable O When

PAEA (PAEB

) is LOW, FIFO A (B) is almost empty based on the offset programmed into

Almost-Empty the appropriate offset register. The default offset at reset is Empty+7.

Flag nized to RCLKA (RCLKB).

Programmable O When

PAFA (PAFB

) is LOW, FIFO A (B) is almost full based on the offset programmed into the

Almost-Full Flag appropriate offset register. The default offset at reset is Full-7.

to WCLKA (WCLKB).

Full Flag O When

When

FFA (FFB
FFA (FFB

) is LOW, FIFO A (B) is full and further data writes into the input are inhibited.
) is HIGH, FIFO A (B) is not full.

(WCLKB).

FIFO A. The corresponding signal names for FIFO B are
provided in parentheses.

FFA (FFB

WENA1 (WENB1

) and

) and

) and

PAFA (PAFB

) go HIGH, and

WENA1 (WENB1

WENA1 (WENB1

) is LOW, data A (B) is written into the

) must be LOW and WENA2 (WENB2) must be HIGH

LDA(LDB

FFA (FFB

) is held LOW to write or read the programmable flag

) is LOW. If the FIFO is configured to

) are asserted.

RENA2 (RENB2

RENA2 (RENB2

) are LOW, data is read from FIFO A (B) on every

) are LOW, data is read from the FIFO A (B) on

A0-DA8 (DB0-DB8) are active. If

) is HIGH, FIFO A (B) is not empty.

FFA (FFB

) is synchronized to WCLKA

PAEA (PAEB

FFA (FFB

OEA (OEB

EFA (EFB

PAEA (PAEB

PAFA (PAFB

) and

) is the only write

) is LOW.

) is HIGH, the

) is synchronized to

) is synchronized

EFA

LDA

RENA1

EFA

) is synchro

3034 tbl 01

(

EFB

)

5.15 3

72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

COMMERCIAL TEMPERATURE

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Unit

TERM Terminal Voltage with –0.5 to +7.0 V

V

Respect to GND

A Operating Temperature 0 to +70 °C

T

BIAS Temperature Under Bias –55 to +125 °C

T

STG Storage Temperature –55 to +125 °C

T

OUT DC Output Current 50 mA

I

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

3034 tbl 02

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.0 — — V

V

IL Input Low Voltage — — 0.8 V

V

3034 tbl 03

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter Conditions Max. Unit

(2)

C

IN
OUT

C

NOTE:

1. With output deselected (

Input Capacitance VIN = 0V 10 pF

(1,2)

Output Capacitance VOUT = 0V 10 pF

OEA, OEB

= HIGH).

IDT72801
IDT72811

3034 tbl 04

Commercial

CLK = 15, 20, 25, 35ns

t

Symbol Parameter Min. Typ. Max. Unit

(1)

LI

I
I

LO

OH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — V

V
V

OL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 V

I

CC

Input Leakage Current (Any Input) –1 — –1 µA

(2)

Output Leakage Current –10 — 10 µA

(3)

Active Power Supply Current — — 270 mA

3034 tbl 05

IDT72821
IDT72831
IDT72841

Commercial

CLK = 20, 25, 35 ns

t

Symbol Parameter Min. Typ. Max. Unit

(1)

LI

I
I

LO

OH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — V

V
V

OL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 V

I

CC

NOTES:

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2. OEA, OEB ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

3. Measurements are made with outputs open. Tested at f

Icc limits applicable when using both banks of FIFOs simultaneously.

Input Leakage Current (Any Input) –1 — –1 µA

(2)

Output Leakage Current –10 — 10 µA

(3)

Active Power Supply Current — — 300 mA

CLK = 20MHz.

3034 tbl 06

5.15 4

72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

COMMERCIAL TEMPERATURE

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)

Commercial
IDT72801L12 IDT72801L15 IDT72801L20 IDT72801L25 IDT72801L35
IDT72811L12 IDT72811L15 IDT72811L20 IDT72811L25 IDT72811L35
IDT72821L12 IDT72821L15 IDT72821L20 IDT72821L25 IDT72821L35
IDT72831L12 IDT72831L15 IDT72831L20 IDT72831L25 IDT72831L35
IDT72841L12 IDT72841L15 IDT72841L20 IDT72841L25 IDT72841L35

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

f

S Clock Cycle Frequency — 83.3 — 66.7 — 50 — 40 — 28.6 MHz

t

A Data Access Time 2 8 2 10 2 12 3 15 3 20 ns

t

CLK Clock Cycle Time 12 — 15 — 20 — 25 — 35 — ns

t

CLKH Clock High Time 5 — 6 — 8 — 10 — 14 — ns

t

CLKL Clock Low Time 5 — 6 — 8 — 10 — 14 — ns

t

DS Data Set-up Time 3 — 4 — 5 — 6 — 8 — ns

t

DH Data Hold Time 0 — 1 — 1 — 1 — 2 — ns

t

ENS Enable Set-up Time 3 — 4 — 5 — 6 — 8 — ns

t

ENH Enable Hold Time 0 — 1 — 1 — 1 — 2 — ns

t

RS Reset Pulse Width

t

RSS Reset Set-up Time 12 — 15 — 20 — 25 — 35 — ns

t

RSR Reset Recovery Time 12 — 15 — 20 — 25 — 35 — ns

t

RSF Reset to Flag Time and Output Time — 12 — 15 — 20 — 25 — 35 ns

t

OLZ Output Enable to Output in Low-Z

t

OE Output Enable to Output Valid 3 7 3 8 3 10 3 13 3 15 ns

t

OHZ Output Enable to Output in High-Z

t

WFF Write Clock to Full Flag — 8 — 10 — 12 — 15 — 20 ns

t

REF Read Clock to Empty Flag — 8 — 10 — 12 — 15 — 20 ns

t

PAF Write Clock to Programmable

Almost-Full Flag — 8 — 10 — 12 — 15 — 20 ns

t

PAE Read Clock to Programmable

Almost-Empty Flag — 8 — 10 — 12 — 15 — 20 ns

t

SKEW1 Skew Time Between Read 5 — 6 — 8 — 10 — 12 — ns

Clock and Write Clock
for Empty Flag and Full Flag

t

SKEW2 Skew Time Between Read Clock 22 — 28 — 35 — 40 — 42 — ns

and Write Clock for Programmable
Almost-Empty Flag and
Programmable Almost-Full Flag

NOTES: 3034 tbl 07

1. Pulse widths less than minimum values are not allowed.

2. Values guaranteed by design, not currently tested.

(1)

(2)

(2)

12 — 15 — 20 — 25 — 35 — ns

0— 0— 0— 0— 0—ns

3 7 3 8 310 313 315ns

5V

AC TEST CONDITIONS

In Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1

1.1K

D.U.T.

680Ω

30pF*

or equivalent circuit

3034 tbl 08

5.15 5

Figure 1. Output Load

*Includes jig and scope capacitances.

3034 drw 03

72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

COMMERCIAL TEMPERATURE

SIGNAL DESCRIPTIONS

FIFO A and FIFO B are identical in every respect. The
following description explains the interaction of input and
output signals for FIFO A. The corresponding signal names
for FIFO B are provided in parentheses.

INPUTS:

Data In (DA0 – DA8, DB0 – DB8) — DA0 - DA8 are the nine

data inputs for memory array A. DB0 - DB8 are the nine data
inputs for memory array B.

CONTROLS:

Reset (

whenever
reset, the internal read and write pointers associated with the
FIFO are set to the first location. A reset is required after
power-up before a write operation can take place. The Full
Flag
(

PAFB

(

EFB

be reset to LOW after tRSF. During reset, the output register
is initialized to all zeros and the offset registers are initialized
to their default values.

Write Clock (WCLKA, WCLKB) — A write cycle to Array
A (B) is initiated on the LOW-to-HIGH transition of WCLKA
(WCLKB). Data set-up and hold times must be met with
respect to the LOW-to-HIGH transition of WCLKA (WCLKB).
The Full Flag

PAFA (PAFB

HIGH transition of the write clock WCLKA (WCLKB).

The write and read clocks can be asynchronous or coinci­dent.

Write Enable 1 (

figured for programmable flags,
enable control pin. In this configuration, when
is LOW, data can be loaded into the input register of RAM
Array A (B) on the LOW-to-HIGH transition of every write clock
WCLKA (WCLKB). Data is stored in Array A (B) sequentially
and independently of any on-going read operation.

In this configuration, when
input register holds the previous data and no new data is
allowed to be loaded into the register.

If the FIFO is configured to have two write enables, which
allows for depth expansion. See Write Enable 2 paragraph
below for operation in this configuration.

To prevent data overflow,
further write operations. Upon the completion of a valid read
cycle, the
write to begin.
is full.

RSA

,

RSB

RSA

RSA (RSB

FFA (FFB

) will be reset to HIGH after t

) — Reset of FIFO A (B) is accomplished

RSB

) input is taken to a LOW state. During

) and Programmable Almost-Full Flag

RSF. The Empty Flag

) and Programmable Almost-Empty Flag

FFA (FFB

) and Programmable Almost-Full Flag

) are synchronized with respect to the LOW-to-

WENA1

WENA1

,

WENB1

WENB1

) — If FIFO A (B) is con-

WENA1 (WENB1

WENA1 (WENB1

FFA (FFB

) will go HIGH after t

WENA1 (WENB1

FFA (FFB

) will go LOW, inhibiting

WFF, allowing a valid

) is ignored when FIFO A (B)

PAFA

EFA

PAEA (PAEB

) will

) is the only

WENA1 (WENB1

) is HIGH, the

Read Clock (RCLKA, RCLKB) — Data can be read from
Array A (B) on the the LOW-to-HIGH transition of RCLKA
(RCLKB). The Empty Flag
Almost-Empty Flag

PAEA (PAEB

EFA (EFB

) and Programmable

) are synchronized with re-

spect to the LOW-to-HIGH transition of RCLKA (RCLKB).

The write and read clock can be asynchronous or coinci­dent.

Read Enables (

both Read Enables

RENA1

RENA1

,

RENA2

RENA2

,

RENB1

RENB1

,

RENB2

RENB2

RENA1, RENA2 (RENB1, RENB2

) — When

LOW, data is read from Array A (B) to the output register on the
LOW-to-HIGH transition of the read clock RCLKA (RCLKB).

When either of the two Read Enable
(

RENB1, RENB2

) associated with FIFO A (B) is HIGH, the

RENA1, RENA2

output register holds the previous data and no new data is
allowed to be loaded into the register.

When all the data has been read from FIFO A (B), the
Empty Flag

EFA (EFB

) will go LOW, inhibiting further read
operations. Once a valid write operation has been accom­plished,
begin. The Read Enables

EFA (EFB

) will go HIGH after t

RENA1, RENA2 (RENB1, RENB2

REF and a valid read can

are ignored when FIFO A (B) is empty.

Output Enable (

(

OEB

) is enabled (LOW), the parallel output buffers of FIFO A

OEA

OEA

,

OEB

) — When Output Enable

OEB

(B) receive data from their respective output register. When
Output Enable

OEA (OEB

) is disabled (HIGH), the QA (QB)

output data bus is in a high-impedance state.

Write Enable 2/Load (WENA2/

LDA

LDA

, WENB2/

LDB

LDB

is a dual-purpose pin. FIFO A (B) is configured at Reset to
have programmable flags or to have two write enables, which
allows depth expansion. If WENA2/
HIGH at Reset

RSA

= LOW (

RSB

LDA

(WENB2/

LDB

= LOW), this pin operates as

a second write enable pin.

If FIFO A (B) is configured to have two write enables, when
Write Enable 1
(WENB2/

WENA1 (WENB1

LDB

) is HIGH, data can be loaded into the input

) is LOW and WENA2/

register and RAM array on the LOW-to-HIGH transition of
every write clock WCLKA (WCLKB). Data is stored in the
array sequentially and independently of any on-going read

)

operation.

In this configuration, when
or WENA2/

LDA

(WENB2/

WENA1 (WENB1

LDB

) is LOW, the input register of

) is HIGH and/

Array A holds the previous data and no new data is allowed to
be loaded into the register.

To prevent data overflow, the Full Flag

FFA (FFB

LOW, inhibiting further write operations. Upon the completion
of a valid read cycle,
lowing a valid write to begin.

LDA

(WENB2/

LDB

FFA (FFB

) will go HIGH after t

WENA1

, (

WENB1

) and WENA2/

) are ignored when the FIFO is full.

FIFO A (B) is configured to have programmable flags when
the WENA2/
LOW (

LDA

(WENB2/

RSB

= LOW). Each FIFO contains four 8-bit offset

LDB

) is set LOW at Reset

registers which can be loaded with data on the inputs, or read
on the outputs. See Figure 3 for details of the size of the
registers and the default values.

) are

OEA

) — This

) is set

LDA

) will go

WFF, al-

RSA

=

)

5.15 6

72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

COMMERCIAL TEMPERATURE

LDA WENA1
LDB WENB1

0 0 Empty Offset (LSB)

WCLKA
WCLKB

(1)
(1)

OPERATION ON FIFO A
OPERATION ON FIFO B

Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)

are set LOW, data on the DA (DB) inputs are written into the
Empty (Least Significant Bit) offset register on the first LOW­to-HIGH transition of the WCLKA (WCLKB). Data are written
into the Empty (Most Significant Bit) offset register on the
second LOW-to-HIGH transition of WCLKA (WCLKB), into
the Full (Least Significant Bit) offset register on the third
transition, and into the Full (Most Significant Bit) offset register
on the fourth transition. The fifth transition of WCLKA (WCLKB)

0 1 No Operation

again writes to the Empty (Least Significant Bit) offset register.

However, writing all offset registers does not have to occur

at one time. One or two offset registers can be written and then

1 0 Write Into FIFO

by bringing
read/write operation. When

1 1 No Operation

NOTE: 3034 drw 04

1. The same selection sequence applies to reading from the registers.

RENA1

and

formed on the LOW-to-HIGH transition of RCLKA (RCLKB).

RENA2 (RENB1

Figure 2. Writing to Offset Registers for FIFOs A and B

and

RENB2

) are enabled and read is per-

WENB1

written.
(QB) outputs when WENA2/

and both Read Enables
set LOW. Data can be read on the LOW-to-HIGH transition of

) is LOW, the next offset register in sequence is

The contents of the offset registers can be read on the QA

(

the read clock RCLKA (RCLKB).

If FIFO A (B) is configured to have programmable flags,

when the

87 0

80

80

WENA1 (WENB1

72801 - 256 x 9 x 2

Empty Offset (LSB) Reg.
Default Value 007H

7

Full Offset (LSB) Reg.
Default Value 007H

) and WENA2/

LDA

(WENB2/

80

7

80

80

7

LDB

72811 - 512 x 9 x 2

Empty Offset (LSB)

Default Value 007H

Full Offset (LSB)

Default Value 007H

A read and write should not be performed simultaneously

)

to the offset registers.

1

LDA (LDB

) HIGH, FIFO A (B) is returned to normal

LDA (LDB

LDA

) is set LOW, and

(WENB2/

LDB

RENA1, RENA2 (RENB1, RENB2

72821 - 1024 x 9 x 2

87 0

Empty Offset (LSB) Reg.
Default Value 007H

80

(MSB)

0

80

7

Full Offset (LSB) Reg.
Default Value 007H

WENA1

) is set LOW

) are

1

(MSB)

00

8

72831 - 2048 x 9 x 2 72841 - 4096 x 9 x 2

87 0

Empty Offset (LSB) Reg.
Default Value 007H

8080

80

7

Full Offset (LSB) Reg.
Default Value 007H

8080

2

(MSB)

000

2

(MSB)

000

Figure 3. Offset Register Formats and Default Values for the A and B FIFOs

80

00

80

7

Empty Offset (LSB)

Default Value 007H

80

7

Full Offset (LSB)

Default Value 007H

5.15 7

1

(MSB)

0

3

(MSB)

0000

3

(MSB)

0000

80

1

3034 drw 05

(MSB)

00