Integrated Device Technology Inc IDT72815LB20BG, IDT72815LB25BG, IDT72815LB35BG, IDT72825LB20BG, IDT72825LB25BG Datasheet

Integrated Device Technology, Inc.

HFA/(WXOA

CMOS DUAL SyncFIFO
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1024 x 18

IDT72805LB
IDT72815LB
IDT72825LB

FEATURES:

• The 72805 is equivalent to two 72205LB 256 x 18
FIFOs

• The 72815 is equivalent to two 72215LB 512 x 18
FIFOs

• The 72825 is equivalent to two 72225LB 1024 x 18
FIFOs

• Offers optimal combination of large capacity (2K), high
speed, design flexibility, and small footprint

• Ideal for the following applications:

- Network switching

- Two level prioritization of parallel data

- Bidirectional data transfer

- Busmatching between 18-bit and 36-bit data paths

- Width expansion to 36-bit per package

- Depth expansion to 2048 words per package

• 20ns read/write cycle time, 12ns access time

• Read and write clocks can be asynchronous or coinci­dent (permits simultaneous reading and writing of data
on a single clock edge)

• Programmable almost-empty and almost-full flags

• Empty and Full flags signal FIFO status

• Half-Full flag capability in single device configuration

• Enable puts output data bus in high impedance state

• High-performance submicron CMOS technology

• Available in a 121-lead, 16 x 16 mm plastic Ball Grid
Array (BGA)

• Industrial temperature range (-40

o

C to +85oC) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT72805LB/72815LB/72825LB are dual 18-bit-wide
synchronous (clocked) first-in, first-out (FIFO) memories.
These devices are functionally equivalent to two IDT72205LB/
72215LB/72225LB FIFOs in a single package with all associ­ated control, data, and flag lines assigned to independent
pins. These FIFOs are applicable for a wide variety of data
buffering needs, such as optical disk controllers, local area
networks (LANs), and interprocessor communication.

Each of the two FIFOs contained in the IDT72805LB/
72815LB/72825LB has an 18-bit input data port (D0 - D17)
and an 18-bit output data port (Q0 - Q17). Each input port is
controlled by a free-running Write Clock (WCLK) and a data
input Write Enable pin (

on every rising clock edge of the appropriate Write Clock
(WCLK) when its corresponding Write Enable line (
asserted.

WEN

). Data is written into each array

WEN

) is

RSB

)

WCLKB

WENB

•

•

WRITE

CONTROL

LOGIC

WRITE

POINTER

EXPANSION

LOGIC

RESET

LOGIC

DB0-DB17

INPUT

REGISTER

ARRAY
256 x 18
512 x 18

1024 x 18

OUTPUT

REGISTER

OEB

QB

RAM

0-QB17

LDB

OFFSET

REGISTER

FFB

•

•

•

•

FLAG

LOGIC

READ

POINTER

READ

CONTROL

LOGIC

•

RCLKB

RENB

PAFB
EFB
PAEB
HFB

/

(

WXOB

)

•

3139 drw 01

FUNCTIONAL BLOCK DIAGRAM

WCLKA

WENA

•

•

WRITE

CONTROL

LOGIC

WRITE

POINTER

FLA

WXIA

RXIA

RXOA

RSA

EXPANSION

LOGIC

RESET

LOGIC

(

HFA)/WXOA

The IDT logo is a registered trademark, and SyncFIFO is a trademark of Integrated Device Technology, Inc.

DA0-DA17

REGISTER

ARRAY
256 x 18
512 x 18

1024 x 18

OUTPUT

REGISTER

OEA

INPUT

RAM

0-QA17

QA

•

•

•

•

OFFSET

REGISTER

FLAG

LOGIC

READ

POINTER

READ

CONTROL

LOGIC

•

RCLKA

•

RENA

LDA

FLB

FFA

PAFA

(

WXIB

EFA

RXIB

HFB)/WXOB

PAEA

RXOB

COMMERCIAL TEMPERATURE RANGE DECEMBER 1996

1996 Integrated Device Technology, Inc

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-839

5.17 1

DSC-3139/2

IDT72805/72815/72825 CMOS Dual SyncFIFO
256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE

DESCRIPTION (CONTINUED)

The output port of each FIFO bank is controlled by a Read
Clock pin (RCLK) and a Read Enable pin (REN). The Read
Clock can be tied to the Write Clock for single clock operation or
the two clock lines can run asynchronously to one another for
dual clock operation. An Output Enable pin (OE) is provided on
the read port of each FIFO for three-state output control.

Each of the two FIFOs has fixed flags, an Empty (EF) and a
Full (FF). Two kinds of programmable flags, an Almost-Empty
(

PAE

) and an Almost-Full (

PAF

), are provided to improve the
utilization of each FIFO memory bank. The offset loading of the
programmable flags is controlled by a simple state machine and

PIN CONFIGURATION

PIN 1

WCLKA DA3 DA1 DA0 DB13 DB16 RCLKB

A

B

C

PAFA

FFA RXIA WXIA

DA4

WENA

DA2 DB12 DB15

DA5 DB14 DB11 GND DB17 GND QB13 QB11

is initiated by asserting the load pin (LD). A Half-Full flag
(HF) is available for each FIFO that is implemented as a
single device.

The IDT72805LB/72815LB/72825LB are depth expand­able using a daisy-chain technique. A set of expansion pins
(XI and XO) are provided for each FIFO. In depth expansion
configuration, FL is grounded on the first device and set high
for all other devices in the daisy-chain.

The IDT72805LB/72815LB/72825LB is fabricated using
IDT's high speed submicron CMOS technology.

LDB RSB

RENB OEB EFB

QB17 QB16

QB15 QB14

D

E

F

G

H

J

K

L

RXOA

QA1 QA4 QA3

QA5 QA6 GND VCC GND GND GND VCC GND QB6 QB5

QA7 QA9 VCC VCC DA6 DA9

QA8 QA10 QA12 VCC DA7 DA10 DA8

QA11 QA13 GND DA17 GND DA11 DA14 DB5

QA14 QA15

QA16 QA17

QA2QA0

EFA OEA RENA

RSA LDA

FLA

WXOA/

HFA

PAEA

RCKLA DA16 DA13 DB0 DB1 DB3 WCLKB

DB9 DB6 VCC VCC QB9 QB7

PAEB

DA15 DA12 DB2

WXOB/

HFB

FLB

QB3 QB4 QB1

QB2 QB0

WXIB RXIB FFB

WENB

DB4

QB8QB10QB12VCCDB7DB10DB8

RXOB

PAFB

1234567891011

BGA
(BG 121-1)
TOP VIEW

5.17 2

3139 drw 02

IDT72805/72815/72825 CMOS Dual SyncFIFO
256 x 18-BIT, 512 x 18, and 1024 x 18

PIN DESCRIPTION

Symbol Name I/O Description

DA0–DA17 Data Inputs I Data inputs for a 18-bit bus.
DB0–DB17

RSA
RSB

WCLKA Write Clock I When
WCLKB if the FIFO is not full.

WENA
WENB

RCLKA Read Clock I When
RCLKB the FIFO is not empty.

RENA
RENB

OEA
OEB

LDA
LDB

FLA
FLB

WXIA
WXIB

RXIA
RXIB

EFA
EFB

PAEA
PAEB

PAFA
PAFB

FFA
FFB

WXOA/HFA
WXOB/HFB

RXOA
RXOB

QA0–QA17 Data Outputs O Data outputs for a 18-bit bus.
QB0–QB17

VCC Power 8 Vcc pins
GND Ground 9 GND pins

Reset I When RS is set LOW, internal read and write pointers are set to the first location of the

RAM array, FF and

PAF

an initial WRITE after power-up.

WEN

is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK,

Write Enable I When

WEN

is LOW, data is written into the FIFO on every LOW-to-HIGH transition of

WCLK. When

WEN

is HIGH, the FIFO holds the previous data. Data will not be written

into the FIFO if the FF is LOW.

REN

is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if

Read Enable I When

REN

is LOW, data is read from the FIFO on every LOW-to-HIGH transition of

RCLK. When

REN

is HIGH, the output register holds the previous data. Data will not be

read from the FIFO if the EF is LOW.

Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will

be in a high-impedance state.

Load I When LD is LOW, data on the inputs D0–D9 is written to the offset and depth registers

on the LOW-to-HIGH transition of the WCLK, when
data on the outputs Q0–Q9 is read from the offset and depth registers on the LOW-to­HIGH transition of the RCLK, when

First Load I In the single device or width expansion configuration, FL is grounded. In the depth

expansion configuration, FL is grounded on the first device (first load device) and set to
HIGH for all other devices in the daisy chain.

Write Expansion I In the single device or width expansion configuration,

Input expansion configuration,

previous device.

Read Expansion I In the single device or width expansion configuration, RXI is grounded. In the depth

Input expansion configuration,

device.

Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited.

When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.

Programmable O When

PAE

is LOW, the FIFO is almost empty based on the offset programmed into the

Almost-Empty Flag FIFO. The default offset at reset is 31 from empty for 72805LB, 63 from empty for

72815LB, and 127 from empty for 72825LB.

Programmable O When

PAF

is LOW, the FIFO is almost full based on the offset programmed into the FIFO.

Almost-Full Flag The default offset at reset is 31 from full for 72805LB, 63 from full for 72815LB, and

127 from full for 72825LB.

Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited.

When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK.

Write Expansion O In the single device or width expansion configuration, the device is more than half full

Out/Half-Full Flag when HF is LOW. In the depth expansion configuration, a pulse is sent from

WXI

of the next device when the last location in the FIFO is written.

Read Expansion O In the depth expansion configuration, a pulse is sent from

Out when the last location in the FIFO is read.

COMMERCIAL TEMPERATURE RANGE

go HIGH, and

REN

WXI

is connected to

RXI

is connected to

PAE

and EF go LOW. A reset is required before

WEN

is LOW. When LD is LOW,

is LOW.

WXI

is grounded. In the depth

WXO

(Write Expansion Out) of the

RXO

(Read Expansion Out) of the previous

RXO

to

RXI

of the next device

WXO

to

3139 tbl 01

5.17 3

IDT72805/72815/72825 CMOS Dual SyncFIFO
256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Commercial Unit

V

TERM Terminal Voltage –0.5 to +7.0 V

RECOMMENDED DC
OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

with respect to GND

CC Supply Voltage 4.5 5.0 5.5 V

T

A Operating 0 to +70 °C

Temperature

T

BIAS Temperature Under –55 to +125 °C

Bias

STG Storage –55 to +125 °C

T

Temperature

I

OUT DC Output Current 50 mA

NOTE: 3139 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT­INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maimum rating conditions for extended
periods may affect reliabilty.

V
GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.0 — — V

V

(1)

V

IL

NOTE: 3139 tbl 03

1. 1.5V undershoots are allowed for 10ns once per cycle.

Input Low Voltage — — 0.8 V

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)

IDT72805LB
IDT72815LB
IDT72825LB
Commercial

t

CLK = 20, 25, 35ns

Symbol Parameter Min. Typ. Max Unit

(1)

I

LI

(2)

LO

I

OH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — V

V

OL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 V

V

(3)

I

CC1

(3)

CC2

I

Input Leakage Current (any input) –1 — 1 µA
Output Leakage Current –10 — 10 µA

Active Power Supply Current — — 250 mA
Average Standby Current (All Input = VCC – 0.2V, — — 80 mA

except RCLK and WCLK which are free-running)

NOTES: 3139 tbl 04

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2. OE ≥ V

3. Tested at f = 20MHz with outputs unloaded. Icc limits applicable when using both banks of FIFOs simultaneously.

IH, 0.4 ≤ VOUT ≤ VCC.

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol Parameter

(2)

C

IN

Input VIN = 0V 10 pF
Capacitance

(1,2)

C

OUT

Output VOUT = 0V 10 pF
Capacitance

NOTES: 3139 tbl 05

1. With output deselected, (

2. Characterized values, not currently tested.

(1)

Conditions Max. Unit

OE

= HIGH).

5.17 4

IDT72805/72815/72825 CMOS Dual SyncFIFO
256 x 18-BIT, 512 x 18, and 1024 x 18

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)

Commercial

72805LB20 72805LB25 72805LB35
72815LB20 72815LB25 72815LB35
72825LB20 72825LB25 72825LB35

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

f

S Clock Cycle Frequency — 50 — 40 — 28.6 MHz

t

A Data Access Time 2 12 3 15 3 20 ns

t

CLK Clock Cycle Time 20 — 25 — 35 — ns

t

CLKH Clock HIGH Time 8 — 10 — 14 — ns

t

CLKL Clock LOW Time 8 — 10 — 14 — ns

t

DS Data Set-up Time 5 — 6 — 7 — ns

t

DH Data Hold Time 1 — 1 — 2 — ns

t

ENS Enable Set-up Time 5 — 6 — 7 — ns

t

ENH Enable Hold Time 1 — 1 — 2 — ns

t

RS Reset Pulse Width

t

RSS Reset Set-up Time 12 — 15 — 20 — ns

t

RSR Reset Recovery Time 12 — 15 — 20 — ns

t

RSF Reset to Flag and Output Time — 35 — 40 — 45 ns

t

OLZ Output Enable to Output in Low-Z

t

OE Output Enable to Output Valid — 9 — 12 — 15 ns

t

OHZ Output Enable to Output in High-Z

t

WFF Write Clock to Full Flag — 12 — 15 — 20 ns

t

REF Read Clock to Empty Flag — 12 — 15 — 20 ns

t

PAF Clock to Programmable Almost-Full Flag — 30 — 35 — 40 ns

t

PAE Clock to Programmable Almost-Empty Flag — 30 — 35 — 40 ns

t

HF Clock to Half-Full Flag — 30 — 35 — 40 ns

t

XO Clock to Expansion Out — 12 — 15 — 20 ns

t

XI Expansion In Pulse Width 8 — 10 — 14 — ns

t

XIS Expansion In Set-Up Time 8 — 10 — 15 — ns

t

SKEW1 Skew time between Read Clock & Write Clock for 14 — 16 — 18 — ns

Full Flag

SKEW2 Skew time between Read Clock & Write Clock for 14 — 16 — 18 — ns

t

Empty Flag

NOTES: 3139 tbl 06

1. Pulse widths less than minimum values are not allowed.

2. Values guaranteed by design, not currently tested.

(1)

(2)

(2)

20 — 25 — 35 — ns

0—0—0—ns

19112115ns

5V

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1

1.1K

D.U.T.

680

Ω

Figure 1. Output Load

3139 tbl 07

5.17 5

* Includes jig and scope capacitances.

30pF*

3139 drw 05

IDT72805/72815/72825 CMOS Dual SyncFIFO
256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE

SIGNAL DESCRIPTIONS:

INPUTS:
DATA IN (DA

Data inputs for 18-bit wide data.

CONTROLS:
RESET (

Reset is accomplished whenever the Reset (

input is taken to a LOW state. During reset, both internal read
and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (
and Programmable Almost-Full Flag (
reset to HIGH after t
Programmable Almost-Empty Flag (
reset to LOW after tRSF. During reset, the output register is
initialized to all zeros and the offset registers are initialized to
their default values.

WRITE CLOCK (WCLKA, WCLKB)

A write cycle is initiated on the LOW-to-HIGH transition of

the write clock (WCLKA, WCLKB). Data set-up and hold times
must be met with respect to the LOW-to-HIGH transition of
WCLK.

The write and read clocks can be asynchronous or

coincident.

WRITE ENABLE (

When Write Enable (

loaded into the input register and RAM array on the LOW-to­HIGH transition of every WCLK. Data is stored in the RAM
array sequentially and independently of any on-going read
operation.

When

data and no new data is loaded into the FIFO.

To prevent data overflow, FF will go LOW, inhibiting further

write operations. Upon the completion of a valid read cycle,
the FF will go HIGH after t
is ignored when the FIFO is full.

READ CLOCK (RCLKA, RCLKB)

Data can be read on the outputs on the LOW-to-HIGH

transition of the read clock (RCLKA, RCLKB), when the
Output Enable (

The write and read clocks can be asynchronous or

coincident.

0 - DA17, DB0 - DB17)

RSA

,

RSB

RSB

)

FFA, FFB

), Half-Full Flag (

RSA

PAFA, PAFB

RSF. The Empty Flag (

EFA, EFB

PAEA, PAEB

WENA

,

WENB

WENA

WENA, WENB

WEN

is HIGH, the input register holds the previous

WFF allowing a write to begin.

OEA, OEB

)

WENB

) is set LOW.

) is LOW, data can be

RSA, RSB

HFA, HFB

) will be

) and

) will be

WEN

performed, the EF will go HIGH after tREF and a read can
begin.

REN

is ignored when the FIFO is empty.

OUTPUT ENABLE (

When Output Enable (

OEA

OEA

,

OEB

)

OEB

OEA, OEB

) is enabled (LOW), the
parallel output buffers receive data from the output register.
When OE is disabled (HIGH), the Q output data bus is in a
high-impedance state.

LOAD (

)

LDA

,

LDB

LDB

)

LDA

The IDT72805LB/72815LB/72825LB devices contain two
10-bit offset registers with data on the inputs, or read on the
outputs. When the Load (

LDA, LDB

) pin is set LOW and

is set LOW, data on the inputs D0-D19 is written into the Empty

),

offset register on the first LOW-to-HIGH transition of WCLK.
When LD and

WEN

are held LOW then data is written into the
Full offset register on the second LOW-to-HIGH transition of
WCLK. The third transition of WCLK again writes to the Empty
offset register.

However, writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then
by bringing LD HIGH, the FIFO is returned to normal read/
write operation. When LD is set LOW, and

WEN

is LOW, the

next offset register in sequence is written.

When LD is LOW and

WEN

is HIGH, the WCLK input is
disabled; then a signal at this input can neither increment the
write offset register pointer, nor execute a write.

The contents of the offset registers can be read on the

output lines when LD is set LOW and

REN

is set LOW; then,
data can be read on the LOW-to-HIGH transition of RCLK. The
act of reading the control registers employs a dedicated read
offset register pointer. (The read and write pointers operate
independently).

A read and a write should not be performed simultaneously

to the offset registers.

LDA

WENA

LDA

WENA

LDB

WENB

LDB

WENB

0 0 Writing to offset registers:

0 1 No Operation

1 0 Write Into FIFO

WCLKA

WCLKA
WCLKB

WCLKB

(1)
(1)

Empty Offset
Full Offset

Selection

WEN

READ ENABLE (

When Read Enable (

RENA

RENA

RENA, RENB

,

RENB

RENB

)

) is LOW, data is loaded
into the RAM array to the output register on the LOW-to-HIGH
transition of the RCLK.

When

REN

is HIGH, the output register holds the previous

data and no new data is loaded into the register.

When all the data has been read from the FIFO, EF will go

LOW, inhibiting further read operations. Once a write is

1 1 No Operation

NOTE: 3139 tbl 08

1. The same selection sequence applies to reading from the registers.
is enabled and read is performed on the LOW-to-HIGH transition of RCLK.

Figure 2. Write Offset Register

5.17 6

REN