Integrated Device Technology Inc IDT7281L15PA, IDT7281L20PA, IDT7281L25PA, IDT7280L20PA, IDT7280L25PA Datasheet

Integrated Device Technology, Inc.

CMOS DUAL ASYNCHRONOUS FIFO
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1024 x 9

IDT7280
IDT7281
IDT7282

FEATURES:

• The 7280 is equivalent to two 7200 256x9 FIFOs

• The 7281 is equivalent to two 7201 512x9 FIFOs

• The 7282 is equivalent to two 7202 1024x9 FIFOs

• Low power consumption
— Active: 1540 mW (max.)
—Power-down: 5.50 mW (max.)

• Ultra high speed—15 ns access time

• Asynchronous and simultaneous read and write

• Offers optimal combination of data capacity, small foot
print and functional flexibility

• Ideal for bi-directional, width expansion, depth expan­sion, bus-matching, and data sorting applications

• Status Flags: Empty, Half-Full, Full

• Auto-retransmit capability

• High-performance CMOS technology

• Space-saving TSSOP

• Industrial temperature range (-40
able, tested to military electrical specifications

o

C to +85oC) is avail-

DESCRIPTION:

The IDT7280/7281/7282 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices
are functional and compatible to two 7200/7201/7202 FIFOs
kin a single package with all associated control, data, and flag
lines assigned to separate pins. The devices use Full and
Empty flags to prevent data overflow and underflow and
expansion logic to allow for unlimited expansion capability in
both word size and depth.

The reads and writes are internally sequential through the
use of ring pointers, with no address information required to
load and unload data. Data is toggled in and out of the devices
through the use of the Write (W) and Read (R) pins.

The devices utilize a 9-bit wide data array to allow for
control and parity bits at the user’s option. This feature is
especially useful in data communications applications where
it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability
that allows for reset of the read pointer to its initial position
when RT is pulsed low to allow for retransmission from the
beginning of data. A Half-Full Flag is available in the single
device mode and width expansion modes.

The IDT7280/7281/7282 are fabricated using IDT’s high­speed CMOS technology. They are designed for those appli­cations requiring asynchronous and simultaneous read/writes
in multiprocessing and rate buffer applications.

FUNCTIONAL BLOCK DIAGRAM

DATA INPUTS

(DA –DA8)

WA

RA

The IDT logo is a trademark of Integrated Device Technology, Inc.

WRITE

CONTROL

CONTROL

XIA

READ

FLAG

LOGIC

EXPANSION

LOGIC

XOA/HFA FFA EFA

WRITE

POINTER

THREE-

STATE

BUFFERS

ARRAY A

256 x 9
512 x 9

1024 x 9

OUTPUTS

(QA –QA )

0

RAM

DATA

0

POINTER

8

READ

FLA/RTA

RSA

RESET
LOGIC

RB

WB

WRITE

CONTROL

READ

CONTROL

XIB

WRITE

POINTER

FLAG

LOGIC

EXPANSION

LOGIC

XOB/HFB FFB EFB

COMMERCIAL TEMPERATURE RANGE DECEMBER 1996

1996 Integrated Device Technology, Inc. DSC-3208/3

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

5.07 1

THREE-

STATE

BUFFERS

DATA INPUTS

0

8)

(DB –DB

RAM

ARRAY B

256 x 9
512 x 9

1024 x 9

DATA

OUTPUTS

0(QB –QB 8)

READ

POINTER

RESET
LOGIC

FLB/RTB

RSB

3208 drw 01

IDT7280/7281/7282 CMOS DUAL ASYNCHRONOUS FIFO PRELIMINARY INFORMATION
DUAL 256 x 9, DUAL 512 x 9 and DUAL 1K x 9 COMMERCIAL TEMPERATURE RANGE

FFA

PIN CONFIGURATIONS

XOA/HFA

XOB/HFB

ABSOLUTE MAXIMUM RATINGS

GND

GND

(1)

1

0

QA

2

QA1

3

QA2

4

QA3

5

QA8

6
7

RA

8

4

QA

9

QA5

10

QA6

11

QA7

12
13

EFA

14

FFB

15

0

QB

16

QB1

17

QB2

18

QB3

19

QB8

20
21

RB

22

4

QB

23

QB5

24

DIP/SOIC/CERPACK

QB6

25

QB7

26
27

EFB

28

TOP VIEW

TOP VIEW

Symbol Rating Com’l. Unit

V

TERM Terminal Voltage –0.5 to +7.0 V

with Respect
to GND

T

A Operating 0 to +70 °C

Temperature

T

BIAS Temperature –55 to +125 °C

Under Bias

T

STG Storage –55 to +125 °C

Temperature

I

OUT DC Output 50 mA

Current

NOTE: 3208 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.

RECOMMENDED DC OPERATING
CONDITIONS

Symbol Parameter Min. Type Max. Unit

V

CC Supply Voltage 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V

(1)

IH

V

(2)

V

IL

NOTE: 3208 tbl 03

1. VIH = 2.6V for XI input (commercial).

2. 1.5V undershoots are allowed for 10ns once per cycle.

Intput High Voltage 2.0 — — V
Intput Low Voltage — — 0.8 V

XIA

S056-2

TSSOP

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

0

DA
DA1
DA2
DA3
DA8

WA

CC

V
DA4
DA5
DA6
DA7

FLA/RTA
RSA
XIB

0

DB
DB1
DB2
DB3
DB8

WB

CC

V
DB4
DB5
DB6
DB7

FLB/RTB
RSB

3208 drw 02

CAPACITANCE (TA = +25°C, f = 1.0 MHz)

Symbol Parameter

C

IN Input Capacitance VIN = 0V 8 pF
OUT Output Capacitance VOUT = 0V 8 pF

C

NOTE: 2679 tbl 02

1. This parameter is sampled and not 100% tested.

(1)

Condition Max. Unit

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C)

IDT7280L
IDT7281L
IDT7282L

Commercial

t

A = 15, 20, 25 ns

Symbol Parameter Min. Typ. Max. Unit

(1)

LI

I

(2)

LO

I

OH Output Logic “1” Voltage 2.4 — — V

V

OL Output Logic “0” Voltage — — 0.4 V

V

CC1

I

I

CC2

CC3(L)

I

NOTES: 3208 tbl 05

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2.R ≥ V

CC measurements are made with outputs open (only capacitive loading).

3. I

4. Tested at f = 20MHz.

Input Leakage Current –1 — 1 µA
(Any Input)

Output Leakage Current –10 — 10 µA

I

OH = –2mA

I

OL = 8mA

(3)

Active Power Supply — — 125
Current

(3)

Standby Current — — 15 mA
(R=W=RS=FL/RT=V

(3)

Power Down Current — — 0.5 mA
(All Input = V

IH, 0.4 ≤ VOUT ≤ VCC.

IH)

CC - 0.2V)

(4)

mA

5.07 2

IDT7280/7281/7282 CMOS DUAL ASYNCHRONOUS FIFO PRELIMINARY INFORMATION
DUAL 256 x 9, DUAL 512 x 9 and DUAL 1K x 9 COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C)

Commercial

7280L15 7280L20 7280L25
7281L15 7281L20 7281L25
7282L15 7282L20 7282L25

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

S Shift Frequency — 40 — 33.3 — 28.5 MHz

t

RC Read Cycle Time 25 — 30 — 35 — ns

t

A Access Time — 15 — 20 — 25 ns

t

RR Read Recovery Time 10 — 10 — 10 — ns

t

RPW Read Pulse Width

t

RLZ Read Pulse Low to Data Bus at Low Z

t

WLZ Write Pulse High to Data Bus at Low Z

t

DV Data Valid from Read Pulse High 5 — 5 — 5 — ns

t

RHZ Read Pulse High to Data Bus at High Z

t

WC Write Cycle Time 25 — 30 — 35 — ns

t

WPW Write Pulse Width

t

WR Write Recovery Time 10 — 10 — 10 — ns

t

DS Data Set-up Time 11 — 12 — 15 — ns

t

DH Data Hold Time 0 — 0 — 0 — ns

t

RSC Reset Cycle Time 25 — 30 — 35 — ns

t

RS Reset Pulse Width

t

RSS Reset Set-up Time

t

RSR Reset Recovery Time 10 — 10 — 10 — ns

t

RTC Retransmit Cycle Time 25 — 30 — 35 — ns

t

RT Retransmit Pulse Width

t

RTS Retransmit Set-up Time

t

RTR Retransmit Recovery Time 10 — 10 — 10 — ns

t

EFL Reset to Empty Flag Low — 25 — 30 — 35 ns

t

HFH,FFH Reset to Half-Full and Full Flag High — 25 — 30 — 35 ns

t

RTF Retransmit Low to Flags Valid — 25 — 30 — 35 ns

t

REF Read Low to Empty Flag Low — 15 — 20 — 25 ns

t

RFF Read High to Full Flag High — 15 — 20 — 25 ns

t

RPE Read Pulse Width after

t

WEF Write High to Empty Flag High — 15 — 20 — 25 ns

t

WFF Write Low to Full Flag Low — 15 — 20 — 25 ns

t

WHF Write Low to Half-Full Flag Low — 25 — 30 — 35 ns

t

RHF Read High to Half-Full Flag High — 25 — 30 — 35 ns

t

WPF Write Pulse Width after

t

XOL Read/Write to

t

XOH Read/Write to

t

XI

t

XIR

t

XIS

t

NOTES: 3208 tbl 06

1. Timings referenced as in AC Test Conditions. 3. Values guaranteed by design, not currently tested.

2. Pulse widths less than minimum value are not allowed. 4. Only applies to read data flow-through mode.

XI

Pulse Width

XI

Recovery Time 10 — 10 — 10 — ns

XI

Set-up Time 10 — 10 — 10 — ns

(2)

(3)

(3, 4)

(3)

(2)

(2)

(3)

(2)

(3)

EF

High 15 — 20 — 25 — ns

FF

High 15 — 20 — 25 — ns

XO

Low — 15 — 20 — 25 ns

XO

High — 15 — 20 — 25 ns

(2)

15 — 20 — 25 — ns

5 — 5—5—ns
5 — 5—5—ns

—15—15—18ns

15 — 20 — 25 — ns

15 — 20 — 25 — ns
15 — 20 — 25 — ns

15 — 20 — 25 — ns
15 — 20 — 25 — ns

15 — 20 — 25 — ns

5.07 3

IDT7280/7281/7282 CMOS DUAL ASYNCHRONOUS FIFO PRELIMINARY INFORMATION
DUAL 256 x 9, DUAL 512 x 9 and DUAL 1K x 9 COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1

3208 tbl 08

SIGNAL DESCRIPTIONS

INPUTS:

DATA IN (D0 – D8)

Data inputs for 9-bit wide data.

CONTROLS:

RESET (

taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place. Both the

Read Enable (
the high state during the window shown in Figure 2, (i.e.,
tRSS before the rising edge of
until tRSR after the rising edge of
will be reset to high after Reset (

WRITE ENABLE (

Full Flag (FF) is not set. Data set-up and hold times must be
adhered to with respect to the rising edge of the Write Enable
(W). Data is stored in the RAM array sequentially and indepen­dently of any on-going read operation.

the next write operation, the Half-Full Flag (HF) will be set to
low and will remain set until the difference between the write
pointer and read pointer is less than or equal to one half of the
total memory of the device. The Half-Full Flag (HF) is then
reset by the rising edge of the read operation.

inhibiting further write operations. Upon the completion of a
valid read operation, the Full Flag (FF) will go high after t
allowing a valid write to begin. When the FIFO is full, the
internal write pointer is blocked from W, so external changes
in W will not affect the FIFO when it is full.

READ ENABLE (

Enable (R) provided the Empty Flag (EF) is not set. The data
is accessed on a First-In/First-Out basis, independent of any
ongoing write operations. After Read Enable (R) goes high,

RSRS)

Reset is accomplished whenever the Reset (RS) input is

RR) and Write Enable (

WW) inputs must be in

RSRS) and should not change

RSRS. Half-Full Flag (

HFHF)

RSRS).

WW)

A write cycle is initiated on the falling edge of this input if the

After half of the memory is filled and at the falling edge of

To prevent data overflow, the Full Flag (FF) will go low,

RFF,

RR)

A read cycle is initiated on the falling edge of the Read

5V

1.1K

TO

OUTPUT

PIN

680Ω

or equivalent circuit

Figure 1. Output Load

* Includes scope and jig capacitances.

30pF*

3208 drw 03

the Data Outputs (Q0 – Q8) will return to a high impedance
condition until the next Read operation. When all data has
been read from the FIFO, the Empty Flag (EF) will go low,
allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high imped­ance state. Once a valid write operation has been accom­plished, the Empty Flag (EF) will go high after tWEF and a valid
Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from R so external changes in R will not
affect the FIFO when it is empty.

FIRST LOAD/RETRANSMIT (

FLFL/

RTRT)

This is a dual-purpose input. In the Depth Expansion
Mode, this pin is grounded to indicate that it is the first loaded
(see Operating Modes). In the Single Device Mode, this pin
acts as the restransmit input. The Single Device Mode is
initiated by grounding the Expansion In (XI).

The IDT7280/7281/7282 can be made to retransmit data
when the Retransmit Enable control (RT) input is pulsed low.
A retransmit operation will set the internal read pointer to the
first location and will not affect the write pointer. Read Enable
(R) and Write Enable (W) must be in the high state during
retransmit. This feature is useful when less than 256/512/
1024 writes are performed between resets. The retransmit
feature is not compatible with the Depth Expansion Mode and
will affect the Half-Full Flag (HF), depending on the relative
locations of the read and write pointers.

EXPANSION IN (

XIXI)

This input is a dual-purpose pin. Expansion In (XI) is
grounded to indicate an operation in the single device mode.
Expansion In (XI) is connected to Expansion Out (XO) of the
previous device in the Depth Expansion or Daisy Chain Mode.

OUTPUTS:

FULL FLAG (

The Full Flag (FF) will go low, inhibiting further write
operation, when the write pointer is one location less than the
read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (RS), the Full-Flag (FF) will go
low after 256 writes for IDT7280, 512 writes for the IDT7281
and 1024 writes for the IDT7282.

FFFF)

5.07 4