Integrated Device Technology Inc IDT72615L20G, IDT72615L20J, IDT72615L20PF, IDT72615L25G, IDT72615L25PF Datasheet
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Integrated Device Technology, Inc.
CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
IDT72605
IDT72615
FEATURES:
• Two independent FIFO memories for fully bidirectional
data transfers
• 256 x 18 x 2 organization (IDT 72605)
• 512 x 18 x 2 organization (IDT 72615)
• Synchronous interface for fast (20ns) read and write
cycle times
• Each data port has an independent clock and read/write
control
• Output enable is provided on each port as a three-state
control of the data bus
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• The synchronous BiFIFO is packaged in a 64-pin TQFP
(Thin Quad Flatpack), 68-pin PGA and 68-pin PLCC
• Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, lowpower bidirectional First-In, First-Out (FIFO) memories, with
synchronous interface for fast read and write cycle times. The
SyncBiFIFO is a data buffer that can store or retrieve
information from two sources simultaneously. Two Dual-Port
FIFO memory arrays are contained in the SyncBiFIFO; one
data buffer for each direction.
The SyncBiFIFO has registers on all inputs and outputs.
Data is only transferred into the I/O registers on clock edges,
hence the interfaces are synchronous. Each Port has its own
independent clock. Data transfers to the I/O registers are
gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal. Individual output enable signals control whether the SyncBiFIFO is
driving the data lines of a port or whether those data lines are
in a high-impedance state.
Bypass control allows data to be directly transferred from
input to output register in either direction.
The SyncBiFIFO has eight flags. The flag pins are full,
empty, almost-full, and almost-empty for both FIFO memories. The offset depths of the almost-full and almost-empty
flags can be programmed to any location.
The SyncBiFIFO is fabricated using IDT’s high-speed,
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
DA0-DA17
EN
A
R/
W
A
OE
A
CS
A
A2
A1
A0
EF
AB
PAE
AB
PAF
AB
FF
AB
CLKB
OE
B
R/
W
B
EN
B
SyncBiFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES DECEMBER 1996
1996 Integrated Device Technology, Inc. DSC-2704/5
HIGH
Z
CONTROL
CLKA
µP
INTERFACE
FLAG
LOGIC
HIGH
Z
CONTROL
INPUT REGISTER
MEMORY
ARRAY
512 x 18
256 x 18
MUX
OUTPUT REGISTER INPUT REGISTER
BYP
B
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DB0-DB17
OUTPUT REGISTER
MUX
MEMORY
ARRAY
512 x 18
256 x 18
5.18 1
RESET
LOGIC
FLAG
LOGIC
POWER
SUPPLY
3
7
2704 drw 01
RS
BA
EF
PAE
PAF
FF
BA
VCC
GND
BA
BA
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2 COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
11
D
B1
10
RS
09
CLK
R/
W
08
07
06
05
04
03
02
B
OE
B
GND A2V
BYP
PAF
PAE
BA
EF
BA
D
A1
D
A2DA3
01
ABCDEF
D
B3
D
B2
D
B0
B
EN
B
B
BA
FF
BA
D
A0
D
A4DA5
D
B4DB5
GND
GND
D
B7
D
B6
D
B8
Pin 1 Designator
D
A6
D
A8
D
A7
D
A9
Top View
D
D
B9
GND
V
D
CC
B10
B11
D
B13
D
B12
D
B14
G68-1
GND D
V
CC
PGA
D
A10
D
A11
G
D
A12
D
A14
GND
D
A13
HJKL
GND
D
OE
PAE
EF
A
EN
CLK
D
B15
A
AB
AB
0
A
A
A16
A15
D
B16
D
B17
PAF
AB
AB
FF
CC
A
1
CS
A
R/
W
A
D
A17
2704 drw 02
DA16
D
A17
CLK
R/WA
EN
CSA
A0
A 1
A2
VCC
EFAB
AB
FF
PAEAB
AB
PAF
OEA
DB17
DB16
A15
GND
D
DA14
DA13
10
11
12
A
13
A
14
15
16
17
18
19
20
21
22
23
24
25
26
A12DA11
D
A10
D
23456789
A9
VCCGND
1
J68-1
DA5DA6DA7DA8D
GND
A3DA4
D
6162636465666768
A2
D
60
DA1
59
DA0
58
EFBA
57
FFBA
56
PAEBA
55
PAFBA
54
GND
53
52
BYPB
51
OEB
50
ENB
B
R/W
49
CLKB
48
RS
47
DB0
46
D
45
44
B1
DB2
35 43424140393837363433323130292827
B9
B15
D
B14
D
GND
B13
D
B12
D
B11
D
B10
D
VCC
GND
PLCC
Top View
B8DB7DB6
D
D
B5DB4DB3
D
GND
2704 drw 03
5.18 2
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2 COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
PIN 1
BA
PAE
BA
PAF
BA
DA1
DA0
EF
BA
FF
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND
B
BYB
BENB
OE
B
W
R/
0
DB1
DB
RS
CLKB
DB2
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
GND
VCC
DA
DA11
DA12
DA13
DA14
DA15
1
2
3
4
5
6
7
8
PN64-1
9
10
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DB3
DB4
GND
DB
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
GND
DB
DB16
5
15
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A
W
DA16
DA17
R/
CLKA
A
A
EN
A0
A1
CS
TQFP
Top View
5.18 3
A2
VCC
AB
EFABFF
PAEABPAF
AB
A
OE
DB17
2704 drw 04
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2 COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol Name I/O Description
A0-DA17 Data A I/O Data inputs & outputs for the 18-bit Port A bus.
D
CS
A Chip Select A I Port A is accessed when CSA is LOW. Port A is inactive if CSA is HIGH.
A Read/Write A I This pin controls the read or write direction of Port A. If R/WA is LOW, Data A input data is
R/
W
written into Port A. If R/
when R/
W
A is LOW, message is written into A→B output register. If R/WA is HIGH, message
is read from B→A output register.
CLK
A Clock A I CLKA is typically a free running clock. Data is read or written into Port A on the rising edge of
CLK
A.
A Enable A I When ENA is LOW, data can be read or written to Port A. When ENA is HIGH, no data
EN
transfers occur.
OE
A Output Enable A I When R/WA is HIGH , Port A is an output bus and OEA controls the high-impedance state of
D
A0-DA17. If OEA is HIGH, Port A is in a high-impedance state. If OEA is LOW while CSA is
LOW and R/
A
0, A1, A2 Addresses I When CSA is asserted, A0, A1, A2 and R/WA are used to select one of six internal resources.
B0-DB17 Data B I/O Data inputs & outputs for the 18-bit Port B bus.
D
B Read/Write B I This pin controls the read or write direction of Port B. If R/WB is LOW, Data B input data is
R/
W
W
A is HIGH, Port A is in an active (low-impedance) state.
written into Port B. If R/
when R/
W
B is LOW, message is written into B→A output register. If R/WB is HIGH, message
is read from A→B output register.
CLK
B Clock B I Clock B is typically a free running clock. Data is read or written into Port B on the rising edge
of CLK
B.
EN
B Enable B I When ENB is LOW, data can be read or written to Port B. When ENB is HIGH, no data
transfers occur.
OE
B Output Enable B I When R/WB is HIGH , Port B is an output bus and OEB controls the high-impedance state of
D
B0-DB17. If OEB is HIGH, Port B is in a high-impedance state. If OEB is LOW while R/WB
is HIGH, Port B is in an active (low-impedance) state.
AB A→B Empty Flag O When EFAB is LOW, the A→B FIFO is empty and further data reads from Port B are inhibited.
EF
When
EF
AB is HIGH, the FIFO is not empty. EFAB is synchronized to CLKB. In the bypass
mode,
EF
AB HIGH indicates that data DA0-DA17 is available for passing through. After the
data D
B0-DB17 has been read, EFAB goes LOW.
PAE
AB A→B O When
PAE
AB is LOW, the A→B FIFO is almost empty. An almost empty FIFO contains less
Programmable than or equal to the offset programmed into
Almost-Empty Flag A→B FIFO contains more than offset in
PAF
AB A→B O When
Register is 8.
PAF
PAE
AB is LOW, the A→B FIFO is almost full. An almost full FIFO contains greater than
Programmable the FIFO depth minus the offset programmed into
Almost-Full Flag the A→B FIFO contains less than or equal to the depth minus the offset in PAF
The default offset value for PAF
AB A→B Full Flag O When FFAB is LOW, the A→B FIFO is full and further data writes into Port A are inhibited.
FF
When
FF
AB is HIGH, the FIFO is not full. FFAB is synchronized to CLKA. In bypass mode,
FF
AB tells Port A that a message is waiting in Port B’s output register. If FFAB is LOW, a
bypass message is in the register. If
message can be written into Port A.
EF
BA B→A Empty Flag O When EFBA is LOW, the B→A FIFO is empty and further data reads from Port A are inhibited.
When
EF
BA is HIGH, the FIFO is not empty. EFBA is synchronized to CLKA. In the bypass
mode,
EF
BA HIGH indicates that data DB0-DB17 is available for passing through. After the
data D
A0-DA17 has been read, EFBA goes LOW on the following cycle.
BA B→A O When
PAE
PAE
BA is LOW, the B→A FIFO is almost empty. An almost empty FIFO contains less
Programmable than or equal to the offset programmed into
Almost-Empty Flag B→A FIFO contains more than offset in
BA B→A O When
PAF
Register is 8.
PAF
PAE
BA is LOW, the B→A FIFO is almost full. An almost full FIFO contains greater than
Programmable the FIFO depth minus the offset programmed into
Almost-Full Flag the B→A FIFO contains less than or equal to the depth minus the offset in
The default offset value for
W
A is HIGH, Data A output data is read from Port A. In bypass mode,
W
B is HIGH, Data B output data is read from Port B. In bypass mode,
PAE
PAE
AB Register. The default offset value for
AB is synchronized to CLKB.
AB Register is 8.
FF
AB is HIGH, Port B has read the message and another
PAE
PAE
BA Register. The default offset value for
BA is synchronized to CLKA.
AB Register. When
PAF
AB Register. When PAFAB is HIGH,
PAF
AB is synchronized to CLKA.
BA Register. When
PAF
BA Register. When
PAE
AB is HIGH, the
PAE
BA is HIGH, the
PAF
PAF
PAF
BA Register is 8.
PAF
BA is synchronized to CLKB.
PAE
AB Register.
PAE
BA is HIGH,
BA Register.
2704 tbl 01
AB
BA
5.18 4
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2 COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (Continued)
Symbol Name I/O Description
FF
BA B→A Full Flag O When FFBA is LOW, the B→A FIFO is full and further data writes into Port B are inhibited.
When
FF
BA is HIGH, the FIFO is not full. FFBA is synchronized to CLKB. In bypass mode,
FF
BA tells Port B that a message is waiting in Port A’s output register. If FFBA is LOW, a
bypass message is in the register. If
FF
BA is HIGH, Port A has read the message and another
message can be written into Port B.
BYP
B Port B Bypass O This flag informs Port B that the Synchronous BiFIFO is in bypass mode. When BYPB is
Flag LOW, Port A has placed the FIFO into bypass mode. If
BiFIFO passes data into memory.
RS
CC Power There are three +5V power pins for the PLCC and PGA packages and two for the TQFP.
V
Reset I A LOW on this pin will perform a reset of all Synchronous BiFIFO functions.
BYP
B is synchronized to CLKB.
BYP
B is HIGH, the Synchronous
GND Ground There are seven ground pins for the PLCC and PGA packages and four for the TQFP.
2704 tbl 02
RECOMMENDED DC
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Rating Com’l. Mil. Unit
TERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
V
with Respect
to Ground
T
A Operating 0 to +70 –55 to +125 °C
Temperature
T
BIAS Temperature –55 to +125 –65 to +135 °C
Under Bias
STG Storage –55 to +125 –65 to +150 °C
T
Temperature
I
OUT DC Output Current 50 50 mA
NOTE: 2704 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
V
CC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
V
IH Input High Voltage 2.0 — — V
(1)
V
IL
NOTE: 2704 tbl 04
1. 1.5V undershoots are allowed for 10ns once per cycle.
Input Low Voltage — — 0.8 V
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol Parameter Conditions Max. Unit
(2)
C
IN
C
OUT
NOTES:
1. With output deselected.
2. Characterized values, not currently tested.
Input Capacitance VIN = 0V 10 pF
(1,2)
Output Capacitance VOUT = 0V 10 pF
2704 tbl 05
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
IDT72615L
IDT72605L
Commercial
t
CLK = 20, 25, 35, 50ns
Symbol Parameter Min. Typ. Max. Unit
(1)
I
IL
OL
I
OH Output Logic "1" Voltage IOUT = –2mA 2.4 — — V
V
OL Output Logic "0" Voltage IOUT = 8mA — — 0.4 V
V
I
CC
NOTES:
1. Measurements with 0.4V ≤ V
2.
OEA, OEB
3. Tested with outputs open. Testing frequency f=20MHz
Input Leakage Current (Any Input) –1 — 1 µA
(2)
Output Leakage Current –10 — 10 µA
(3)
Average VCC Power Supply Current — — 230 mA
IH; 0.4 ≤ VOUT ≤ VCC.
≥ V
IN ≤ VCC.
5.18 5
2704 tbl 06
IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2 COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
+5V
In Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
1.1KΩ
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 2
2704 tbl 07
AC ELECTRICAL CHARACTERISTICS
D.U.T.
680Ω
or equivalent circuit
Figure 2. Output Load
* Includes jig and scope capacitances.
30pF*
2704 drw 05
(Commercial: VCC = 5V±10%, TA = 0°C to +70°C)
Commercial
72615L20 72615L25 72615L35 72615L50
72605L20 72605L25 72605L35 72605L50
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit Timing Figures
f
CLK Clock frequency — 50 — 40 — 28 — 20 MHz —
CLK Clock cycle time 20 — 25 — 35 — 50 — ns 4,5,6,7
t
CLKH Clock HIGH time 8 — 10 — 14 — 20 — ns 4,5,6,7,12,13,14,15
t
CLKL Clock LOW time 8 — 10 — 14 — 20 — ns 4,5,6,7,12,13,14,15
t
RS Reset pulse width 20 — 25 — 35 — 50 — ns 3
t
RSS Reset set-up time 12 — 15 — 21 — 30 — ns 3
t
RSR Reset recovery time 12 — 15 — 21 — 30 — ns 3
t
RSF Reset to flags in intial state — 27 — 28 — 35 — 50 ns 3
t
A Data access time 3 10 3 15 3 21 3 25 ns 5,7,8,9,10,11
t
CS Control signal set-up time
t
CH Control signal hold time
t
t
DS Data set-up time 6 — 6 — 8 — 10 — ns 4,6,8,9,10,11
DH Data hold time 1 — 1 — 1 — 1 — ns 4,6
t
OE Output Enable LOW to 3 10 3 13 3 20 3 28 ns 5,7,8,9,10,11
t
output data valid
tOLZ Output Enable LOW to data 0 — 0 — 0 — 0 — ns 5,7,8,9,10,11
bus at Low-Z
tOHZ Output Enable HIGH to data 3 10 3 13 3 20 3 28 ns 5,7,10,11
bus at High-Z
(2)
(2)
(2)
tFF Clock to Full Flag time — 10 — 15 — 21 — 30 ns 4,6,10,11
EF Clock to Empty Flag time — 10 — 15 — 21 — 30 ns 5,7,8,9,10,11
t
PAE Clock to Programmable — 12 — 15 — 21 — 30 ns 12,14
t
Almost Empty Flag time
PAF Clock to Programmable — 12 — 15 — 21 — 30 ns 13,15
t
Almost Full Flag time
t
SKEW1 Skew between CLKA & CLKB 10 — 12 — 17 — 20 — ns 4,5,6,7,8,9,10,11
for Empty/Full Flags
tSKEW2 Skew between CLKA & CLKB 17 — 19 — 25 — 34 — ns 4, 7,12,13,14,15
for Programmable Flags
NOTES:
1. Control signals refer to
2. Minimum values are guaranteed by design.
A, R/WA, ENA, A2, A1, A0, R/WB, ENB.
CS
(1)
6 — 6 — 8 — 10 — ns 4,5,6,7,8,9,10,11,
12, 13,14,15
(1)
1 — 1 — 1 — 1 — ns 4,5,6,7,10,11,12,
13, 14,15
(2)
(2)
2704 tbl 08
5.18 6
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