IDT IDT72605, IDT72615 User Manual

CMOS SyncBiFIFO
256 x 18 x 2
512 x 18 x 2

TM

IDT72605
IDT72615

FEATURES:

••

•

Two independent FIFO memories for fully bidirectional data

••

transfers

••

256 x 18 x 2 organization (IDT72605)

•

••

••

• 512 x 18 x 2 organization (IDT72615)

••

••

• Synchronous interface for fast (20ns) read and write cycle times

••

••

• Each data port has an independent clock and read/write control

••

••

• Output enable is provided on each port as a three-state control

••

of the data bus

••

Built-in bypass path for direct data transfer between two ports

•

••

••

• Two fixed flags, Empty and Full, for both the A-to-B and the B-

••

to-A FIFO

••

• Programmable flag offset can be set to any depth in the FIFO

••

••

• The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin

••

Quad Flatpack) and 68-pin PLCC

••

• Industrial temperature range (–40

••

°°

°C to +85

°°

°°

°C)

°°

DESCRIPTION:

The IDT72605 and IDT72615 are very high-speed, low-power bidirec-

tional First-In, First-Out (FIFO) memories, with synchronous interface for fast

FUNCTIONAL BLOCK DIAGRAM

read and write cycle times. The SyncBiFIFO™ is a data buffer that can store
or retrieve information from two sources simultaneously. Two Dual-Port FIFO
memory arrays are contained in the SyncBiFIFO; one data buffer for each
direction.

The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. Each Port has its own independent clock. Data transfers to the
I/O registers are gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal. Individual output enable
signals control whether the SyncBiFIFO is driving the data lines of a port or
whether those data lines are in a high-impedance state.

Bypass control allows data to be directly transferred from input to output
register in either direction.

The SyncBiFIFO has eight flags. The flag pins are Full, Empty, Almost-Full,
and Almost-Empty for both FIFO memories. The offset depths of the Almost-Full
and Almost-Empty flags can be programmed to any location.

The SyncBiFIFO is fabricated using IDT’s high-speed, submicron CMOS
technology.

DA0-D

A17

EN

R/W

OE

CS

EF
PAE
PAF

FF

CLK

OE

R/W

EN

A
A
A

HIGH

Z

CONTROL

CLK

A

A

A

2

A

1

A

0

AB
AB
AB
AB

µP

INTERFACE

FLAG

LOGIC

INPUT REGISTER

MEMORY

ARRAY
512 x 18
256 x 18

MUX

B

B

B

B

HIGH

Z

CONTROL

BYP

OUTPUT REGISTER INPUT REGISTER

B

DB0-D

OUTPUT REGISTER

MUX

MEMORY

512 x 18
256 x 18

B17

ARRAY

RESET

LOGIC

FLAG

LOGIC

POWER

SUPPLY

RS

EF
PAE
PAF
FF

3

V

7

GND

2704 drw 01

BA

BA
BA

BA

CC

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

APRIL 2003

1

2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2704/7

IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2

PIN CONFIGURATIONS

INDUSTRIAL TEMPERATURE RANGE

D
C

CLK
R/W

EN
CS

EF

FF
PAE
PAF

OE

D
D

V

A16

A17

A
A
A

CC

AB

AB

AB

AB

B17

B16

A15

A14DA13DA12DA11DA10

D

GND

D

10

VCCGND

DA9DA8DA7DA6DA5GND

23456789

1

11

A

12

A

13

A

14

A

15

0

16

1

17

2

18
19
20
21
22
23

A

24
25
26

DA4D

6162636465666768

A3

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

D

A2

D

A1

D

A0

EF
FF
PAE
PAF

GND

BYP
OE
EN

R/W
CLK

RS

B0

D
D

B1

D

B2

BA

BA

BA

BA

B

B

B

B

B

35 43424140393837363433323130292827

B15

B14DB13DB12DB11DB10

D

D

GND

CC

V

GND

B9DB8DB7DB6DB5

D

GND

B4DB3

D

2704 drw 02

PLCC (J68-1, order code: J)

TOP VIEW

PIN 1

D

A2

D

A3

D

A4

D

A5

D

A6

D

A7

D

A8

D

A9

GND

CC

V

D

A10

D

A11

D

A12

D

A13

D

A14

D

A15

DA1DA0EFBAFFBAPAEBAPAFBAGND

BYBBOEBENBR/WBCLKBRS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

A16DA17

D

A

CLK

AENACSA

R/W

A0A1A

2

CC

V

AB

EF

AB

FF

TQFP (PN64-1, order code: PF)

TOP VIEW

AB

PAE

DB0DB1D

A

AB

OE

PAF

B2

B17

D

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

2704 drw 03

D

B3

D

B4

GND

B5

D
D

B6

D

B7

D

B8

D

B9

D

B10

D

B11

D

B12

D

B13

D

B14

GND

B15

D
D

B16

2

IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE

PIN DESCRIPTION

Symbol Name I/O Description

D

A0-DA17 Data A I/O Data inputs & outputs for the 18-bit Port A bus.

A Chip Select A I Port A is accessed when CSA is LOW. Port A is inactive if CSA is HIGH.

CS

A Read/Write A I

R/W

CLKA Clock A I CLKA is typically a free running clock. Data is read or written into Port A on the rising edge of CLKA.

A Enable A I

EN
OEA

0, A1, A2 Addresses I When CSA is asserted, A0, A1, A2 and R/WA are used to select one of six internal resources.

A

B0-DB17 Data B I/O Data inputs & outputs for the 18-bit Port B bus.

D
R/W

Output Enable A

B Read/Write B I

CLKB Clock B I

ENB Enable B I
OEB

EF

Output Enable B

AB A→B Empty O When EFAB is LOW, the A→B FIFO is empty and further data reads from Port B are inhibited. When EFAB is HIGH, the FIFO is

Flag not empty. EF

AB A→B O When PAEAB is LOW, the A→B FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset

PAE

Programmable programmed into PAE
Almost-Empty default offset value for PAE
Flag

AB A→B O When PAFAB is LOW, the A→B FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset

PAF

Programmable programmed into PAF
Almost-Full offset in PAF
Flag

AB A→B Full Flag O

FF

EFBA B→A Empty O When EFBA is LOW, the B→A FIFO is empty and further data reads from Port A are inhibited. When EFBA is HIGH, the FIFO

Flag is not empty. EF

BA B→A O When PAEBA is LOW, the B→A FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset

PAE

Programmable programmed into PAE
Almost-Empty default offset value for PAE
Flag

BA B→A O When PAFBA is LOW, the B→A FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset

PAF

Programmable programmed into PAF
Almost-Full offset in PAF
Flag

BA B→A Full Flag O

FF

BYPB Port B Bypass O

Flag bypass mode. If BYP

RS Reset I A LOW on this pin will perform a reset of all synchronous BiFIFO functions.

CC Power There are three +5V power pins for the PLCC and two for the TQFP.

V
GND Ground There are seven ground pins for the PLCC and four for the TQFP.

This pin controls the read or write direction of Port A. If R/WA is LOW, Data A input data is written into Port A. If R/WA is HIGH,

A

Data A output data is read from Port A. In bypass mode, when R/W

A

is HIGH, message is read from B→A output register.

R/W

is LOW, message is written into A→B output register. If

When ENA is LOW, data can be read or written to Port A. When ENA is HIGH, no data transfers occur.

I When R/WA is HIGH, Port A is an output bus and OEA controls the high-impedance state of DA0-DA17. If OEA is HIGH, Port A is

in a high-impedance state. If OE

A is LOW while CSA is LOW and R/WA is HIGH, Port A is in an active (low-impedance) state.

This pin controls the read or write direction of Port B. If R/WB is LOW, Data B input data is written into Port B. If R/WB is HIGH,

B

Data B output data is read from Port B. In bypass mode, when R/W

B

is HIGH, message is read from A→B output register.

R/W

is LOW, message is written into B→A output register. If

Clock B is typically a free running clock. Data is read or written into Port B on the rising edge of CLKB.
When ENB is LOW, data can be read or written to Port B. When ENB is HIGH, no data transfers occur.

I When R/WB is HIGH, Port B is an output bus and OEB controls the high-impedance state of DB0-DB17. If OEB is HIGH, Port B is

in a high-impedance state. If OE

AB is synchronized to CLKB. In the bypass mode, EFAB HIGH indicates that data DA0-DA17 is available for passing

through. After the data D

AB Register. When PAEAB is HIGH, the A→B FIFO contains more than offset in PAEAB Register. The

AB Register. When PAFAB is HIGH, the A→B FIFO contains less than or equal to the depth minus the

AB Register. The default offset value for PAFAB Register is 8. PAFAB is synchronized to CLKA.

When FFAB is LOW, the A→B FIFO is full and further data writes into Port A are inhibited. When FF

AB

full. FF

FF

is synchronized to CLKA. In bypass mode, FFAB tells Port A that a message is waiting in Port B’s output register. If

AB

is LOW, a bypass message is in the register. If FF

B is LOW while R/WB is HIGH, Port B is in an active (low-impedance) state.

B0-DB17 has been read, EFAB goes LOW.

AB Register is 8. PAEAB is synchronized to CLKB.

AB

is HIGH, Port B has read the message and another message can be

AB

is HIGH, the FIFO is not

written into Port A.

BA is synchronized to CLKA. In the bypass mode, EFBA HIGH indicates that data DB0-DB17 is available for

passing through. After the data D

BA Register. When PAEBA is HIGH, the B→A FIFO contains more than offset in PAEBA Register. The

BA Register. When PAFBA is HIGH, the B→A FIFO contains less than or equal to the depth minus the

BA Register. The default offset value for PAFBA Register is 8. PAFBA is synchronized to CLKB.

A0-DA17 has been read, EFBA goes LOW on the following cycle.

BA Register is 8. PAEBA is synchronized to CLKA.

When FFBA is LOW, the B→A FIFO is full and further data writes into Port B are inhibited. When FFBA is HIGH, the FIFO is

BA

not full. FF

BA

FF

is synchronized to CLKB. In bypass mode, FFBA tells Port B that a message is waiting in Port A’s output register. If

is LOW, a bypass message is in the register. If FFBA is HIGH, Port A has read the message and another message can be

written into Port B.
This flag informs Port B that the synchronous BiFIFO is in bypass mode. When BYPB is LOW, Port A has placed the FIFO into

B

is HIGH, the synchronous BiFIFO passes data into memory. BYPB is synchronized to CLKB.

3

IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Rating Industrial Unit

TERM Terminal Voltage with –0.5 to +7.0 V

V

Respect to Ground

STG Storage Temperature –55 to +125 °C

T

OUT DC Output Current –50 to +50 mA

I

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

INDUSTRIAL TEMPERATURE RANGE

RECOMMENDED DC OPERATING
CONDITIONS

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

CC Supply Voltage 4.5 5.0 5.5 V

V
GND Supply Voltage 0 0 0 V

IH Input High Voltage 2.0 — — V

V

(1)

IL

V

A Operating Temperature -40 — 85 °C

T

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

Input Low Voltage — — 0.8 V

DC ELECTRICAL CHARACTERISTICS

(Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)

IDT72615L
IDT72605L

Industrial

CLK = 20, 25, 35, 50ns

t

Symbol Parameter Min. Typ. Max. Unit

(1)

LI

I

LO

I

OH Output Logic "1" Voltage IOUT = –2mA 2.4 — — V

V

OL Output Logic "0" Voltage IOUT = 8mA — — 0.4 V

V

CC

I

NOTES:

1. Measurements with 0.4V ≤ V

2. OEA, OEB ≥ V

3. Tested with outputs open (I

Input Leakage Current (Any Input) – 1 — 1 µA

(2)

Output Leakage Current –1 0 — 10 µA

(3)

Active Power Supply Current — — 230 mA

IH; 0.4 ≤ VOUT ≤ VCC.

IN ≤ VCC.

OUT = 0). Testing frequency f=20MHz.

CAPACITANCE (TA = +25°C, F = 1.0MHz)

Symbol Parameter Conditions Max. Unit

(2)

IN

C

OUT

C

NOTES:

1. With output deselected.

2. Characterized values, not currently tested.

Input Capacitance VIN = 0V 10 pF

(1,2)

Output Capacitance VOUT = 0V 10 pF

4

IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE

AC TEST CONDITIONS

+5V

In Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns

1.1KΩ

Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 2

D.U.T.

680Ω

30pF*

2704 drw 04

or equivalent circuit

Figure 2. Output Load

* Includes jig and scope capacitances.

AC ELECTRICAL CHARACTERISTICS

(Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)

Industrial

IDT72615L20 IDT72615L25 IDT72615L35 IDT72615L50
IDT72605L20 IDT72605L25 IDT72605L35 IDT72605L50

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit Timing Figures

CLK Clock frequency — 50 — 4 0 — 28 — 20 MHz —

f

CLK Clock cycle time 2 0 — 25 — 35 — 50 — ns 4,5,6,7

t

CLKH Clock HIGH time 8 — 10 — 14 — 20 — ns 4,5,6,7,12,13,14,15

t

CLKL Clock LOW time 8 — 1 0 — 1 4 — 2 0 — ns 4,5,6,7,12,13,14,15

t

RS Reset pulse width 2 0 — 25 — 35 — 5 0 — ns 3

t

RSS Reset setup time 12 — 1 5 — 2 1 — 30 — ns 3

t

RSR Reset recovery time 1 2 — 1 5 — 21 — 3 0 — ns 3

t

RSF Reset to flags in initial state — 27 — 28 — 35 — 50 ns 3

t

A Data access time 3 10 3 1 5 3 21 3 25 ns 5,7,8,9,10,11

t

CS Control signal setup time

t

CH Control signal hold time

t

DS Data setup time 6 — 6 — 8 — 10 — ns 4,6,8,9,10,11

t

DH Data hold time 1 — 1 — 1 — 1 — ns 4,6

t

OE Output Enable LOW to output data valid

t

OLZ Output Enable LOW to data bus at Low-Z

t

OHZ Output Enable HIGH to data bus at High-Z

t

FF Clock to Full Flag time — 1 0 — 15 — 2 1 — 30 ns 4,6,10,11

t

EF Clock to Empty Flag time — 10 — 1 5 — 2 1 — 30 ns 5,7,8,9,10,11

t

PAE Clock to Programmable — 12 — 15 — 2 1 — 3 0 n s 12,14

t

Almost-Empty Flag time

PAF Clock to Programmable — 1 2 — 1 5 — 21 — 30 ns 13,15

t

Almost-Full Flag time

SKEW1 Skew between CLKA & CLKB 10 — 12 — 17 — 2 0 — ns 4,5,6,7,8,9,10,11

t

for Empty/Full Flags

tSKEW2 Skew between CLKA & CLKB 17 — 1 9 — 25 — 34 — ns 4, 7,12,13,14,15

for Programmable Flags

NOTES:

1. Control signals refer to CS

2. Minimum values are guaranteed by design.

(1)

(1)

(2)

(2)

(2)

A, R/WA, ENA, A2, A1, A0, R/WB, ENB.

6 — 6 — 8 — 10 — ns 4,5,6,7,8,9,10,11,

1 — 1 — 1 — 1 — ns 4,5,6,7,10,11,12,

3 10 3 13 3 2 0 3 28 ns 5,7,8,9,10,11

(2)

0 — 0 — 0 — 0 — ns 5,7,8,9,10,11

(2)

3 10 3 13 3 20 3 28 ns 5,7,10,11

12, 13,14,15

13, 14,15

5

IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2

INDUSTRIAL TEMPERATURE RANGE

FUNCTIONAL DESCRIPTION

IDTs SyncBiFIFO is versatile for both multiprocessor and peripheral

applications. Data can be stored or retrieved from two sources simultaneously.

The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. Two Dual-Port FIFO memory arrays are contained in the
SyncBiFIFO; one data buffer for each direction. Each port has its own
independent clock. Data transfers to the I/O registers are gated by the enable
signals. The transfer direction for each port is controlled independently by a
read/write signal. Individual output enable signals control whether the SyncBiFIFO
is driving the data lines of a port or whether those data lines are in a high­impedance state. The processor connected to Port A of the BiFIFO can send
or receive messages directly to the Port B device using the 18-bit bypass path.

The SyncBiFIFO can be used in multiples of 18-bits. In a 36- to 36-bit
configuration, two SyncBiFIFOs operate in parallel. Both devices are pro­grammed simultaneously, 18 data bits to each device. This configuration can
be extended to wider bus widths (54- to 54-bits, 72- to 72-bits, etc.) by adding
more SyncBiFIFOs to the configuration. Figure 1 shows multiple SyncBiFIFOs
configured for multiprocessor communication.

The microprocessor or microcontroller connected to Port A controls all
operations of the SyncBiFIFO. Thus, all Port A interface pins are inputs driven
by the controlling processor. Port B interfaces with a second processor. The
Port B control pins are inputs driven by the second processor.

RESET

Reset is accomplished whenever the Reset (RS) input is taken to a LOW state

A, ENA and ENB HIGH. During reset, both internal read and write

with CS
pointers are set to the first location. A reset is required after power up before a
write operation can take place. The A→B and B→A FIFO Empty Flags (EFAB,

EFBA) and Programmable Almost-Empty flags (PAEAB, PAEBA) will be set to

LOW after tRSF. The A→B and B→A FIFO Full Flags (FFAB, FFBA) and
Programmable Almost- Full flags (PAFAB, PAFBA) will be set to HIGH after tRSF.
After the reset, the offsets of the Almost-Empty flags and Almost- Full flags for the
A→B and B→A FIFO offset default to 8.

PORT A INTERFACE

The SyncBiFIFO is straightforward to use in micro-processor-based
systems because each port has a standard microprocessor control set. Port A
interfaces with microprocessor through the three address pins (A

2-A0) and a

Chip Select CSA pins. When CSA is asserted, A2,A1,A0 and R/WA are used
to select one of six internal resources (Table 1).

With A2=0 and A1=0, A0 determines whether data can be read out of output
register or be written into the FIFO (A0=0), or the data can pass through the
FIFO through the bypass path (A0=1).

2=1, four programmable flags (two A→B FIFO programmable flags

With A
and two B→A FIFO programmable flags) can be selected: the A→B FIFO
Almost-Empty flag Offset (A1=0, A0=0), A→B FIFO Almost-Full flag Offset
(A

1=0, A0=1), B→A FIFO Almost-Empty flag Offset (A1=1, A0=0), B→A FIFO

Almost-Full flag Offset (A1=1, A0=1).

Port A is disabled when CSA is deasserted and data A is in high-impedance
state.

BYPASS PATH

The bypass paths provide direct communication between Port A and Port
B. There are two full 18-bit bypass paths, one in each direction. During a bypass
operation, data is passed directly between the input and output registers, and
the FIFO memory is undisturbed.

Port A initiates and terminates all bypass operations. The bypass flag, BYP
is asserted to inform Port B that a bypass operation is beginning. The bypass
flag state is controlled by the Port A controls, although the BYPB signal is
synchronized to CLKB. So, BYPB is asserted on the next rising edge of CLKB
when A2A1A0=001and CS A is LOW. When Port A returns to normal FIFO mode
(A2A1A0=000 or CSA is HIGH), BYPB is deasserted on the next CLKB rising
edge.

Once the SyncBiFIFO is in bypass mode, all data transfers are controlled
by the standard Port A (R/WA, CLKA, ENA, OEA) and Port B (R/WB, CLKB,

ENB, OEB) interface pins. Each bypass path can be considered as a one word

deep FIFO. Data is held in each input register until it is read. Since the controls

B,

CLK

MICROPROCESSOR

NOTES:

1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration.

2. Control A consists of R/W

A

RAM A

DATA

ADDR, I/0

A, ENA, OEA, CSA, A2, A 1, A0. Control B consists of R/WB, ENB, OEB.

CONTROL

LOGIC

SYSTEM

CLOCK A

Figure 1. 36- to 36-bit Processor Interface Configuration

SYNCBIFIFO

DATA A
CLK

A

CONTROL A

SYNCBIFIFO

DATA A

A

CLK

CONTROL A

IDT

DATA B

CONTROL B

IDT

CONTROL B

6

CLK

DATA B

CLK

B

B

SYSTEM

CLOCK B

CONTROL

LOGIC

CLK

MICROPROCESSOR

B

DATA

ADDR, I/0

RAM B

2704 drw 05