Integrated Device Technology Inc IDT72511L35J, IDT72511L40GB, IDT72511L40JB, IDT72511L50G, IDT72511L50GB Datasheet

Integrated Device Technology, Inc.

PARALLEL BIDIRECTIONAL FIFO
512 x 18 & 1024 x 18

IDT72511
IDT72521

FEATURES:

• Two side-by-side FIFO memory arrays for bidirectional
data transfers

• 512 x 18-Bit - 512 x 18-Bit (IDT72511)

• 1024 x 18-Bit - 1024 x 18-Bit (IDT72521)

• 18-bit data buses on Port A side and Port B side

• Can be configured for 18-to-18-bit or 36-to-36-bit com­munication

• Fast 35ns access time

• Fully programmable standard microprocessor interface

• Built-in bypass path for direct data transfer between two
ports

• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO

• Two programmable flags, Almost-Empty and Almost-Full
for each FIFO

• Programmable flag offset can be set to any depth in the
FIFO

• Any of the eight flags can be assigned to four external
flag pins

• Flexible reread/rewrite capabilities

• Six general-purpose programmable I/O pins

• Standard DMA control pins for data exchange with
peripherals

• 68-pin PGA and PLCC packages

DESCRIPTION:

The IDT72511 and IDT72521 are highly integrated first-in,
first-out memories that enhance processor-to-processor and
processor-to-peripheral communications. IDT BiFIFOs inte­grate two side-by-side memory arrays for data transfers in
two directions.

The BiFIFOs have two ports, A and B, that both have
standard microprocessor interfaces. All BiFIFO operations
are controlled from the 18-bit wide Port A. Port B is also 18
bits wide and can be connected to another processor or a
peripheral controller. The BiFIFOs have a 9-bit bypass path
that allows the device connected to Port A to pass messages
directly to the Port B device.

Ten registers are accessible through Port A, a Com­mand Register, a Status Register, and eight Configuration
Registers.

The IDT BiFIFO has programmable flags. Each FIFO
memory array has four internal flags, Empty, Almost-Empty,
Almost-Full and Full, for a total of eight internal flags. The
Almost-Empty and Almost-Full flag offsets can be set to any
depth through the Configuration Registers. These eight inter­nal flags can be assigned to any of four external flag pins
(FLG

A-FLGD) through one Configuration Register.

Port B has programmable I/O, reread/rewrite and DMA
functions. Six programmable I/O pins are manipulated through

SIMPLIFIED BLOCK DIAGRAM

18-Bit

FIFO

18-bits

Data Data

Port

A

Control

Flags

The IDT logo is a registered trademark of Integrated Device Techology, Inc.

Processor

Interface

A

Programmable

Flag Logic

Bypass

18-Bit

FIFO

Registers

9-bits

Programmable

I/O Logic

Processor

Interface

B

Handshake

Interface

MILITARY AND COMMERCIAL TEMPERATURE RANGES DECEMBER 1995

1996 Integrated Device Technology, Inc. DSC-2668/6

5.32 1

18-bits

Port

B

I/O

Control

DMA

2668 drw 01

IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

two Configuration Registers. The Reread and Rewrite controls
will read or write Port B data blocks multiple times. The
BiFIFO has three pins, REQ, ACK and CLK, to control DMA
transfers from Port B devices.

PIN CONFIGURATIONS

11

10

09

08

07

06

05

04

03

02

01

DB13 DB14

DB17 FLGB FLGD A0 DA15 DA13 DA11

DB12 DB15 FLGA FLGC A1 DA17 DA14 DA12 DB13 PIO4DB11 PIO5

DB10DB9 DA9

DB8GND PIO3

GNDRB

VCCWB VCC

DB16DB7 GND

G68-1

PGA

TOP VIEW

DB6DB5 PIO2

DB4DB3

DB13

DB2

DB1 CLK REQ

DB0 ACK REW GND

RER R/WA

PIO0 DA0 DA2 DA5

PIO1 DA1 DA3

CSA

GND

DA7

DB13

DA4

DA10

DA8

LDRER

DSA

RS

LDREW

DA16

DA6

P

IN 1

DESIGNATOR

ABCDEFGH LKJ

A

0

A

RER

PIO

23456789

CS

R/W

1

GND

REW

J68-1

PLCC

TOP VIEW

35 36 37 38 39 40 41 4342

3433323130292827

0A1

D

A

FLGCFLG

FLG

B

REQ

A

FLG

ACK

B17DB15DB14DB13

D

INDEX

DA5
D

A6

D

A7

DA16

PIO

LDREW

GND

RS

V

CC

DSA

GND

LDRER

PIO

DA8
DA9

D

A10

PIO

1

A1DA0

A2

D

DA4DA3D

10
11
12
13
14

2

15
16
17
18
19
20
21
22

3

23
24
25
26

4

5

A11DA12DA13DA14DA15DA17

D

PIO

PIO

636465666768

CLK

62 61

B0DB1

D

2668 drw 02

D

60

B2

D

59

B3

D

58

B4

D

B5

57

D

56

B6

D

55

B7

D

54

B16

W

53
52
51
50
49
48
47
46
45
44

(R/W )

B

V

CC

R

(DS )

B

GND
GND

D

B8

D

B9

D

B10

D

B11

D

B12

2668 drw 03

B

B

5.32 2

IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Symbol Name I/O Description

DA0-DA17 Data A I/O Data inputs and outputs for the 18-bit Port A bus.

CS

A Chip Select A I Port A is accessed when Chip Select A is LOW.

DS

A Data Strobe

A

R/

W

A Read/Write A I This pin controls the read or write direction of Port A. When CSA is LOW and R/WA is HIGH,

A0, A1 Addresses I When Chip Select A is asserted, A0, A1, and Read/Write A are used to select one of six internal

DB0-DB17 Data B I/O Data inputs and outputs for the 18-bit Port B bus.

R

B (DSB) Read B I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is

W

B (R/WB) Write B I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is

RER

REW

Reread I Loads A→B FIFO Read Pointer with the value of the Reread Pointer when LOW.

Rewrite I Loads B→A FIFO Write Pointer with the value of the Rewrite Pointer when LOW.
LDRER Load Reread I Loads the Reread Pointer with the value of the A→B FIFO Read Pointer when HIGH.
LDREW Load Rewrite I Loads the Rewrite Pointer with the value of the B→A FIFO Write Pointer when HIGH.
REQ Request I When Port B is programmed in peripheral mode, asserting this pin begins a data transfer.

ACK Acknowledge O When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a

CLK Clock I This pin is used to generate timing for ACK,

FLGA­FLG

D

Flags O These four outputs pins can be assigned any one of the eight internal flags in the BiFIFO. Each

PIO0-PIO5 Program-

mable Inputs/
Outputs

RS

Reset I A LOW on this pin will perform a reset of all BiFIFO functions.
VCC Power There are two +5V power pins.
GND Ground There are five Ground pins at 0V.

I Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is

read out of Port A on the falling edge of Data Strobe when Chip Select is LOW.

data is read from Port A on the falling edge of
is written into Port A on the rising edge of

DS

A. When CSA is LOW and R/WA is LOW, data

DS

A.

resources.

programmed to peripheral mode this pin functions as an output. This pin can function as part of
an Intel-style interface (
interface, data is read from Port B on a falling edge of
read on the falling edge of
is Intel-style processor mode. (

R

B) or as part of a Motorola-style interface (DSB). As an Intel-style

B or written on the rising edge of DSB through Port B. The default

DS

R

B as an input).

R

B. As a Motorola-style interface, data is

programmed to peripheral mode this pin functions as an output. This pin can function as part of
an Intel-style interface (
interface, data is written to Port B on a rising edge of
read (R/

W

B = HIGH) or written (R/WB = LOW) to Port B in conjunction with a Data Strobe B

falling or rising edge. The default is Intel-style processor mode (

W

B) or as part of a Motorola-style interface (R/WB). As an Intel-style

W

B. As a Motorola-style interface, data is

W

B as an input.)

Request can be programmed either active HIGH or active LOW.

Request signal. This confirms that a data transfer may begin. Acknowledge can be programmed
either active HIGH or active LOW.

R

B , WB, DSB and R/WB when Port B is in the

peripheral mode.

of the two internal FIFOs (A→B and B→A) has four internal flags: Empty, Almost-Empty,
Almost-Full and Full.

I/O Six general purpose I/O pins. The input or output direction of each pin can be set independently.

2668 tbl 01

5.32 3

IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED BLOCK DIAGRAM

Reread Pointer

Port A

D

A0-DA17

CS
DSA

R/WA

A1
A0

A

Port A

Write Pointer Read Pointer

Load Reread

Control

Reread

Port B

Control

LDRER

LDREW
RER
REW

R

B (DSB) ==

W

B (R/WB) ==

A B FIFO

18

Bypass Path

9

18

Port B

D

B0-DB17

9

B A FIFO

18 18

Read Pointer

Write Pointer

Load Rewrite Rewrite

Rewrite Pointer

Command

Status

Configuration 0
Configuration 1

Configuration 2

FLGA*

FLGB*
FLGC*
FLGD*

16

Programmable

Flag Logic

Configuration 3
Configuration 4
Configuration 5
Configuration 6
Configuration 7

NOTES:

(*) Can be programmed either active high or active low in internal configuration registerers.
(==) Can be programmed through an internal configuration register to be either an input or an output.

Reset

DMA

Control

Programmable

I/O Logic

RS

REQ*
ACK*
CLK

PIO5 ==
PIO4 ==
PIO3 ==
PIO2 ==
PIO1 ==
PIO0 ==

2668 drw 04

5.32 4

IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

IDT’s BiFIFO family is versatile for both multiprocessor
and peripheral applications. Data can be sent through both
FIFO memories concurrently, thus freeing both processors
from laborious direct memory access (DMA) protocols and
frequent interrupts.

Two full 18-bit wide FIFOs are integrated into the IDT
BiFIFO, making simultaneous data exchange possible. Each
FIFO is monitored by separate internal read and write point­ers, so communication is not only bidirectional, it is also
totally independent in each direction. The processor con­nected to Port A of the BiFIFO can send or receive mes­sages directly to the Port B device using the BiFIFO’s 9-bit
bypass path.

The BiFIFO can be used in different bus configurations:
18 bits to 18 bits and 36 bits to 36 bits. One BiFIFO can be
used for the 18- to 18-bit configuration, and two BiFIFOs are
required for 36- to 36-bit configuration. This configuration
can be extended to wider bus widths (54- to 54-bits, 72- to
72-bits, …) by adding more BiFIFOs to the configuration.

The microprocessor or microcontroller connected to Port
A controls all operations of the BiFIFO. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B can be programmed to interface either with a second
processor or a peripheral device. When Port B is programmed
in processor interface mode, the Port B interface pins are
inputs driven by the second processor. If a peripheral device

is connected to the BiFIFO, Port B is programmed to periph­eral interface mode and the interface pins are outputs.

18- to 18-bit Configurations

A single BiFIFO can be configured to connect an 18-bit
processor to another 18-bit processor or an 18-bit peripheral.
The upper BiFIFO shown in each of the Figures 1 and 2 can
be used in 18- to 18-bit configurations for processor and
peripheral interface modes respectively.

36- to 36-bit Configurations

In a 36- to 36-bit configuration, two BiFIFOs operate in
parallel. Both BiFIFOs are programmed simultaneously, 18
data bits to each device. Figures 1 and 2 show multiple
BiFIFOs configured for processor and peripheral interface
modes respectively.

Processor Interface Mode

When a microprocessor or microcontroller is connected to
Port B, all BiFIFOs in the configuration must be programmed
to processor interface mode. In this mode, all Port B inter­face controls are inputs. Both REQ and CLK pins should be
pulled LOW to ensure that the setup and hold time require­ments for these pins are met during reset. Figure 1 shows
the BiFIFO in processor interface mode.

Processor

A

Address

Control

Data

RAM

Logic

Control

36

36-bit bus

18

IDT

BiFIFO

Cntl A Cntl B

ACK
REQ

CLK

Data A Data B

IDT

BiFIFO

Cntl A Cntl B

ACK
REQ

CLK

Data A

Data B

18

Control

36-bit bus

36

Logic

Processor

B

Control

Data

RAM

2668 drw 05

NOTE:

1. 36- to 36-bit processor interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that
and

DS

A;

Cntl B

refers to R/

W

B and

Figure 1. 36-Bit Processor to 36-Bit Processor Configuration

DS

B or RB and WB.

5.32 5

Cntl A

refers to

CS

A, A1, A0, R/WA,

IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

Peripheral Interface Mode

If Port B is connected to a peripheral controller, all
BiFIFOs in the configuration must be programmed in peri­pheral interface mode. In this mode, all the Port B interface
pins are all outputs. To assure fixed high states for

W

B before they are programmed into an output, these two

R

B and

pins should be pulled up to VCC with 10K resistors. Of
course, only one set of Port B interface pins should be used
to control a single peripheral device, while the other interface
pins are all ignored. Figure 2 shows a BiFIFO configuration
connected to a peripheral.

Port A Interface

The BiFIFO is straightforward to use in microprocessor­based systems because each BiFIFO port has a standard
microprocessor control set. Port A has access to six re­sources: the A→B FIFO, the B→A FIFO, the 9-bit direct data
bus (bypass path), the configuration registers, status and
command registers. The Port A Address and Read/Write
pins determine the resource being accessed as shown in
Table 1. Data Strobe is used to move data in and out of the
BiFIFO.

IDT

BiFIFO

When either of the internal FIFOs are accessed, 18 bits of
data are transferred across Port A. Since the bypass path is
only 9 bits wide, the least significant byte (DA0-DA7, DA16) is
used on Port A. All of the registers are 16 bits wide which
means only the data bits (DA0-DA15) are passed by Port A.

Bypass Path

The bypass path acts as a bidirectional bus transceiver
directly between Port A and Port B. The direct connection
requires that the Port A interface pins are inputs and the Port
B interface pins are outputs. The bypass path is 9 bits wide in
an 18- to 18-bit configuration or 18 bits wide in a 36- to 36­bit configuration.

During bypass operations, the BiFIFOs must be pro­grammed into peripheral interface mode. Bit 10 of Configura­tion Register 5 (see Table 10) is set to 1 for peripheral
interface mode.

Command Register

Ten registers are accessible through Port A, a Command
Register, a Status Register, and eight Configuration
Registers.

Processor

Address

Control

Data

RAM

Logic

Control

36

36-bit bus

18

Cntl A Cntl B

ACK

REQ

CLK

Data A Data B

IDT

BiFIFO

Cntl ACntl B

ACK

REQ

CLK

Data A Data B

18

36-bit bus

36

DMA or System

Clock

Peripheral

Controller

Cntl
ACK

REQ
Data

I/O

Data

2668 drw 06

NOTE:

1. 36- to 36-bit peripheral interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that

W

A, and DSA;

Cntl B

refers to R/

Figure 2. 36-Bit Processor to 36-Bit Peripheral Configuration

W

B and DSB or RB and WB.

5.32 6

Cntl A

refers to

CS

A, A1, A0, R/

IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

The Command Register is written by setting

CS

A = 0, A1 =

1, A0 = 1. Commands written into the BiFIFO have a 4-bit
opcode (bit8 – bit 11) and a 3-bit operand (bit 0 – bit 2) as
shown in Figure 3. The commands can be used to reset the
BiFIFO, to select the Configuration Register, to perform intel­ligent reread/rewrite, to set the Port B DMA direction, to set
the Status Register format, and to modify the Port B Read
and Write Pointers. The command opcodes are shown in
Table 2.

The reset command initializes different portions of the
BiFIFO depending on the command operand. Table 3 shows
the reset command operands.

The configuration Register address is set directly by the

COMMAND FORMAT

15 12 11 8 7 3 2 0

X X X X Command Opcode X X X X X Command Operand

Figure 3. Format for Commands Written into Port A

command operands shown in Table 4.

Intelligent reread/rewrite is performed by interchanging
the Port B Read Pointer with the Reread Pointer or by
interchanging the Port B Write Pointer with the Rewrite Pointer.
No command operands are required to perform a reread/
rewrite operation.

When Port B of the BiFIFO is in peripheral mode, the DMA
direction is controlled by the Command Register. Table 5
shows the Port B read/write DMA direction operands.

Two commands are provided to increment the Port B Read
and Write Pointers. No operands are required for these
commands.

2668 tbl 02

5.32 7

IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

Reset

The IDT72511 and IDT72521 have a hardware reset pin
(RS) that resets all BiFIFO functions. A hardware reset re­quires the following four conditions:

RER

and

REW

must be HIGH, LDRER and LDREW must be

LOW, and

DS

A must be HIGH (Figure 9). After a hardware

R

B and WB must be HIGH,

reset, the BiFIFO is in the following state: Configuration
Registers 0-3 are 0000H, Configuration Register 4 is set to
6420H, and Configuration Registers 5, 6 and 7 are 0000H.
Additionally, all the pointers including the Reread and Rewrite
Pointers are set to 0, the DMA direction is set to B→A write,
and the internal DMA request circuitry is cleared (set to its
initial state).

A software reset command can reset A→B pointers and the
B→A pointers to 0 independently or together. The internal

PORT A RESOURCE SELECTION

CS

A A1 A0 Read Write

CS

000
0 0 1 9-bit Bypass Path 9-bit Bypass Path

0 1 0 Configuration

0 1 1 Status Register Command

1 X X Disabled Disabled

B→A FIFO A→B FIFO

Registers

Configuration
Registers

Register

2668 tbl 03

Table 1. Accessing Port A Resources Using

CS

A, A0 and A1

COMMAND OPERATIONS

Command

Opcode Function

0000 Reset BiFIFO (see Table 3)
0001 Select Configuration Register (see Table 4)
0010 Load Reread Pointer with Read Pointer Value
0011 Load Rewrite Pointer with Write Pointer Value
0100 Load Read Pointer with Reread Pointer Value
0101 Load Write Pointer with Rewrite Pointer Value
0110 Set DMA Transfer Direction (see Table 5)
0111 Reserved
1000 Increment A→B FIFO Read Pointer (Port B)
1001 Increment B→A FIFO Write Pointer (Port B)

1010 Reserved
1011 Reserved

2668 tbl 05

Table 2. Functions Performed by Port A Commands

request DMA circuitry can also be reset independently. A
software Reset All command resets all the pointers, the DMA
request circuitry, and sets all the Configuration Registers to
their default condition. Note that a hardware reset is NOT the
same as a software Reset All command. Table 6 shows the
BiFIFO state after the different hardware and software resets

Status Register

The Status Register reports the state of the programmable
flags and the DMA read/write direction. The Status Register
is read by setting

CS

A = 0, A1 = 1, A0 = 1 (see Table 1). See

Table 7 for the Status Register format.

Configuration Registers

The eight Configuration Register formats are shown in

RESET COMMAND FUNCTIONS

Reset

Operands Function

000 No Operation
001 Reset B→A FIFO (Read, Write, and Rewrite

Pointers = 0)

010 Reset A→B FIFO (Read, Write, and Reread

Pointers = 0)

011 Reset B→A and A→B FIFO
100 Reset Internal DMA Request Circuitry
101 No Operation

110 No Operation
111 Reset All

2668 tbl 04

Table 3. Reset Command Functions

SELECT CONFIGURATION REGISTER/
COMMAND FUNCTIONS

Operands Function

000 Select Configuration Register 0
001 Select Configuration Register 1
010 Select Configuration Register 2
011 Select Configuration Register 3
100 Select Configuration Register 4
101 Select Configuration Register 5
110 Select Configuration Register 6
111 Select Configuration Register 7

2668 tbl 06

Table 4. Select Configuration Register Functions.

DMA DIRECTION COMMAND FUNCTIONS

Operands Function

XX0 Write B→A FIFO
XX1 Read A→B FIFO

2668 tbl 07

Table 5. Set DMA Direction Command Functions. Command Only

5.32 8

Operates in Peripheral Interface Mode

IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES

STATE AFTER RESET

Software Reset

Hardware Reset

RS

asserted) B→A(001) A→B(010)

(

Configuration Registers 0-3 0000H ————0000H
Configuration Register 4 6420H ————6420H
Configuration Register 5 0000H ————0000H
Configuration Register 6-7 0000H ————0000H
Status Register format 0 —————
B→A Read, Write, Rewrite Pointers 0 0 — 0 — 0
A→B Read, Write, Reread Pointers 0 — 0 0 — 0
DMA direction B→A write
DMA internal request clear — — — clear clear

Table 6. The BiFIFO State After a Reset Command

—————

B→A and

A→B(011)

Internal
Request

(100) All(111)

2668 tbl 08

Table 8. Configuration Registers 0-3 contain the programmable
flag offsets for the Almost-Empty and Almost-Full flags. These
offsets are set to 0 when a hardware reset or a software Reset
All is applied. Note that Table 8 shows that Configuration
Registers 0-3 are 10 bits wide to accommodate the 1024
locations in each FIFO memory of the IDT7252/520. Only 9
least significant bits are used for the 512 locations of the
IDT7251/510; the most significant bit, bit 9, must be set to 0.

Configuration Register 4 is used to assign the internal flags

to the external flag pins (FLG

A-FLGD). Each external flag pin

is assigned an internal flag based on the four bit codes shown
in Table 9. The default condition for Configuration Register 4
is 6420H as shown in Table 6. The default flag assignments
are: FLGD is assigned B→A

Empty

, FLGB is assigned A→B

Empty

.

Full

, FLGC is assigned B→A

Full

, FLGA is assigned A→B

Configuration Register 5 is a general control register. The

format of Configuration Register 5 is shown in Table 10.

Bit 0 sets the Intel-style interface (

interface (

DS

B, R/WB) for Port B. Bits 2 and 3 redefine Full and

R

B, WB) or Motorola-style

Empty Flags for reread/rewrite data protection.

Bits 4-9 control the DMA interface and are only applicable
in peripheral interface mode. In processor interface mode,
these bits are don’t care states. Bits 4 and 5 set the polarity of
the DMA control pins REQ and ACK respectively. An internal
clock controls all DMA operations. This internal clock is
derived from the external clock (CLK). Bit 9 determines the
internal clock frequency: the internal clock = CLK or the
internal clock = CLK divided by 2. Bit 8 sets whether
and

DS

B are asserted for either one or two internal clocks. Bits

R

B, WB,

6 and 7 set the number of internal clocks between REQ
assertion and ACK assertion. The timing can be from 2 to 5
cycles as shown in Figure 17.

Bit 10 controls Port B processor or peripheral interface
mode. In processor mode, the Port B control pins (

DS

B, R/WB) are inputs and the DMA controls are ignored. In

R

B, WB,

peripheral mode, the Port B control pins are outputs and the
DMA controls are active.

Six PIO pins can be programmed as an input or output
by the corresponding mask bits in Configuration Register 7.
The format of Configuration Register 7 is shown in Figure

5. Each bit of the register set the I/O direction independ­ently. A logic 1 indicates that the corresponding PIO pin is
an output, while a logic 0 indicates that the PIO pin is an
input. This I/O mask register can be read or written.

A programmed output PIO

i pin (i = 0, 1, . . . 5) displays the

data latched in Bit i of Configuration Register 6. A programmed
input PIOi pin allows Port A bus to sample the data on DAi by

reading Configuration Register 6.

STATUS REGISTER FORMAT

Bit Signal

0 Reserved
1 Reserved
2 Reserved
3 DMA Direction
4

5
6
7
8 Reserved

9 Reserved
10 Reserved
11 Reserved
12

13
14
15

A→B Empty Flag
A→B Almost-Empty Flag
B→A Full Flag
B→A Almost-Full Flag

A→B Full Flag
A→B Almost-Full Flag
B→A Empty Flag
B→A Almost-Empty Flag

2668 tbl 09

Table 7. The Status Register Format

5.32 9