Integrated Device Technology Inc IDT72520L25J, IDT72520L35J, IDT72520L50J, IDT72510L25J, IDT72510L35J Datasheet

Integrated Device Technology, Inc.

BUS-MATCHING
BIDIRECTIONAL FIFO
512 x 18-BIT – 1024 x 9-BIT
1024 x 18-BIT – 2048 x 9-BIT

IDT72510
IDT72520

FEATURES:

• Two side-by-side FIFO memory arrays for bidirectional
data transfers

• 512 x 18-Bit – 1024 x 9-Bit (IDT72510)

• 1024 x 18-Bit – 2048 x 9-Bit (IDT72520)

• 18-bit data bus on Port A side and 9-bit data bus on Port
B side

• Can be configured for 18-to-9-bit, 36-to-9-bit, or 36-to-18­bit communication

• Fast 25ns access time

• Fully programmable standard microprocessor interface

• Built-in bypass path for direct data transfer between two
ports

• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO

• Two programmable flags, Almost-Empty and Almost-Full
for each FIFO

• Programmable flag offset can be set to any depth in the
FIFO

• Any of the eight internal flags can be assigned to four
external flag pins

• Flexible reread/rewrite capabilities.

• On-chip parity checking and generation

• Standard DMA control pins for data exchange with
peripherals

• IDT72510 and IDT72520 available in the the 52-pin PLCC
package

DESCRIPTION:

The IDT72510 and IDT72520 are highly integrated first­in, first-out memories that enhance processor-to-processor
and processor-to-peripheral communications. IDT BiFIFOs
integrate two side-by-side memory arrays for data transfers
in two directions.

The BiFIFOs have two ports, A and B, that both have
standard microprocessor interfaces. All BiFIFO operations
are controlled from the 18-bit wide Port A. The BiFIFOs
incorporate bus matching logic to convert the 18-bit wide
memory data paths to the 9-bit wide Port B data bus. The
BiFIFOs have a bypass path that allows the device con­nected to Port A to pass messages directly to the Port B
device.

Ten registers are accessible through Port A, a
Command Register, a Status Register, and eight Configuration
Registers.

The IDT BiFIFOs have programmable flags. Each FIFO
memory array has four internal flags, Empty, Almost-Empty,
Almost-Full and Full, for a total of eight internal flags. The
Almost-Empty and Almost-Full flag offsets can be set to any
depth through the Configuration Registers. These eight inter­nal flags can be assigned to any of four external flag pins
(FLG

A-FLGD) through one Configuration Register.

Port B has parity, reread/rewrite and DMA functions. Par­ity generation and checking can be done by the BiFIFO on
data passing through Port B. The Reread and Rewrite con-

SIMPLIFIED BLOCK DIAGRAM

18-Bit

FIFO

18-bits

Data Data

Port

A

Control

Flags

The IDT logo is a registered trademark of Integrated Device Techology, Inc.

COMMERCIAL TEMPERATURE RANGE DECEMBER 1995

1996 Integrated Device Technology, Inc. DSC-2669/-
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

Processor

Interface

Bypass Path

A

Programmable

Flag Logic

9-bits9-bits

18-Bit

FIFO

Registers

Processor

Interface

B

Handshake

Interface

5.31 1

Port

B

Control

DMA

2669 drw 01

IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE

trols will read or write Port B data blocks multiple times. The
BiFIFOs have three pins, REQ, ACK and CLK, to control
DMA transfers from Port B devices.

PIN CONFIGURATION

A16

DA7

DA6

INDEX

DA10
DA11
DA12
DA13
DA14
DA15

DA17

A0

A1
FLGD
FLGC
FLGB
FLGA

8
9
10

11
12
13

14
15
16
17
18
19
20

DA9

DA8

LDRER

GND

DSAVCC

251 4776543

J52-1

RS

GND

LDREW

52 50 49 48

1

D

DA5

46
45
44

43
42

41
40
39
38
37
36
35
34

DA4
DA3

A2

D

DA1
DA0

CS

R/

W

RER

REW

REQ
ACK
CLK
D

B0

A

A

B8

D

DB7

DB6

DB5

GND

B)

DS

GND

B (

R

PLCC

TOP VIEW

VCC

29 30 31 32 3321 22 23 24 25 26 27 28

B)

B4

W

B (R/

W

D

DB3

DB2

DB1

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IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS

Symbol Name I/O Description

DA0-DA15 Data A I/O Data inputs and outputs for 16 bits of the 18-bit Port A bus.
DA16-DA17 Parity A I/O DA16 is the parity bit for DA0-DA7. DA17 is the parity bit for DA8-

DA15. DA16 and DA17 can be used as two extra data bits if the
parity generate function is disabled.

CS

A Chip Select A I Port A is accessed when Chip Select A is LOW.

DS

A Data Strobe A I Data is written into Port A on the rising edge of Data Strobe when

Chip Select is LOW. Data is read out of Port A on the falling edge of
Data Strobe when Chip Select is LOW.

R/WA Read/Write A I This pin controls the read or write direction of Port A. When CSA is

LOW and R/WA is HIGH, data is read from Port A on the falling edge
of DSA. When CSA is LOW and R/WA is LOW, data is written into
Port A on the rising edge of DSA.

A0, A1 Addresses I When Chip Select A is asserted, A0, A1, and Read/Write A are used

to select one of six internal resources.
DB0-DB7 Data B I / O Data inputs and outputs for 8 bits of the 9-bit Port B bus.
DB8 Parity B I / O DB8 is the parity bit for DB0-DB7. DB8 can be used as a data bit if

the parity generate function is disabled.

R

B (DSB) Read B I or O If Port B is programmed to processor mode, this pin functions as an

input. If Port B is programmed to peripheral mode this pin functions

as an output. This pin can function as part of an Intel-style interface

(RB) or as part of a Motorola-style interface (DSB). As an Intel-style

interface, data is read from Port B on a falling edge of RB. As a

Motorola-style interface, data is read on the falling edge of DSB or

written on the rising edge of DSB through Port B. The Default is Intel-

style processor mode (RB as an input).

W

B (R/WB) Write B I or O If Port B is programmed to processor mode, this pin functions as an

input. If Port B is programmed to peripheral mode this pin functions

as an output. This pin can function as part of an Intel-style interface

(WB) or as part of a Motorola-style interface (R/WB). As an Intel

style interface, data is written to Port B on a rising edge of WB. As

a Motorola-style interface, data is read (R/WB = HIGH) or written (R/

W

B = LOW) to Port B in conjunction with a Data Strobe B falling or

rising edge. The Default is Intel-style processor mode (WB as input).

RER

REW

LDRER Load Reread I Loads the Reread Pointer with the value of the A-to-B FIFO Read

LDREW Load Rewrite I Loads the Rewrite Pointer with the value of the B-to-A FIFO Write

REQ Request I When Port B is programmed in peripheral mode, asserting this pin

Reread I Loads A-to-B FIFO Read Pointer with the value of the Reread

Pointer when LOW.

Rewrite I Loads B-to-A FIFO Write Pointer with the value of the Rewrite

Pointer when LOW.

Pointer when HIGH. This signal is accessible through the Command

Register.

Pointer when HIGH. This signal is accessible through the Command

Register.

begins a data transfer. Request can be programmed either active

HIGH or active LOW.

2669 tbl 01

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IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS

Symbol Name I/O Description

ACK Acknowledge O When Port B is programmed in peripheral mode, Acknowledge is

asserted in response to a Request signal. This confirms that a data

transfer may begin. Acknowledge can be programmed either active

HIGH or active LOW.
CLK Clock I This pin is used to generate timing for ACK, RB, WB,

DS

B and R/WB when Port B is in the peripheral mode.

FLGA-FLGD Flags O These four outputs pins can be assigned to any one of the eight

internal flags in the BiFIFO. Each of the two internal FIFOs (A-to-B

and B-to-A) has four internal flags: Empty, Almost-Empty, Almost-

Full, and Full. If parity checking is enabled, the FLGA pin can also

be assigned as a parity error output.

RS

VCC Power There are two +5V power pins on all four devices.
GND Ground There are four ground pins

Reset I A LOW on this pin will perform a reset of all BiFIFO functions.

Software reset can be achieved through command register.

2669 tbl 02

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IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE

DETAILED BLOCK DIAGRAM

RER

LDRER †

LDREW †

Port B

Control

B) ††

DS

B (

REW

R

B) ††

W

B (R/

W

(DB8)

1

MUX

Read Parity Error

Check

Generate/

Parity

B0-DB7)

(D

Port B

8

†

CLK

ACK*

REQ*

RS

DB0-DB8

2669 drw 04

DMA

Reset

Control

8

Check

Generate/

Parity

MUX

Write

Parity Error

9

Reread

ReRead Pointer

Load Reread

Write Pointer Read Pointer

A→B FIFO

Parity Bit 16

Parity Bit 17

8

Data Bits 0-7

Data Bits 8-15

18

8

Bypass Path

9

A0-DA7,DA16)

(D

Parity Bit 16

Parity Bit 17

B→A FIFO

Register

Odd Byte

Data Bits 0-7

Data Bits 8-15

18

Rewrite

Write Pointer

ReWrite Pointer

Load Rewrite

Read Pointer

Command

Status

Configuration 0

16

A0-DA15)

(D

Configuration 1

Configuration 2

Configuration 3

Configuration 4

Configuration 5

Configuration 6

Configuration 7

A

CS

Port A

Control

A

A

W

DS

R/

Flag Logic

Programmable

A1

A0

FLGA*

FLGB*

FLGC*

Port A

DA0-DA17

5.31 5

FLGD*

NOTES:

(*) Can be programmed either active high or active low in internal configuration registers.

(†) Accessible through internal registers.

(††) Can be programmed through an internal configuration register to be either an input or an output.

2669 drw 03

IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE

FUNCTIONAL DESCRIPTION

IDT’s BiFIFO family is versatile for both multiprocessor

and peripheral applications. Data can be sent through both
FIFO memories concurrently, thus freeing both processors
from laborious direct memory access (DMA) protocols and
frequent interrupts.

Two full 18-bit wide FIFOs are integrated into the IDT

BiFIFO, making simultaneous data exchange possible. Each
FIFO is monitored by separate internal read and write point-

The microprocessor or microcontroller connected to Port
A controls all operations of the BiFIFOs. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B can be programmed to interface either with a second
processor or a peripheral device. When Port B is programmed
in processor interface mode, the Port B interface pins are
inputs driven by the second processor. If a peripheral device
is connected to the BiFIFOs, Port B is programmed to pe­ripheral interface mode and the interface pins are outputs.

ers, so communication is not only bidirectional, it is also
totally independent in each direction. The processor con­nected to Port A of the BiFIFO can send or receive mes­sages directly to the Port B device using the BiFIFO’s 9-bit
bypass path.

The BiFIFOs can be used in three different bus configura­tions: 18 bits to 9 bits, 36 bits to 9 bits and 36 bits to 18 bits.
One BiFIFO can be used for the 18- to 9-bit configuration,

18- to 9-bit Configurations

A single BiFIFO can be configured to connect an 18-bit
processor to another 9-bit processor or a 9-bit peripheral.
Bits 11 and 12 of Configuration Register 5 should be set to
00 for a stand-alone configuration. Figures 1 and 2 show the
BiFIFO in 18- to 9-bit configurations for processor and
peripheral interface modes respectively.

and two BiFIFOs are required for 36- to 9-bit or 36- to 18-bit
configurations. Bits 11 and 12 of Configuration Register 5
determine the BiFIFO configuration (see Table 11 for
Configuration Register 5 format).

36- to 9-bit Configurations

Two BiFIFOs can be hooked together to create a 36-bit to
9-bit configuration. This means that a 36-bit processor can

36-BIT PROCESSOR to 18-BIT PROCESSOR CONFIGURATION

Processor

A

Address

Control

Data

RAM

Logic

Control

36

36-bit bus

18

IDT

BiFIFO

(Stand-Alone)

Cntl A Cntl B

ACK
REQ

CLK

Data A Data B

IDT

BiFIFO

(Stand-Alone)

Cntl A Cntl B

ACK
REQ

CLK

Data B

Data A

9

18-bit bus

Logic

Control

18

Processor

B

Control

Data

RAM

2669 drw 04

NOTE:

1. Upper BiFIFO only is used in 18- to 9-bit configuration. Note that
and

W

B.

Figure 1. 36- to 18-Bit Processor Interface Configuration

Cntl A

refers to

5.31 6

CS

A, A1, A0, R/WA and DSA;

Cntl B

refers to R/

W

B and DSB or RB

IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE

36-BIT PROCESSOR to 18-BIT PERIPHERAL CONFIGURATION

IDT

BiFIFO

(Stand-Alone)

Cntl A Cntl B

ACK

Processor

Address

Control

Data

RAM

Logic

Control

36

36-bit bus

18

REQ
CLK

Data B

Data A

IDT

BiFIFO

(Stand-Alone)

Cntl A Cntl B

ACK
REQ
CLK

Data A Data B

18

18-bit bus

9

DMA or System

Clock

Peripheral
Controller

Cntl
ACK

REQ

Data

I/O

Data

2669 drw 05

NOTE:

1. Upper BiFIFO only is used in 18- to 9-bit configuration. Note that
and

W

B.

Figure 2. 36- to 18-Bit Peripheral Interface Configuration

Cntl A

talk to a 9-bit processor or a 9-bit peripheral. Both BiFIFOs
are programmed simultaneously through Port A by placing
one command word on the most significant 16 data bits and
one command word on the least significant 16 data bits
(parity bits should be ignored).

One BiFIFO must be programmed as the master device
and the other BiFIFO is the slave device. Bits 11 and 12 of
Configuration Register 5 are set to 10 for the slave device
and 11 for the master device. The first two 9-bit words on
Port B are read from or written to the slave device and the
next two 9-bit words go to the master device.

When both BiFIFOs are in peripheral interface mode, the
Port B interface pins of the master device are outputs and
this BiFIFO controls the bus. The Port B interface pins of the
slave device are inputs driven by the master BiFIFO. Two
BiFIFOs are connected in Figure 4 to create a 36- to 9-bit
peripheral interface.

The two BiFIFOs shown in Figure 3 are configured to
connect a 36-bit processor to a 9-bit processor.

36- to 18-bit Configurations

In a 36- to 18-bit configuration, two BiFIFOs operate in
parallel. Both BiFIFOs are programmed simultaneously, 16
data bits to each device with the 4 parity bits ignored.

Both BiFIFOs must be programmed into stand-alone mode
for a 36-bit processor to communicate with an 18-bit proces­sor or an 18-bit peripheral. This means that bits 11 and 12 of

refers to

CS

A, A1, A0, R/

W

A and

DS

A;

Cntl B

refers to R/

W

B and DSB or RB

Configuration Register 5 must be set to 00.

This configuration can be extended to wider bus widths
(54- to 27-bits, 72- to 36-bits, …) by adding more BiFIFOs to
the configuration. Figures 1 and 2 show multiple BiFIFOs
configured for processor and peripheral interface modes
respectively.

Processor Interface Mode

When a microprocessor or microcontroller is connected to
Port B, all BiFIFOs in the configuration must be programmed
to processor interface mode. In this mode, all Port B interface
controls are inputs. Both REQ and CLK pins should be pulled
LOW to ensure that the set-up and hold time requirements for
these pins are met during reset. Figures 1 and 3 show
BiFIFOs in processor interface mode.

Peripheral Interface Mode

If Port B is connected to a peripheral controller, all BiFIFOs
in the configuration must be programmed in the peripheral
interface mode. To assure fixed high states for

R

B and WB

before they are programmed into an output, both pins should
be pulled-up to V

CC with 10K resistors.

If the BiFIFOs are in stand-alone configuration mode
(18- to 9-bit, 36- to 18-bit, …), then the Port B interface pins are
all outputs. Of course, only one set of Port B interface pins
should be used to control a single peripheral device, while the
other interface pins are all ignored. Figure 2 shows stand-

5.31 7

IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE

alone configuration BiFIFOs connected to a peripheral.

In a 36- to 9-bit configuration, the master device controls
the bus. The Port B interface pins of the master device are
outputs and the interface pins of the slave device are inputs.
A 36- to 9-bit configuration of two BiFIFOs connected to a
peripheral is shown in Figure 4.

sources: the A→B FIFO, the B→A FIFO, the 9-bit direct data
bus (bypass path), the configuration registers, status and
command registers. The Port A Address and Read/Write pins
determine the resource being accessed as shown in Table 1.
Data Strobe is used to move data in and out of the BiFIFO.

When either of the internal FIFOs are accessed 18 bits of

data are transferred across Port A. Since the bypass path is

Port A Interface

The BiFIFO is straightforward to use in microprocessor­based systems because each BiFIFO port has a standard
microprocessor control set. Port A has access to six re-

only 9 bits wide, the least significant byte with parity
(DA0-DA7, DA16) is used on Port A. All of the registers are 16
bits wide which means only the data bits (DA0-DA15) are
passed by Port A.

36-BIT PROCESSOR to 9-BIT PROCESSOR CONFIGURATION

IDT

BiFIFO

(Master)

Cntl A Cntl B

ACK
REQ
CLK

Data A Data B

Processor

A

Address

Control

Logic

Control

Logic

Control

Processor

B

Control

NOTE:

1.

Cntl A

refers to

Data

RAM

CS

A, A1, A0, R/WA and DSA;

IDT

BiFIFO

36-bit bus

18

Figure 3. 36- to 9-Bit Processor Interface Configuration

Cntl B

refers to R/

(Slave)

Cntl A

Data A Data B

W

Cntl B

ACK
REQ
CLK

B and DSB or RB and WB.

9-bit bus

Data

RAM

2669 drw 06

5.31 8

IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE

36-BIT PROCESSOR to 9-BIT PERIPHERAL CONFIGURATION

IDT

BiFIFO

(Master)

Cntl A Cntl B

ACK

Processor

Address

Control

Data

RAM

Logic

Control

36-bit bus

18

REQ
CLK

Data A Data B

IDT

BiFIFO

(Slave)

Cntl A Cntl B

ACK
REQ
CLK

Data A Data B

9-bit bus

DMA or
System

Clock

Peripheral

Controller

Cntl
ACK

REQ

Data

Data

I/O

2669 drw 07

NOTE:

Cntl A

1.

refers to

CS

A, A1, A0, R/WA and DSA;

Figure 4. 36- to 9-Bit Peripheral Interface Configuration

Cntl B

refers to R/

W

B and DSB or RB and WB.

5.31 9

IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO COMMERCIAL TEMPERATURE RANGE

PORT A RESOURCES COMMAND OPERATIONS

CS

CS

A1 A0 Read Write

A

000
0 0 1 9-bit Bypass Path 9-bit Bypass Path

0 1 0 Configuration

0 1 1 Status Register Command Register
1 X X Disabled Disabled

Table 1. Accessing Port A Resources Using

B→A FIFO A→B FIFO

Registers

Configuration

Registers

CS

A, A0, and A1

CS

2669 tbl 03

Bypass Path

The bypass path acts as a bidirectional bus transceiver
directly between Port A and Port B. The direct connection
requires that the Port A interface pins are inputs and the Port
B interface pins are outputs. The bypass path is 9 bits wide in
an 18- to 9-bit configuration or in a 36- to 9-bit configuration.
Only in the 36- to 18-bit configuration is the bypass path 18 bits
wide.

During bypass operations, the BiFIFOs must be pro­grammed into peripheral interface mode. Bit 10 of Configura­tion Register 5 (see Table 11) is set to 1 for peripheral interface
mode. In a 36- to 9-bit configuration, both Port B data buses
will be active. Data written into Port A will appear on both
master and slave Port B buses concurrently. To avoid Port B
bus contention, the data on D

A0-DA7 and DA16 of both BiFIFOs

should be exactly the same. Data read from Port A will appear
on pins DA0-DA7 and DA16 of both BiFIFOs within the same 36­bit word.

Command Register

Ten registers are accessible through Port A, a Command
Register, a Status Register, and eight Configuration Registers.

The Command Register is written by setting

CS

A = 0, A1 =

1, A0 = 1. Commands written into the BiFIFO have a 4-bit
opcode (bit 8 – bit 11) and a 3-bit operand (bit 0 – bit 2) as
shown in Figure 5. The commands can be used to reset the
BiFIFO, to select the Configuration Register, to perform intel­ligent reread/rewrite, to set the Port B DMA direction, to set the
Status Register format, to modify the Port B Read and Write
Pointers, and to clear Port B parity errors. The command
opcodes are shown in Table 2.

The reset command initializes different portions of the
BiFIFO depending on the command operand. Table 3 shows
the reset command operands.

The Configuration Register address is set directly by the
command operands shown in Table 4.

Intelligent reread/rewrite is performed by changing the Port
B Read Pointer with the Reread Pointer or by changing the

Command

Opcode

0000 Reset BiFIFO (see Table 3)
0001 Select Configuration Register (see Table 4)
0010 Load Reread Pointer with Read Pointer Value
0011 Load Rewrite Pointer with Write Pointer Value
0100 Load Read Pointer with Reread Pointer Value
0101 Load Write Pointer with Rewrite Pointer Value
0110 Set DMA Transfer Direction (see Table 5)
0111 Set Status Register Format (see Table 6)
1000

1001

1010 Clear Write Parity Error Flag
1011 Clear Read Parity Error Flag

Increment in byte for A→B FIFO Read Pointer
(Port B)

Increment in byte for B→A FIFO Write Pointer
(Port B)

Function

2669 tbl 04

Table 2. Functions Performed by Port A Commands

Port B Write Pointer with the Rewrite Pointer. No command
operands are required to perform a reread/rewrite operation.

When Port B of the BiFIFO is in peripheral mode, the DMA
direction is controlled by the Command Register. Table 5
shows the Port B read/write DMA direction operands.

The BiFIFO supports two Status Register formats. Status
Register format 1 gives all the internal flag status, while Status
Register format 0 provides the data in the Odd Byte Register.
Table 6 gives the operands for selecting the appropriate
Status Register format. See Table 8 for the details of the two
Status Register formats.

Two commands are provided to increment the Port B Read
and Write Pointers in case reread/rewrite is performed.
Incrementing the pointers guarantees that pointers will be on
a word boundary when an odd number of bytes is transmitted
through Port B. No operands are required for these commands.

When parity check errors occur on Port B, a clear parity
error command is needed to remove the parity error. There are
no operands for these commands.

Reset

The IDT72510 and IDT72520 have a hardware reset pin
(RS) that resets all BiFIFO functions. A hardware reset re­quires the following four conditions:

RER

and

REW

must be HIGH, LDRER and LDREW must be

LOW, and

DS

A must be HIGH (Figure 9). After a hardware

R

B and WB must be HIGH,

reset, the BiFIFO is in the following state: Configuration
Registers 0-3 are 0000H, Configuration Register 4 is set to

COMMAND FORMAT

15 12 11 8 7 3 2 0

X X X X Command Opcode XXXXXCommand Operand

Figure 5. Format for Commands Written into Port A

5.31 10

2669 tbl 05